MdeModulePkg/Universal/CapsulePei/Capsule.h

   1 /** @file
   2
   3 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
   4
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions
   7 of the BSD License which accompanies this distribution.  The
   8 full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef _CAPSULE_PEIM_H_
  17 #define _CAPSULE_PEIM_H_
  18
  19 #include <PiPei.h>
  20 #include <Uefi/UefiSpec.h>
  21
  22 #include <Ppi/Capsule.h>
  23 #include <Ppi/LoadFile.h>
  24 #include <Ppi/ReadOnlyVariable2.h>
  25 #include <Guid/CapsuleVendor.h>
  26
  27 #include <Library/DebugLib.h>
  28 #include <Library/PeimEntryPoint.h>
  29 #include <Library/PeiServicesLib.h>
  30 #include <Library/BaseMemoryLib.h>
  31 #include <Library/HobLib.h>
  32 #include <Library/PeiServicesTablePointerLib.h>
  33 #include <Library/PrintLib.h>
  34 #include <Library/PeCoffLib.h>
  35 #include <Library/PeCoffGetEntryPointLib.h>
  36 #include <Library/PcdLib.h>
  37 #include <Library/ReportStatusCodeLib.h>
  38 #include <Library/DebugAgentLib.h>
  39 #include <IndustryStandard/PeImage.h>
  40 #include "Common/CommonHeader.h"
  41
  42 #ifdef MDE_CPU_IA32
  43
  44 #pragma pack(1)
  45
  46 //
  47 // Page-Map Level-4 Offset (PML4) and
  48 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  49 //
  50
  51 typedef union {
  52   struct {
  53     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  54     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  55     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  56     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  57     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  58     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  59     UINT64  Reserved:1;               // Reserved
  60     UINT64  MustBeZero:2;             // Must Be Zero
  61     UINT64  Available:3;              // Available for use by system software
  62     UINT64  PageTableBaseAddress:40;  // Page Table Base Address
  63     UINT64  AvabilableHigh:11;        // Available for use by system software
  64     UINT64  Nx:1;                     // No Execute bit
  65   } Bits;
  66   UINT64    Uint64;
  67 } PAGE_MAP_AND_DIRECTORY_POINTER;
  68
  69 //
  70 // Page Table Entry 2MB
  71 //
  72 typedef union {
  73   struct {
  74     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  75     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
  76     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
  77     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
  78     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
  79     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
  80     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
  81     UINT64  MustBe1:1;                // Must be 1
  82     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  83     UINT64  Available:3;              // Available for use by system software
  84     UINT64  PAT:1;                    //
  85     UINT64  MustBeZero:8;             // Must be zero;
  86     UINT64  PageTableBaseAddress:31;  // Page Table Base Address
  87     UINT64  AvabilableHigh:11;        // Available for use by system software
  88     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
  89   } Bits;
  90   UINT64    Uint64;
  91 } PAGE_TABLE_ENTRY;
  92
  93 //
  94 // Page Table Entry 1GB
  95 //
  96 typedef union {
  97   struct {
  98     UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory
  99     UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write
 100     UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User
 101     UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching
 102     UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached
 103     UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)
 104     UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page
 105     UINT64  MustBe1:1;                // Must be 1
 106     UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 107     UINT64  Available:3;              // Available for use by system software
 108     UINT64  PAT:1;                    //
 109     UINT64  MustBeZero:17;            // Must be zero;
 110     UINT64  PageTableBaseAddress:22;  // Page Table Base Address
 111     UINT64  AvabilableHigh:11;        // Available for use by system software
 112     UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution
 113   } Bits;
 114   UINT64    Uint64;
 115 } PAGE_TABLE_1G_ENTRY;
 116
 117 #pragma pack()
 118
 119 typedef
 120 EFI_STATUS
 121 (*COALESCE_ENTRY) (
 122   IN EFI_PEI_SERVICES                **PeiServices,
 123   IN EFI_CAPSULE_BLOCK_DESCRIPTOR    *BlockList,
 124   IN OUT VOID                        **MemoryBase,
 125   IN OUT UINTN                       *MemorySize
 126   );
 127
 128 #endif
 129
 130 #endif