MdePkg/Include/IndustryStandard/Pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   This file includes the definitions in the following specifications,
   5     PCI Local Bus Specification, 2.0
   6     PCI-to-PCI Bridge Architecture Specification,
   7     PC Card Standard, 8.0
   8
   9   Copyright (c) 2006 - 2008, Intel Corporation
  10   All rights reserved. This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18 **/
  19
  20 #ifndef _PCI22_H_
  21 #define _PCI22_H_
  22
  23 #define PCI_MAX_SEGMENT 0
  24 #define PCI_MAX_BUS     255
  25 #define PCI_MAX_DEVICE  31
  26 #define PCI_MAX_FUNC    7
  27
  28
  29 typedef struct {
  30   UINT16  VendorId;
  31   UINT16  DeviceId;
  32   UINT16  Command;
  33   UINT16  Status;
  34   UINT8   RevisionID;
  35   UINT8   ClassCode[3];
  36   UINT8   CacheLineSize;
  37   UINT8   LatencyTimer;
  38   UINT8   HeaderType;
  39   UINT8   BIST;
  40 } PCI_DEVICE_INDEPENDENT_REGION;
  41
  42 typedef struct {
  43   UINT32  Bar[6];
  44   UINT32  CISPtr;
  45   UINT16  SubsystemVendorID;
  46   UINT16  SubsystemID;
  47   UINT32  ExpansionRomBar;
  48   UINT8   CapabilityPtr;
  49   UINT8   Reserved1[3];
  50   UINT32  Reserved2;
  51   UINT8   InterruptLine;
  52   UINT8   InterruptPin;
  53   UINT8   MinGnt;
  54   UINT8   MaxLat;
  55 } PCI_DEVICE_HEADER_TYPE_REGION;
  56
  57 typedef struct {
  58   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  59   PCI_DEVICE_HEADER_TYPE_REGION Device;
  60 } PCI_TYPE00;
  61
  62 ///
  63 /// defined in PCI-to-PCI Bridge Architecture Specification
  64 ///
  65 typedef struct {
  66   UINT32  Bar[2];
  67   UINT8   PrimaryBus;
  68   UINT8   SecondaryBus;
  69   UINT8   SubordinateBus;
  70   UINT8   SecondaryLatencyTimer;
  71   UINT8   IoBase;
  72   UINT8   IoLimit;
  73   UINT16  SecondaryStatus;
  74   UINT16  MemoryBase;
  75   UINT16  MemoryLimit;
  76   UINT16  PrefetchableMemoryBase;
  77   UINT16  PrefetchableMemoryLimit;
  78   UINT32  PrefetchableBaseUpper32;
  79   UINT32  PrefetchableLimitUpper32;
  80   UINT16  IoBaseUpper16;
  81   UINT16  IoLimitUpper16;
  82   UINT8   CapabilityPtr;
  83   UINT8   Reserved[3];
  84   UINT32  ExpansionRomBAR;
  85   UINT8   InterruptLine;
  86   UINT8   InterruptPin;
  87   UINT16  BridgeControl;
  88 } PCI_BRIDGE_CONTROL_REGISTER;
  89
  90 typedef struct {
  91   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  92   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
  93 } PCI_TYPE01;
  94
  95 typedef union {
  96   PCI_TYPE00  Device;
  97   PCI_TYPE01  Bridge;
  98 } PCI_TYPE_GENERIC;
  99
 100 ///
 101 /// CardBus Conroller Configuration Space, defined in PC Card Standard. 8.0
 102 ///
 103 typedef struct {
 104   UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
 105   UINT8   Cap_Ptr;
 106   UINT8   Reserved;
 107   UINT16  SecondaryStatus;      ///< Secondary Status
 108   UINT8   PciBusNumber;         ///< PCI Bus Number
 109   UINT8   CardBusBusNumber;     ///< CardBus Bus Number
 110   UINT8   SubordinateBusNumber; ///< Subordinate Bus Number
 111   UINT8   CardBusLatencyTimer;  ///< CardBus Latency Timer
 112   UINT32  MemoryBase0;          ///< Memory Base Register 0
 113   UINT32  MemoryLimit0;         ///< Memory Limit Register 0
 114   UINT32  MemoryBase1;
 115   UINT32  MemoryLimit1;
 116   UINT32  IoBase0;
 117   UINT32  IoLimit0;             ///< I/O Base Register 0
 118   UINT32  IoBase1;              ///< I/O Limit Register 0
 119   UINT32  IoLimit1;
 120   UINT8   InterruptLine;        ///< Interrupt Line
 121   UINT8   InterruptPin;         ///< Interrupt Pin
 122   UINT16  BridgeControl;        ///< Bridge Control
 123 } PCI_CARDBUS_CONTROL_REGISTER;
 124
 125 //
 126 // Definitions of PCI class bytes and manipulation macros.
 127 //
 128 #define PCI_CLASS_OLD                 0x00
 129 #define   PCI_CLASS_OLD_OTHER           0x00
 130 #define   PCI_CLASS_OLD_VGA             0x01
 131
 132 #define PCI_CLASS_MASS_STORAGE        0x01
 133 #define   PCI_CLASS_MASS_STORAGE_SCSI   0x00
 134 #define   PCI_CLASS_MASS_STORAGE_IDE    0x01
 135 #define   PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 136 #define   PCI_CLASS_MASS_STORAGE_IPI    0x03
 137 #define   PCI_CLASS_MASS_STORAGE_RAID   0x04
 138 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
 139
 140 #define PCI_CLASS_NETWORK             0x02
 141 #define   PCI_CLASS_NETWORK_ETHERNET    0x00
 142 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
 143 #define   PCI_CLASS_NETWORK_FDDI        0x02
 144 #define   PCI_CLASS_NETWORK_ATM         0x03
 145 #define   PCI_CLASS_NETWORK_ISDN        0x04
 146 #define   PCI_CLASS_NETWORK_OTHER       0x80
 147
 148 #define PCI_CLASS_DISPLAY             0x03
 149 #define   PCI_CLASS_DISPLAY_VGA         0x00
 150 #define     PCI_IF_VGA_VGA                0x00
 151 #define     PCI_IF_VGA_8514               0x01
 152 #define   PCI_CLASS_DISPLAY_XGA         0x01
 153 #define   PCI_CLASS_DISPLAY_3D          0x02
 154 #define   PCI_CLASS_DISPLAY_OTHER       0x80
 155 #define   PCI_CLASS_DISPLAY_GFX         0x80
 156
 157 #define PCI_CLASS_MEDIA               0x04
 158 #define   PCI_CLASS_MEDIA_VIDEO         0x00
 159 #define   PCI_CLASS_MEDIA_AUDIO         0x01
 160 #define   PCI_CLASS_MEDIA_TELEPHONE     0x02
 161 #define   PCI_CLASS_MEDIA_OTHER         0x80
 162
 163 #define PCI_CLASS_MEMORY_CONTROLLER   0x05
 164 #define   PCI_CLASS_MEMORY_RAM          0x00
 165 #define   PCI_CLASS_MEMORY_FLASH        0x01
 166 #define   PCI_CLASS_MEMORY_OTHER        0x80
 167
 168 #define PCI_CLASS_BRIDGE              0x06
 169 #define   PCI_CLASS_BRIDGE_HOST         0x00
 170 #define   PCI_CLASS_BRIDGE_ISA          0x01
 171 #define   PCI_CLASS_BRIDGE_EISA         0x02
 172 #define   PCI_CLASS_BRIDGE_MCA          0x03
 173 #define   PCI_CLASS_BRIDGE_P2P          0x04
 174 #define     PCI_IF_BRIDGE_P2P             0x00
 175 #define     PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01
 176 #define   PCI_CLASS_BRIDGE_PCMCIA       0x05
 177 #define   PCI_CLASS_BRIDGE_NUBUS        0x06
 178 #define   PCI_CLASS_BRIDGE_CARDBUS      0x07
 179 #define   PCI_CLASS_BRIDGE_RACEWAY      0x08
 180 #define   PCI_CLASS_BRIDGE_OTHER        0x80
 181 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 182
 183 #define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
 184 #define   PCI_SUBCLASS_SERIAL           0x00
 185 #define     PCI_IF_GENERIC_XT             0x00
 186 #define     PCI_IF_16450                  0x01
 187 #define     PCI_IF_16550                  0x02
 188 #define     PCI_IF_16650                  0x03
 189 #define     PCI_IF_16750                  0x04
 190 #define     PCI_IF_16850                  0x05
 191 #define     PCI_IF_16950                  0x06
 192 #define   PCI_SUBCLASS_PARALLEL         0x01
 193 #define     PCI_IF_PARALLEL_PORT          0x00
 194 #define     PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 195 #define     PCI_IF_ECP_PARALLEL_PORT      0x02
 196 #define     PCI_IF_1284_CONTROLLER        0x03
 197 #define     PCI_IF_1284_DEVICE            0xFE
 198 #define   PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 199 #define   PCI_SUBCLASS_MODEM            0x03
 200 #define     PCI_IF_GENERIC_MODEM          0x00
 201 #define     PCI_IF_16450_MODEM            0x01
 202 #define     PCI_IF_16550_MODEM            0x02
 203 #define     PCI_IF_16650_MODEM            0x03
 204 #define     PCI_IF_16750_MODEM            0x04
 205 #define   PCI_SUBCLASS_SCC_OTHER          0x80
 206
 207 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 208 #define   PCI_SUBCLASS_PIC              0x00
 209 #define     PCI_IF_8259_PIC               0x00
 210 #define     PCI_IF_ISA_PIC                0x01
 211 #define     PCI_IF_EISA_PIC               0x02
 212 #define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
 213 #define     PCI_IF_APIC_CONTROLLER2       0x20
 214 #define   PCI_SUBCLASS_DMA              0x01
 215 #define     PCI_IF_8237_DMA               0x00
 216 #define     PCI_IF_ISA_DMA                0x01
 217 #define     PCI_IF_EISA_DMA               0x02
 218 #define   PCI_SUBCLASS_TIMER            0x02
 219 #define     PCI_IF_8254_TIMER             0x00
 220 #define     PCI_IF_ISA_TIMER              0x01
 221 #define     PCI_IF_EISA_TIMER             0x02
 222 #define   PCI_SUBCLASS_RTC              0x03
 223 #define     PCI_IF_GENERIC_RTC            0x00
 224 #define     PCI_IF_ISA_RTC                0x00
 225 #define   PCI_SUBCLASS_PNP_CONTROLLER   0x04    ///< HotPlug Controller
 226 #define   PCI_SUBCLASS_PERIPHERAL_OTHER 0x80
 227
 228 #define PCI_CLASS_INPUT_DEVICE        0x09
 229 #define   PCI_SUBCLASS_KEYBOARD         0x00
 230 #define   PCI_SUBCLASS_PEN              0x01
 231 #define   PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 232 #define   PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 233 #define   PCI_SUBCLASS_GAMEPORT         0x04
 234 #define     PCI_IF_GAMEPORT               0x00
 235 #define     PCI_IF_GAMEPORT1              0x01
 236 #define   PCI_SUBCLASS_INPUT_OTHER      0x80
 237
 238 #define PCI_CLASS_DOCKING_STATION     0x0A
 239
 240 #define PCI_CLASS_PROCESSOR           0x0B
 241 #define   PCI_SUBCLASS_PROC_386         0x00
 242 #define   PCI_SUBCLASS_PROC_486         0x01
 243 #define   PCI_SUBCLASS_PROC_PENTIUM     0x02
 244 #define   PCI_SUBCLASS_PROC_ALPHA       0x10
 245 #define   PCI_SUBCLASS_PROC_POWERPC     0x20
 246 #define   PCI_SUBCLASS_PROC_MIPS        0x30
 247 #define   PCI_SUBCLASS_PROC_CO_PORC     0x40 ///< Co-Processor
 248
 249 #define PCI_CLASS_SERIAL              0x0C
 250 #define   PCI_CLASS_SERIAL_FIREWIRE     0x00
 251 #define     PCI_IF_1394                   0x00
 252 #define     PCI_IF_1394_OPEN_HCI          0x10
 253 #define   PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 254 #define   PCI_CLASS_SERIAL_SSA          0x02
 255 #define   PCI_CLASS_SERIAL_USB          0x03
 256 #define     PCI_IF_UHCI                   0x00
 257 #define     PCI_IF_OHCI                   0x10
 258 #define     PCI_IF_USB_OTHER              0x80
 259 #define     PCI_IF_USB_DEVICE             0xFE
 260 #define   PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 261 #define   PCI_CLASS_SERIAL_SMB          0x05
 262
 263 #define PCI_CLASS_WIRELESS            0x0D
 264 #define   PCI_SUBCLASS_IRDA             0x00
 265 #define   PCI_SUBCLASS_IR               0x01
 266 #define   PCI_SUBCLASS_RF               0x02
 267 #define   PCI_SUBCLASS_WIRELESS_OTHER   0x80
 268
 269 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 270
 271 #define PCI_CLASS_SATELLITE           0x0F
 272 #define   PCI_SUBCLASS_TV               0x01
 273 #define   PCI_SUBCLASS_AUDIO            0x02
 274 #define   PCI_SUBCLASS_VOICE            0x03
 275 #define   PCI_SUBCLASS_DATA             0x04
 276
 277 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
 278 #define   PCI_SUBCLASS_NET_COMPUT       0x00
 279 #define   PCI_SUBCLASS_ENTERTAINMENT    0x10
 280 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
 281
 282 #define PCI_CLASS_DPIO                0x11
 283 #define   PCI_SUBCLASS_DPIO             0x00
 284 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
 285
 286 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 287 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 288 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 289
 290 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 291 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
 292 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
 293 #define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
 294 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 295 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 296 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 297 #define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
 298 #define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
 299 #define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
 300 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
 301 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
 302 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
 303 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 304
 305 //
 306 // the definition of Header Type
 307 //
 308 #define HEADER_TYPE_DEVICE            0x00
 309 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 310 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 311 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 312 //
 313 // Mask of Header type
 314 //
 315 #define HEADER_LAYOUT_CODE            0x7f
 316
 317 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 318 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 319 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 320
 321 ///
 322 /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
 323 ///
 324 #define PCI_BRIDGE_ROMBAR             0x38
 325
 326 #define PCI_MAX_BAR                   0x0006
 327 #define PCI_MAX_CONFIG_OFFSET         0x0100
 328
 329 #define PCI_VENDOR_ID_OFFSET                        0x00
 330 #define PCI_DEVICE_ID_OFFSET                        0x02
 331 #define PCI_COMMAND_OFFSET                          0x04
 332 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 333 #define PCI_REVISION_ID_OFFSET                      0x08
 334 #define PCI_CLASSCODE_OFFSET                        0x09
 335 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 336 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 337 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 338 #define PCI_BIST_OFFSET                             0x0F
 339 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 340 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 341 #define PCI_SVID_OFFSET                             0x2C ///< SubSystem Vendor id
 342 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 343 #define PCI_SID_OFFSET                              0x2E ///< SubSystem ID
 344 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 345 #define PCI_EXPANSION_ROM_BASE                      0x30
 346 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 347 #define PCI_INT_LINE_OFFSET                         0x3C ///< Interrupt Line Register
 348 #define PCI_INT_PIN_OFFSET                          0x3D ///< Interrupt Pin Register
 349 #define PCI_MAXGNT_OFFSET                           0x3E ///< Max Grant Register
 350 #define PCI_MAXLAT_OFFSET                           0x3F ///< Max Latency Register
 351
 352 //
 353 // defined in PCI-to-PCI Bridge Architecture Specification
 354 //
 355 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 356 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 357 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 358 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 359 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 360
 361 ///
 362 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
 363 ///
 364 #define PCI_INT_LINE_UNKNOWN                        0xFF
 365
 366 typedef union {
 367   struct {
 368     UINT32  Reg : 8;
 369     UINT32  Func : 3;
 370     UINT32  Dev : 5;
 371     UINT32  Bus : 8;
 372     UINT32  Reserved : 7;
 373     UINT32  Enable : 1;
 374   } Bits;
 375   UINT32  Uint32;
 376 } PCI_CONFIG_ACCESS_CF8;
 377
 378 #define EFI_PCI_COMMAND_IO_SPACE                        BIT0   ///< 0x0001
 379 #define EFI_PCI_COMMAND_MEMORY_SPACE                    BIT1   ///< 0x0002
 380 #define EFI_PCI_COMMAND_BUS_MASTER                      BIT2   ///< 0x0004
 381 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   BIT3   ///< 0x0008
 382 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     BIT4   ///< 0x0010
 383 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               BIT5   ///< 0x0020
 384 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            BIT6   ///< 0x0040
 385 #define EFI_PCI_COMMAND_STEPPING_CONTROL                BIT7   ///< 0x0080
 386 #define EFI_PCI_COMMAND_SERR                            BIT8   ///< 0x0100
 387 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               BIT9   ///< 0x0200
 388
 389 //
 390 // defined in PCI-to-PCI Bridge Architecture Specification
 391 //
 392 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    BIT0   ///< 0x0001
 393 #define EFI_PCI_BRIDGE_CONTROL_SERR                     BIT1   ///< 0x0002
 394 #define EFI_PCI_BRIDGE_CONTROL_ISA                      BIT2   ///< 0x0004
 395 #define EFI_PCI_BRIDGE_CONTROL_VGA                      BIT3   ///< 0x0008
 396 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   BIT4   ///< 0x0010
 397 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             BIT5   ///< 0x0020
 398 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      BIT6   ///< 0x0040
 399 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        BIT7   ///< 0x0080
 400 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    BIT8   ///< 0x0100
 401 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  BIT9   ///< 0x0200
 402 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             BIT10  ///< 0x0400
 403 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       BIT11  ///< 0x0800
 404
 405 //
 406 // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard
 407 //
 408 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE           BIT7   ///< 0x0080
 409 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE       BIT8   ///< 0x0100
 410 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE       BIT9   ///< 0x0200
 411 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE     BIT10  ///< 0x0400
 412
 413 //
 414 // Following are the PCI status control bit
 415 //
 416 #define EFI_PCI_STATUS_CAPABILITY                       BIT4   ///< 0x0010
 417 #define EFI_PCI_STATUS_66MZ_CAPABLE                     BIT5   ///< 0x0020
 418 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE               BIT7   ///< 0x0080
 419 #define EFI_PCI_MASTER_DATA_PARITY_ERROR                BIT8   ///< 0x0100
 420
 421 ///
 422 /// defined in PC Card Standard
 423 ///
 424 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 425
 426 //
 427 // PCI Capability List IDs and records
 428 //
 429 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 430 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 431 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 432 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 433 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 434 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 435
 436 typedef struct {
 437   UINT8 CapabilityID;
 438   UINT8 NextItemPtr;
 439 } EFI_PCI_CAPABILITY_HDR;
 440
 441 ///
 442 /// Capability EFI_PCI_CAPABILITY_ID_PMI, defined in PCI Power Management Interface Specifiction
 443 ///
 444 typedef struct {
 445   EFI_PCI_CAPABILITY_HDR  Hdr;
 446   UINT16                  PMC;
 447   UINT16                  PMCSR;
 448   UINT8                   BridgeExtention;
 449   UINT8                   Data;
 450 } EFI_PCI_CAPABILITY_PMI;
 451
 452 ///
 453 /// Capability EFI_PCI_CAPABILITY_ID_AGP, defined in Accelerated Graphics Port Interface Specification
 454 ///
 455 typedef struct {
 456   EFI_PCI_CAPABILITY_HDR  Hdr;
 457   UINT8                   Rev;
 458   UINT8                   Reserved;
 459   UINT32                  Status;
 460   UINT32                  Command;
 461 } EFI_PCI_CAPABILITY_AGP;
 462
 463 ///
 464 /// Capability EFI_PCI_CAPABILITY_ID_VPD, in PCI2.2 Spec.
 465 ///
 466 typedef struct {
 467   EFI_PCI_CAPABILITY_HDR  Hdr;
 468   UINT16                  AddrReg;
 469   UINT32                  DataReg;
 470 } EFI_PCI_CAPABILITY_VPD;
 471
 472 ///
 473 /// Capability EFI_PCI_CAPABILITY_ID_SLOTID, defined in PCI-to-PCI Bridge Architeture Specification
 474 ///
 475 typedef struct {
 476   EFI_PCI_CAPABILITY_HDR  Hdr;
 477   UINT8                   ExpnsSlotReg;
 478   UINT8                   ChassisNo;
 479 } EFI_PCI_CAPABILITY_SLOTID;
 480
 481 ///
 482 /// Capability EFI_PCI_CAPABILITY_ID_MSI, defined in PCI2.2
 483 ///
 484 typedef struct {
 485   EFI_PCI_CAPABILITY_HDR  Hdr;
 486   UINT16                  MsgCtrlReg;
 487   UINT32                  MsgAddrReg;
 488   UINT16                  MsgDataReg;
 489 } EFI_PCI_CAPABILITY_MSI32;
 490
 491 typedef struct {
 492   EFI_PCI_CAPABILITY_HDR  Hdr;
 493   UINT16                  MsgCtrlReg;
 494   UINT32                  MsgAddrRegLsdw;
 495   UINT32                  MsgAddrRegMsdw;
 496   UINT16                  MsgDataReg;
 497 } EFI_PCI_CAPABILITY_MSI64;
 498
 499 ///
 500 /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, defined in CompactPCI Hot Swap Specification PICMG 2.1, R1.0
 501 ///
 502 typedef struct {
 503   EFI_PCI_CAPABILITY_HDR  Hdr;
 504   ///
 505   /// not finished - fields need to go here
 506   ///
 507 } EFI_PCI_CAPABILITY_HOTPLUG;
 508
 509 #define DEVICE_ID_NOCARE    0xFFFF
 510
 511 #define PCI_ACPI_UNUSED     0
 512 #define PCI_BAR_NOCHANGE    0
 513 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 514 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 515 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 516 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 517
 518 #define PCI_BAR_IDX0        0x00
 519 #define PCI_BAR_IDX1        0x01
 520 #define PCI_BAR_IDX2        0x02
 521 #define PCI_BAR_IDX3        0x03
 522 #define PCI_BAR_IDX4        0x04
 523 #define PCI_BAR_IDX5        0x05
 524 #define PCI_BAR_ALL         0xFF
 525
 526 ///
 527 /// EFI PCI Option ROM definitions
 528 ///
 529 #define EFI_ROOT_BRIDGE_LIST                            'eprb'
 530 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
 531
 532 typedef struct {
 533   UINT8 Register;
 534   UINT8 Function;
 535   UINT8 Device;
 536   UINT8 Bus;
 537   UINT8 Reserved[4];
 538 } DEFIO_PCI_ADDR;
 539
 540 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 541 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 542 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 543 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001  ///<defined in UEFI spec.
 544
 545 typedef struct {
 546   UINT16  Signature;    ///< 0xaa55
 547   UINT8   Reserved[0x16];
 548   UINT16  PcirOffset;
 549 } PCI_EXPANSION_ROM_HEADER;
 550
 551 typedef struct {
 552   UINT16  Signature;    ///< 0xaa55
 553   UINT8   Size512;
 554   UINT8   InitEntryPoint[3];
 555   UINT8   Reserved[0x12];
 556   UINT16  PcirOffset;
 557 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 558
 559 typedef struct {
 560   UINT32  Signature;    ///< "PCIR"
 561   UINT16  VendorId;
 562   UINT16  DeviceId;
 563   UINT16  Reserved0;
 564   UINT16  Length;
 565   UINT8   Revision;
 566   UINT8   ClassCode[3];
 567   UINT16  ImageLength;
 568   UINT16  CodeRevision;
 569   UINT8   CodeType;
 570   UINT8   Indicator;
 571   UINT16  Reserved1;
 572 } PCI_DATA_STRUCTURE;
 573
 574 ///
 575 /// defined in EFI/UEFI Spec
 576 ///
 577 typedef struct {
 578   UINT16  Signature;    ///< 0xaa55
 579   UINT16  InitializationSize;
 580   UINT32  EfiSignature; ///< 0x0EF1
 581   UINT16  EfiSubsystem;
 582   UINT16  EfiMachineType;
 583   UINT16  CompressionType;
 584   UINT8   Reserved[8];
 585   UINT16  EfiImageHeaderOffset;
 586   UINT16  PcirOffset;
 587 } EFI_PCI_EXPANSION_ROM_HEADER;
 588
 589 typedef union {
 590   UINT8                           *Raw;
 591   PCI_EXPANSION_ROM_HEADER        *Generic;
 592   EFI_PCI_EXPANSION_ROM_HEADER    *Efi;
 593   EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;
 594 } EFI_PCI_ROM_HEADER;
 595
 596 #endif