MdePkg/Include/IndustryStandard/SdramSpd.h

   1 /** @file
   2   This file contains definitions for the SPD fields on an SDRAM.
   3
   4   Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 **/
  13
  14 #ifndef _SDRAM_SPD_H_
  15 #define _SDRAM_SPD_H_
  16
  17 #include <IndustryStandard/SdramSpdDdr3.h>
  18 #include <IndustryStandard/SdramSpdDdr4.h>
  19 #include <IndustryStandard/SdramSpdLpDdr.h>
  20
  21 //
  22 // SDRAM SPD field definitions
  23 //
  24 #define SPD_MEMORY_TYPE                 2
  25 #define SPD_SDRAM_ROW_ADDR              3
  26 #define SPD_SDRAM_COL_ADDR              4
  27 #define SPD_SDRAM_MODULE_ROWS           5
  28 #define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
  29 #define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
  30 #define SPD_SDRAM_ECC_SUPPORT           11
  31 #define SPD_SDRAM_REFRESH               12
  32 #define SPD_SDRAM_WIDTH                 13
  33 #define SPD_SDRAM_ERROR_WIDTH           14
  34 #define SPD_SDRAM_BURST_LENGTH          16
  35 #define SPD_SDRAM_NO_OF_BANKS           17
  36 #define SPD_SDRAM_CAS_LATENCY           18
  37 #define SPD_SDRAM_MODULE_ATTR           21
  38
  39 #define SPD_SDRAM_TCLK1_PULSE           9   ///< cycle time for highest cas latency
  40 #define SPD_SDRAM_TAC1_PULSE            10  ///< access time for highest cas latency
  41 #define SPD_SDRAM_TCLK2_PULSE           23  ///< cycle time for 2nd highest cas latency
  42 #define SPD_SDRAM_TAC2_PULSE            24  ///< access time for 2nd highest cas latency
  43 #define SPD_SDRAM_TCLK3_PULSE           25  ///< cycle time for 3rd highest cas latency
  44 #define SPD_SDRAM_TAC3_PULSE            26  ///< access time for 3rd highest cas latency
  45 #define SPD_SDRAM_MIN_PRECHARGE         27
  46 #define SPD_SDRAM_ACTIVE_MIN            28
  47 #define SPD_SDRAM_RAS_CAS               29
  48 #define SPD_SDRAM_RAS_PULSE             30
  49 #define SPD_SDRAM_DENSITY               31
  50
  51 //
  52 // Memory Type Definitions
  53 //
  54 #define SPD_VAL_SDR_TYPE  4       ///< SDR SDRAM memory
  55 #define SPD_VAL_DDR_TYPE  7       ///< DDR SDRAM memory
  56 #define SPD_VAL_DDR2_TYPE 8       ///< DDR2 SDRAM memory
  57 #define SPD_VAL_DDR3_TYPE 11      ///< DDR3 SDRAM memory
  58 #define SPD_VAL_DDR4_TYPE 12      ///< DDR4 SDRAM memory
  59 #define SPD_VAL_LPDDR3_TYPE 15    ///< LPDDR3 SDRAM memory
  60 #define SPD_VAL_LPDDR4_TYPE 16    ///< LPDDR4 SDRAM memory
  61
  62 //
  63 // ECC Type Definitions
  64 //
  65 #define SPD_ECC_TYPE_NONE   0x00  ///< No error checking
  66 #define SPD_ECC_TYPE_PARITY 0x01  ///< No error checking
  67 #define SPD_ECC_TYPE_ECC    0x02  ///< Error checking only
  68 //
  69 // Module Attributes (Bit positions)
  70 //
  71 #define SPD_BUFFERED    0x01
  72 #define SPD_REGISTERED  0x02
  73
  74 #endif