MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be through I/O ports 0xCF8 and 0xCFC.  This library only allows
   6   access to PCI Segment #0.
   7
   8 Copyright (c) 2006 - 2009, Intel Corporation<BR>
   9 All rights reserved. This program and the accompanying materials
  10 are licensed and made available under the terms and conditions of the BSD License
  11 which accompanies this distribution.  The full text of the license may be found at
  12 http://opensource.org/licenses/bsd-license.php
  13
  14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17 **/
  18
  19 #ifndef __PCI_CF8_LIB_H__
  20 #define __PCI_CF8_LIB_H__
  21
  22
  23 /**
  24   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  25   address that can be passed to the PCI Library functions.
  26
  27   Computes an address that is compatible with the PCI Library functions. The
  28   unused upper bits of Bus, Device, Function and Register are stripped prior to
  29   the generation of the address.
  30
  31   @param  Bus       PCI Bus number. Range 0..255.
  32   @param  Device    PCI Device number. Range 0..31.
  33   @param  Function  PCI Function number. Range 0..7.
  34   @param  Register  PCI Register number. Range 0..255.
  35
  36   @return The encode PCI address.
  37
  38 **/
  39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  40   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  41
  42 /**
  43   Registers a PCI device so PCI configuration registers may be accessed after
  44   SetVirtualAddressMap().
  45
  46   Registers the PCI device specified by Address so all the PCI configuration registers
  47   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
  48
  49   If Address > 0x0FFFFFFF, then ASSERT().
  50   If the register specified by Address >= 0x100, then ASSERT().
  51
  52   @param  Address Address that encodes the PCI Bus, Device, Function and
  53                   Register.
  54
  55   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  56   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  57                                    after ExitBootServices().
  58   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  59                                    at runtime could not be mapped.
  60   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  61                                    complete the registration.
  62
  63 **/
  64 RETURN_STATUS
  65 EFIAPI
  66 PciCf8RegisterForRuntimeAccess (
  67   IN UINTN  Address
  68   );
  69
  70 /**
  71   Reads an 8-bit PCI configuration register.
  72
  73   Reads and returns the 8-bit PCI configuration register specified by Address.
  74   This function must guarantee that all PCI read and write operations are
  75   serialized.
  76
  77   If Address > 0x0FFFFFFF, then ASSERT().
  78   If the register specified by Address >= 0x100, then ASSERT().
  79
  80   @param  Address Address that encodes the PCI Bus, Device, Function and
  81                   Register.
  82
  83   @return The read value from the PCI configuration register.
  84
  85 **/
  86 UINT8
  87 EFIAPI
  88 PciCf8Read8 (
  89   IN      UINTN                     Address
  90   );
  91
  92 /**
  93   Writes an 8-bit PCI configuration register.
  94
  95   Writes the 8-bit PCI configuration register specified by Address with the
  96   value specified by Value. Value is returned. This function must guarantee
  97   that all PCI read and write operations are serialized.
  98
  99   If Address > 0x0FFFFFFF, then ASSERT().
 100   If the register specified by Address >= 0x100, then ASSERT().
 101
 102   @param  Address Address that encodes the PCI Bus, Device, Function and
 103                   Register.
 104   @param  Value   The value to write.
 105
 106   @return The value written to the PCI configuration register.
 107
 108 **/
 109 UINT8
 110 EFIAPI
 111 PciCf8Write8 (
 112   IN      UINTN                     Address,
 113   IN      UINT8                     Value
 114   );
 115
 116 /**
 117   Performs a bitwise OR of an 8-bit PCI configuration register with
 118   an 8-bit value.
 119
 120   Reads the 8-bit PCI configuration register specified by Address, performs a
 121   bitwise OR between the read result and the value specified by
 122   OrData, and writes the result to the 8-bit PCI configuration register
 123   specified by Address. The value written to the PCI configuration register is
 124   returned. This function must guarantee that all PCI read and write operations
 125   are serialized.
 126
 127   If Address > 0x0FFFFFFF, then ASSERT().
 128   If the register specified by Address >= 0x100, then ASSERT().
 129
 130   @param  Address Address that encodes the PCI Bus, Device, Function and
 131                   Register.
 132   @param  OrData  The value to OR with the PCI configuration register.
 133
 134   @return The value written back to the PCI configuration register.
 135
 136 **/
 137 UINT8
 138 EFIAPI
 139 PciCf8Or8 (
 140   IN      UINTN                     Address,
 141   IN      UINT8                     OrData
 142   );
 143
 144 /**
 145   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 146   value.
 147
 148   Reads the 8-bit PCI configuration register specified by Address, performs a
 149   bitwise AND between the read result and the value specified by AndData, and
 150   writes the result to the 8-bit PCI configuration register specified by
 151   Address. The value written to the PCI configuration register is returned.
 152   This function must guarantee that all PCI read and write operations are
 153   serialized.
 154
 155   If Address > 0x0FFFFFFF, then ASSERT().
 156   If the register specified by Address >= 0x100, then ASSERT().
 157
 158   @param  Address Address that encodes the PCI Bus, Device, Function and
 159                   Register.
 160   @param  AndData The value to AND with the PCI configuration register.
 161
 162   @return The value written back to the PCI configuration register.
 163
 164 **/
 165 UINT8
 166 EFIAPI
 167 PciCf8And8 (
 168   IN      UINTN                     Address,
 169   IN      UINT8                     AndData
 170   );
 171
 172 /**
 173   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 174   value, followed a  bitwise OR with another 8-bit value.
 175
 176   Reads the 8-bit PCI configuration register specified by Address, performs a
 177   bitwise AND between the read result and the value specified by AndData,
 178   performs a bitwise OR between the result of the AND operation and
 179   the value specified by OrData, and writes the result to the 8-bit PCI
 180   configuration register specified by Address. The value written to the PCI
 181   configuration register is returned. This function must guarantee that all PCI
 182   read and write operations are serialized.
 183
 184   If Address > 0x0FFFFFFF, then ASSERT().
 185   If the register specified by Address >= 0x100, then ASSERT().
 186
 187   @param  Address Address that encodes the PCI Bus, Device, Function and
 188                   Register.
 189   @param  AndData The value to AND with the PCI configuration register.
 190   @param  OrData  The value to OR with the result of the AND operation.
 191
 192   @return The value written back to the PCI configuration register.
 193
 194 **/
 195 UINT8
 196 EFIAPI
 197 PciCf8AndThenOr8 (
 198   IN      UINTN                     Address,
 199   IN      UINT8                     AndData,
 200   IN      UINT8                     OrData
 201   );
 202
 203 /**
 204   Reads a bit field of a PCI configuration register.
 205
 206   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 207   specified by the StartBit and the EndBit. The value of the bit field is
 208   returned.
 209
 210   If Address > 0x0FFFFFFF, then ASSERT().
 211   If the register specified by Address >= 0x100, then ASSERT().
 212   If StartBit is greater than 7, then ASSERT().
 213   If EndBit is greater than 7, then ASSERT().
 214   If EndBit is less than StartBit, then ASSERT().
 215
 216   @param  Address   PCI configuration register to read.
 217   @param  StartBit  The ordinal of the least significant bit in the bit field.
 218                     Range 0..7.
 219   @param  EndBit    The ordinal of the most significant bit in the bit field.
 220                     Range 0..7.
 221
 222   @return The value of the bit field read from the PCI configuration register.
 223
 224 **/
 225 UINT8
 226 EFIAPI
 227 PciCf8BitFieldRead8 (
 228   IN      UINTN                     Address,
 229   IN      UINTN                     StartBit,
 230   IN      UINTN                     EndBit
 231   );
 232
 233 /**
 234   Writes a bit field to a PCI configuration register.
 235
 236   Writes Value to the bit field of the PCI configuration register. The bit
 237   field is specified by the StartBit and the EndBit. All other bits in the
 238   destination PCI configuration register are preserved. The new value of the
 239   8-bit register is returned.
 240
 241   If Address > 0x0FFFFFFF, then ASSERT().
 242   If the register specified by Address >= 0x100, then ASSERT().
 243   If StartBit is greater than 7, then ASSERT().
 244   If EndBit is greater than 7, then ASSERT().
 245   If EndBit is less than StartBit, then ASSERT().
 246
 247   @param  Address   PCI configuration register to write.
 248   @param  StartBit  The ordinal of the least significant bit in the bit field.
 249                     Range 0..7.
 250   @param  EndBit    The ordinal of the most significant bit in the bit field.
 251                     Range 0..7.
 252   @param  Value     New value of the bit field.
 253
 254   @return The value written back to the PCI configuration register.
 255
 256 **/
 257 UINT8
 258 EFIAPI
 259 PciCf8BitFieldWrite8 (
 260   IN      UINTN                     Address,
 261   IN      UINTN                     StartBit,
 262   IN      UINTN                     EndBit,
 263   IN      UINT8                     Value
 264   );
 265
 266 /**
 267   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 268   writes the result back to the bit field in the 8-bit port.
 269
 270   Reads the 8-bit PCI configuration register specified by Address, performs a
 271   bitwise OR between the read result and the value specified by
 272   OrData, and writes the result to the 8-bit PCI configuration register
 273   specified by Address. The value written to the PCI configuration register is
 274   returned. This function must guarantee that all PCI read and write operations
 275   are serialized. Extra left bits in OrData are stripped.
 276
 277   If Address > 0x0FFFFFFF, then ASSERT().
 278   If the register specified by Address >= 0x100, then ASSERT().
 279   If StartBit is greater than 7, then ASSERT().
 280   If EndBit is greater than 7, then ASSERT().
 281   If EndBit is less than StartBit, then ASSERT().
 282
 283   @param  Address   PCI configuration register to write.
 284   @param  StartBit  The ordinal of the least significant bit in the bit field.
 285                     Range 0..7.
 286   @param  EndBit    The ordinal of the most significant bit in the bit field.
 287                     Range 0..7.
 288   @param  OrData    The value to OR with the PCI configuration register.
 289
 290   @return The value written back to the PCI configuration register.
 291
 292 **/
 293 UINT8
 294 EFIAPI
 295 PciCf8BitFieldOr8 (
 296   IN      UINTN                     Address,
 297   IN      UINTN                     StartBit,
 298   IN      UINTN                     EndBit,
 299   IN      UINT8                     OrData
 300   );
 301
 302 /**
 303   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 304   AND, and writes the result back to the bit field in the 8-bit register.
 305
 306   Reads the 8-bit PCI configuration register specified by Address, performs a
 307   bitwise AND between the read result and the value specified by AndData, and
 308   writes the result to the 8-bit PCI configuration register specified by
 309   Address. The value written to the PCI configuration register is returned.
 310   This function must guarantee that all PCI read and write operations are
 311   serialized. Extra left bits in AndData are stripped.
 312
 313   If Address > 0x0FFFFFFF, then ASSERT().
 314   If the register specified by Address >= 0x100, then ASSERT().
 315   If StartBit is greater than 7, then ASSERT().
 316   If EndBit is greater than 7, then ASSERT().
 317   If EndBit is less than StartBit, then ASSERT().
 318
 319   @param  Address   PCI configuration register to write.
 320   @param  StartBit  The ordinal of the least significant bit in the bit field.
 321                     Range 0..7.
 322   @param  EndBit    The ordinal of the most significant bit in the bit field.
 323                     Range 0..7.
 324   @param  AndData   The value to AND with the PCI configuration register.
 325
 326   @return The value written back to the PCI configuration register.
 327
 328 **/
 329 UINT8
 330 EFIAPI
 331 PciCf8BitFieldAnd8 (
 332   IN      UINTN                     Address,
 333   IN      UINTN                     StartBit,
 334   IN      UINTN                     EndBit,
 335   IN      UINT8                     AndData
 336   );
 337
 338 /**
 339   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 340   bitwise OR, and writes the result back to the bit field in the
 341   8-bit port.
 342
 343   Reads the 8-bit PCI configuration register specified by Address, performs a
 344   bitwise AND followed by a bitwise OR between the read result and
 345   the value specified by AndData, and writes the result to the 8-bit PCI
 346   configuration register specified by Address. The value written to the PCI
 347   configuration register is returned. This function must guarantee that all PCI
 348   read and write operations are serialized. Extra left bits in both AndData and
 349   OrData are stripped.
 350
 351   If Address > 0x0FFFFFFF, then ASSERT().
 352   If the register specified by Address >= 0x100, then ASSERT().
 353   If StartBit is greater than 7, then ASSERT().
 354   If EndBit is greater than 7, then ASSERT().
 355   If EndBit is less than StartBit, then ASSERT().
 356
 357   @param  Address   PCI configuration register to write.
 358   @param  StartBit  The ordinal of the least significant bit in the bit field.
 359                     Range 0..7.
 360   @param  EndBit    The ordinal of the most significant bit in the bit field.
 361                     Range 0..7.
 362   @param  AndData   The value to AND with the PCI configuration register.
 363   @param  OrData    The value to OR with the result of the AND operation.
 364
 365   @return The value written back to the PCI configuration register.
 366
 367 **/
 368 UINT8
 369 EFIAPI
 370 PciCf8BitFieldAndThenOr8 (
 371   IN      UINTN                     Address,
 372   IN      UINTN                     StartBit,
 373   IN      UINTN                     EndBit,
 374   IN      UINT8                     AndData,
 375   IN      UINT8                     OrData
 376   );
 377
 378 /**
 379   Reads a 16-bit PCI configuration register.
 380
 381   Reads and returns the 16-bit PCI configuration register specified by Address.
 382   This function must guarantee that all PCI read and write operations are
 383   serialized.
 384
 385   If Address > 0x0FFFFFFF, then ASSERT().
 386   If Address is not aligned on a 16-bit boundary, then ASSERT().
 387   If the register specified by Address >= 0x100, then ASSERT().
 388
 389   @param  Address Address that encodes the PCI Bus, Device, Function and
 390                   Register.
 391
 392   @return The read value from the PCI configuration register.
 393
 394 **/
 395 UINT16
 396 EFIAPI
 397 PciCf8Read16 (
 398   IN      UINTN                     Address
 399   );
 400
 401 /**
 402   Writes a 16-bit PCI configuration register.
 403
 404   Writes the 16-bit PCI configuration register specified by Address with the
 405   value specified by Value. Value is returned. This function must guarantee
 406   that all PCI read and write operations are serialized.
 407
 408   If Address > 0x0FFFFFFF, then ASSERT().
 409   If Address is not aligned on a 16-bit boundary, then ASSERT().
 410   If the register specified by Address >= 0x100, then ASSERT().
 411
 412   @param  Address Address that encodes the PCI Bus, Device, Function and
 413                   Register.
 414   @param  Value   The value to write.
 415
 416   @return The value written to the PCI configuration register.
 417
 418 **/
 419 UINT16
 420 EFIAPI
 421 PciCf8Write16 (
 422   IN      UINTN                     Address,
 423   IN      UINT16                    Value
 424   );
 425
 426 /**
 427   Performs a bitwise OR of a 16-bit PCI configuration register with
 428   a 16-bit value.
 429
 430   Reads the 16-bit PCI configuration register specified by Address, performs a
 431   bitwise OR between the read result and the value specified by
 432   OrData, and writes the result to the 16-bit PCI configuration register
 433   specified by Address. The value written to the PCI configuration register is
 434   returned. This function must guarantee that all PCI read and write operations
 435   are serialized.
 436
 437   If Address > 0x0FFFFFFF, then ASSERT().
 438   If Address is not aligned on a 16-bit boundary, then ASSERT().
 439   If the register specified by Address >= 0x100, then ASSERT().
 440
 441   @param  Address Address that encodes the PCI Bus, Device, Function and
 442                   Register.
 443   @param  OrData  The value to OR with the PCI configuration register.
 444
 445   @return The value written back to the PCI configuration register.
 446
 447 **/
 448 UINT16
 449 EFIAPI
 450 PciCf8Or16 (
 451   IN      UINTN                     Address,
 452   IN      UINT16                    OrData
 453   );
 454
 455 /**
 456   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 457   value.
 458
 459   Reads the 16-bit PCI configuration register specified by Address, performs a
 460   bitwise AND between the read result and the value specified by AndData, and
 461   writes the result to the 16-bit PCI configuration register specified by
 462   Address. The value written to the PCI configuration register is returned.
 463   This function must guarantee that all PCI read and write operations are
 464   serialized.
 465
 466   If Address > 0x0FFFFFFF, then ASSERT().
 467   If Address is not aligned on a 16-bit boundary, then ASSERT().
 468   If the register specified by Address >= 0x100, then ASSERT().
 469
 470   @param  Address Address that encodes the PCI Bus, Device, Function and
 471                   Register.
 472   @param  AndData The value to AND with the PCI configuration register.
 473
 474   @return The value written back to the PCI configuration register.
 475
 476 **/
 477 UINT16
 478 EFIAPI
 479 PciCf8And16 (
 480   IN      UINTN                     Address,
 481   IN      UINT16                    AndData
 482   );
 483
 484 /**
 485   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 486   value, followed a  bitwise OR with another 16-bit value.
 487
 488   Reads the 16-bit PCI configuration register specified by Address, performs a
 489   bitwise AND between the read result and the value specified by AndData,
 490   performs a bitwise OR between the result of the AND operation and
 491   the value specified by OrData, and writes the result to the 16-bit PCI
 492   configuration register specified by Address. The value written to the PCI
 493   configuration register is returned. This function must guarantee that all PCI
 494   read and write operations are serialized.
 495
 496   If Address > 0x0FFFFFFF, then ASSERT().
 497   If Address is not aligned on a 16-bit boundary, then ASSERT().
 498   If the register specified by Address >= 0x100, then ASSERT().
 499
 500   @param  Address Address that encodes the PCI Bus, Device, Function and
 501                   Register.
 502   @param  AndData The value to AND with the PCI configuration register.
 503   @param  OrData  The value to OR with the result of the AND operation.
 504
 505   @return The value written back to the PCI configuration register.
 506
 507 **/
 508 UINT16
 509 EFIAPI
 510 PciCf8AndThenOr16 (
 511   IN      UINTN                     Address,
 512   IN      UINT16                    AndData,
 513   IN      UINT16                    OrData
 514   );
 515
 516 /**
 517   Reads a bit field of a PCI configuration register.
 518
 519   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 520   specified by the StartBit and the EndBit. The value of the bit field is
 521   returned.
 522
 523   If Address > 0x0FFFFFFF, then ASSERT().
 524   If Address is not aligned on a 16-bit boundary, then ASSERT().
 525   If the register specified by Address >= 0x100, then ASSERT().
 526   If StartBit is greater than 15, then ASSERT().
 527   If EndBit is greater than 15, then ASSERT().
 528   If EndBit is less than StartBit, then ASSERT().
 529
 530   @param  Address   PCI configuration register to read.
 531   @param  StartBit  The ordinal of the least significant bit in the bit field.
 532                     Range 0..15.
 533   @param  EndBit    The ordinal of the most significant bit in the bit field.
 534                     Range 0..15.
 535
 536   @return The value of the bit field read from the PCI configuration register.
 537
 538 **/
 539 UINT16
 540 EFIAPI
 541 PciCf8BitFieldRead16 (
 542   IN      UINTN                     Address,
 543   IN      UINTN                     StartBit,
 544   IN      UINTN                     EndBit
 545   );
 546
 547 /**
 548   Writes a bit field to a PCI configuration register.
 549
 550   Writes Value to the bit field of the PCI configuration register. The bit
 551   field is specified by the StartBit and the EndBit. All other bits in the
 552   destination PCI configuration register are preserved. The new value of the
 553   16-bit register is returned.
 554
 555   If Address > 0x0FFFFFFF, then ASSERT().
 556   If Address is not aligned on a 16-bit boundary, then ASSERT().
 557   If the register specified by Address >= 0x100, then ASSERT().
 558   If StartBit is greater than 15, then ASSERT().
 559   If EndBit is greater than 15, then ASSERT().
 560   If EndBit is less than StartBit, then ASSERT().
 561
 562   @param  Address   PCI configuration register to write.
 563   @param  StartBit  The ordinal of the least significant bit in the bit field.
 564                     Range 0..15.
 565   @param  EndBit    The ordinal of the most significant bit in the bit field.
 566                     Range 0..15.
 567   @param  Value     New value of the bit field.
 568
 569   @return The value written back to the PCI configuration register.
 570
 571 **/
 572 UINT16
 573 EFIAPI
 574 PciCf8BitFieldWrite16 (
 575   IN      UINTN                     Address,
 576   IN      UINTN                     StartBit,
 577   IN      UINTN                     EndBit,
 578   IN      UINT16                    Value
 579   );
 580
 581 /**
 582   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 583   writes the result back to the bit field in the 16-bit port.
 584
 585   Reads the 16-bit PCI configuration register specified by Address, performs a
 586   bitwise OR between the read result and the value specified by
 587   OrData, and writes the result to the 16-bit PCI configuration register
 588   specified by Address. The value written to the PCI configuration register is
 589   returned. This function must guarantee that all PCI read and write operations
 590   are serialized. Extra left bits in OrData are stripped.
 591
 592   If Address > 0x0FFFFFFF, then ASSERT().
 593   If Address is not aligned on a 16-bit boundary, then ASSERT().
 594   If the register specified by Address >= 0x100, then ASSERT().
 595   If StartBit is greater than 15, then ASSERT().
 596   If EndBit is greater than 15, then ASSERT().
 597   If EndBit is less than StartBit, then ASSERT().
 598
 599   @param  Address   PCI configuration register to write.
 600   @param  StartBit  The ordinal of the least significant bit in the bit field.
 601                     Range 0..15.
 602   @param  EndBit    The ordinal of the most significant bit in the bit field.
 603                     Range 0..15.
 604   @param  OrData    The value to OR with the PCI configuration register.
 605
 606   @return The value written back to the PCI configuration register.
 607
 608 **/
 609 UINT16
 610 EFIAPI
 611 PciCf8BitFieldOr16 (
 612   IN      UINTN                     Address,
 613   IN      UINTN                     StartBit,
 614   IN      UINTN                     EndBit,
 615   IN      UINT16                    OrData
 616   );
 617
 618 /**
 619   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 620   AND, and writes the result back to the bit field in the 16-bit register.
 621
 622   Reads the 16-bit PCI configuration register specified by Address, performs a
 623   bitwise AND between the read result and the value specified by AndData, and
 624   writes the result to the 16-bit PCI configuration register specified by
 625   Address. The value written to the PCI configuration register is returned.
 626   This function must guarantee that all PCI read and write operations are
 627   serialized. Extra left bits in AndData are stripped.
 628
 629   If Address > 0x0FFFFFFF, then ASSERT().
 630   If Address is not aligned on a 16-bit boundary, then ASSERT().
 631   If the register specified by Address >= 0x100, then ASSERT().
 632   If StartBit is greater than 15, then ASSERT().
 633   If EndBit is greater than 15, then ASSERT().
 634   If EndBit is less than StartBit, then ASSERT().
 635
 636   @param  Address   PCI configuration register to write.
 637   @param  StartBit  The ordinal of the least significant bit in the bit field.
 638                     Range 0..15.
 639   @param  EndBit    The ordinal of the most significant bit in the bit field.
 640                     Range 0..15.
 641   @param  AndData   The value to AND with the PCI configuration register.
 642
 643   @return The value written back to the PCI configuration register.
 644
 645 **/
 646 UINT16
 647 EFIAPI
 648 PciCf8BitFieldAnd16 (
 649   IN      UINTN                     Address,
 650   IN      UINTN                     StartBit,
 651   IN      UINTN                     EndBit,
 652   IN      UINT16                    AndData
 653   );
 654
 655 /**
 656   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 657   bitwise OR, and writes the result back to the bit field in the
 658   16-bit port.
 659
 660   Reads the 16-bit PCI configuration register specified by Address, performs a
 661   bitwise AND followed by a bitwise OR between the read result and
 662   the value specified by AndData, and writes the result to the 16-bit PCI
 663   configuration register specified by Address. The value written to the PCI
 664   configuration register is returned. This function must guarantee that all PCI
 665   read and write operations are serialized. Extra left bits in both AndData and
 666   OrData are stripped.
 667
 668   If Address > 0x0FFFFFFF, then ASSERT().
 669   If Address is not aligned on a 16-bit boundary, then ASSERT().
 670   If the register specified by Address >= 0x100, then ASSERT().
 671   If StartBit is greater than 15, then ASSERT().
 672   If EndBit is greater than 15, then ASSERT().
 673   If EndBit is less than StartBit, then ASSERT().
 674
 675   @param  Address   PCI configuration register to write.
 676   @param  StartBit  The ordinal of the least significant bit in the bit field.
 677                     Range 0..15.
 678   @param  EndBit    The ordinal of the most significant bit in the bit field.
 679                     Range 0..15.
 680   @param  AndData   The value to AND with the PCI configuration register.
 681   @param  OrData    The value to OR with the result of the AND operation.
 682
 683   @return The value written back to the PCI configuration register.
 684
 685 **/
 686 UINT16
 687 EFIAPI
 688 PciCf8BitFieldAndThenOr16 (
 689   IN      UINTN                     Address,
 690   IN      UINTN                     StartBit,
 691   IN      UINTN                     EndBit,
 692   IN      UINT16                    AndData,
 693   IN      UINT16                    OrData
 694   );
 695
 696 /**
 697   Reads a 32-bit PCI configuration register.
 698
 699   Reads and returns the 32-bit PCI configuration register specified by Address.
 700   This function must guarantee that all PCI read and write operations are
 701   serialized.
 702
 703   If Address > 0x0FFFFFFF, then ASSERT().
 704   If Address is not aligned on a 32-bit boundary, then ASSERT().
 705   If the register specified by Address >= 0x100, then ASSERT().
 706
 707   @param  Address Address that encodes the PCI Bus, Device, Function and
 708                   Register.
 709
 710   @return The read value from the PCI configuration register.
 711
 712 **/
 713 UINT32
 714 EFIAPI
 715 PciCf8Read32 (
 716   IN      UINTN                     Address
 717   );
 718
 719 /**
 720   Writes a 32-bit PCI configuration register.
 721
 722   Writes the 32-bit PCI configuration register specified by Address with the
 723   value specified by Value. Value is returned. This function must guarantee
 724   that all PCI read and write operations are serialized.
 725
 726   If Address > 0x0FFFFFFF, then ASSERT().
 727   If Address is not aligned on a 32-bit boundary, then ASSERT().
 728   If the register specified by Address >= 0x100, then ASSERT().
 729
 730   @param  Address Address that encodes the PCI Bus, Device, Function and
 731                   Register.
 732   @param  Value   The value to write.
 733
 734   @return The value written to the PCI configuration register.
 735
 736 **/
 737 UINT32
 738 EFIAPI
 739 PciCf8Write32 (
 740   IN      UINTN                     Address,
 741   IN      UINT32                    Value
 742   );
 743
 744 /**
 745   Performs a bitwise OR of a 32-bit PCI configuration register with
 746   a 32-bit value.
 747
 748   Reads the 32-bit PCI configuration register specified by Address, performs a
 749   bitwise OR between the read result and the value specified by
 750   OrData, and writes the result to the 32-bit PCI configuration register
 751   specified by Address. The value written to the PCI configuration register is
 752   returned. This function must guarantee that all PCI read and write operations
 753   are serialized.
 754
 755   If Address > 0x0FFFFFFF, then ASSERT().
 756   If Address is not aligned on a 32-bit boundary, then ASSERT().
 757   If the register specified by Address >= 0x100, then ASSERT().
 758
 759   @param  Address Address that encodes the PCI Bus, Device, Function and
 760                   Register.
 761   @param  OrData  The value to OR with the PCI configuration register.
 762
 763   @return The value written back to the PCI configuration register.
 764
 765 **/
 766 UINT32
 767 EFIAPI
 768 PciCf8Or32 (
 769   IN      UINTN                     Address,
 770   IN      UINT32                    OrData
 771   );
 772
 773 /**
 774   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 775   value.
 776
 777   Reads the 32-bit PCI configuration register specified by Address, performs a
 778   bitwise AND between the read result and the value specified by AndData, and
 779   writes the result to the 32-bit PCI configuration register specified by
 780   Address. The value written to the PCI configuration register is returned.
 781   This function must guarantee that all PCI read and write operations are
 782   serialized.
 783
 784   If Address > 0x0FFFFFFF, then ASSERT().
 785   If Address is not aligned on a 32-bit boundary, then ASSERT().
 786   If the register specified by Address >= 0x100, then ASSERT().
 787
 788   @param  Address Address that encodes the PCI Bus, Device, Function and
 789                   Register.
 790   @param  AndData The value to AND with the PCI configuration register.
 791
 792   @return The value written back to the PCI configuration register.
 793
 794 **/
 795 UINT32
 796 EFIAPI
 797 PciCf8And32 (
 798   IN      UINTN                     Address,
 799   IN      UINT32                    AndData
 800   );
 801
 802 /**
 803   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 804   value, followed a  bitwise OR with another 32-bit value.
 805
 806   Reads the 32-bit PCI configuration register specified by Address, performs a
 807   bitwise AND between the read result and the value specified by AndData,
 808   performs a bitwise OR between the result of the AND operation and
 809   the value specified by OrData, and writes the result to the 32-bit PCI
 810   configuration register specified by Address. The value written to the PCI
 811   configuration register is returned. This function must guarantee that all PCI
 812   read and write operations are serialized.
 813
 814   If Address > 0x0FFFFFFF, then ASSERT().
 815   If Address is not aligned on a 32-bit boundary, then ASSERT().
 816   If the register specified by Address >= 0x100, then ASSERT().
 817
 818   @param  Address Address that encodes the PCI Bus, Device, Function and
 819                   Register.
 820   @param  AndData The value to AND with the PCI configuration register.
 821   @param  OrData  The value to OR with the result of the AND operation.
 822
 823   @return The value written back to the PCI configuration register.
 824
 825 **/
 826 UINT32
 827 EFIAPI
 828 PciCf8AndThenOr32 (
 829   IN      UINTN                     Address,
 830   IN      UINT32                    AndData,
 831   IN      UINT32                    OrData
 832   );
 833
 834 /**
 835   Reads a bit field of a PCI configuration register.
 836
 837   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 838   specified by the StartBit and the EndBit. The value of the bit field is
 839   returned.
 840
 841   If Address > 0x0FFFFFFF, then ASSERT().
 842   If Address is not aligned on a 32-bit boundary, then ASSERT().
 843   If the register specified by Address >= 0x100, then ASSERT().
 844   If StartBit is greater than 31, then ASSERT().
 845   If EndBit is greater than 31, then ASSERT().
 846   If EndBit is less than StartBit, then ASSERT().
 847
 848   @param  Address   PCI configuration register to read.
 849   @param  StartBit  The ordinal of the least significant bit in the bit field.
 850                     Range 0..31.
 851   @param  EndBit    The ordinal of the most significant bit in the bit field.
 852                     Range 0..31.
 853
 854   @return The value of the bit field read from the PCI configuration register.
 855
 856 **/
 857 UINT32
 858 EFIAPI
 859 PciCf8BitFieldRead32 (
 860   IN      UINTN                     Address,
 861   IN      UINTN                     StartBit,
 862   IN      UINTN                     EndBit
 863   );
 864
 865 /**
 866   Writes a bit field to a PCI configuration register.
 867
 868   Writes Value to the bit field of the PCI configuration register. The bit
 869   field is specified by the StartBit and the EndBit. All other bits in the
 870   destination PCI configuration register are preserved. The new value of the
 871   32-bit register is returned.
 872
 873   If Address > 0x0FFFFFFF, then ASSERT().
 874   If Address is not aligned on a 32-bit boundary, then ASSERT().
 875   If the register specified by Address >= 0x100, then ASSERT().
 876   If StartBit is greater than 31, then ASSERT().
 877   If EndBit is greater than 31, then ASSERT().
 878   If EndBit is less than StartBit, then ASSERT().
 879
 880   @param  Address   PCI configuration register to write.
 881   @param  StartBit  The ordinal of the least significant bit in the bit field.
 882                     Range 0..31.
 883   @param  EndBit    The ordinal of the most significant bit in the bit field.
 884                     Range 0..31.
 885   @param  Value     New value of the bit field.
 886
 887   @return The value written back to the PCI configuration register.
 888
 889 **/
 890 UINT32
 891 EFIAPI
 892 PciCf8BitFieldWrite32 (
 893   IN      UINTN                     Address,
 894   IN      UINTN                     StartBit,
 895   IN      UINTN                     EndBit,
 896   IN      UINT32                    Value
 897   );
 898
 899 /**
 900   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 901   writes the result back to the bit field in the 32-bit port.
 902
 903   Reads the 32-bit PCI configuration register specified by Address, performs a
 904   bitwise OR between the read result and the value specified by
 905   OrData, and writes the result to the 32-bit PCI configuration register
 906   specified by Address. The value written to the PCI configuration register is
 907   returned. This function must guarantee that all PCI read and write operations
 908   are serialized. Extra left bits in OrData are stripped.
 909
 910   If Address > 0x0FFFFFFF, then ASSERT().
 911   If Address is not aligned on a 32-bit boundary, then ASSERT().
 912   If the register specified by Address >= 0x100, then ASSERT().
 913   If StartBit is greater than 31, then ASSERT().
 914   If EndBit is greater than 31, then ASSERT().
 915   If EndBit is less than StartBit, then ASSERT().
 916
 917   @param  Address   PCI configuration register to write.
 918   @param  StartBit  The ordinal of the least significant bit in the bit field.
 919                     Range 0..31.
 920   @param  EndBit    The ordinal of the most significant bit in the bit field.
 921                     Range 0..31.
 922   @param  OrData    The value to OR with the PCI configuration register.
 923
 924   @return The value written back to the PCI configuration register.
 925
 926 **/
 927 UINT32
 928 EFIAPI
 929 PciCf8BitFieldOr32 (
 930   IN      UINTN                     Address,
 931   IN      UINTN                     StartBit,
 932   IN      UINTN                     EndBit,
 933   IN      UINT32                    OrData
 934   );
 935
 936 /**
 937   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 938   AND, and writes the result back to the bit field in the 32-bit register.
 939
 940   Reads the 32-bit PCI configuration register specified by Address, performs a
 941   bitwise AND between the read result and the value specified by AndData, and
 942   writes the result to the 32-bit PCI configuration register specified by
 943   Address. The value written to the PCI configuration register is returned.
 944   This function must guarantee that all PCI read and write operations are
 945   serialized. Extra left bits in AndData are stripped.
 946
 947   If Address > 0x0FFFFFFF, then ASSERT().
 948   If Address is not aligned on a 32-bit boundary, then ASSERT().
 949   If the register specified by Address >= 0x100, then ASSERT().
 950   If StartBit is greater than 31, then ASSERT().
 951   If EndBit is greater than 31, then ASSERT().
 952   If EndBit is less than StartBit, then ASSERT().
 953
 954   @param  Address   PCI configuration register to write.
 955   @param  StartBit  The ordinal of the least significant bit in the bit field.
 956                     Range 0..31.
 957   @param  EndBit    The ordinal of the most significant bit in the bit field.
 958                     Range 0..31.
 959   @param  AndData   The value to AND with the PCI configuration register.
 960
 961   @return The value written back to the PCI configuration register.
 962
 963 **/
 964 UINT32
 965 EFIAPI
 966 PciCf8BitFieldAnd32 (
 967   IN      UINTN                     Address,
 968   IN      UINTN                     StartBit,
 969   IN      UINTN                     EndBit,
 970   IN      UINT32                    AndData
 971   );
 972
 973 /**
 974   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 975   bitwise OR, and writes the result back to the bit field in the
 976   32-bit port.
 977
 978   Reads the 32-bit PCI configuration register specified by Address, performs a
 979   bitwise AND followed by a bitwise OR between the read result and
 980   the value specified by AndData, and writes the result to the 32-bit PCI
 981   configuration register specified by Address. The value written to the PCI
 982   configuration register is returned. This function must guarantee that all PCI
 983   read and write operations are serialized. Extra left bits in both AndData and
 984   OrData are stripped.
 985
 986   If Address > 0x0FFFFFFF, then ASSERT().
 987   If Address is not aligned on a 32-bit boundary, then ASSERT().
 988   If the register specified by Address >= 0x100, then ASSERT().
 989   If StartBit is greater than 31, then ASSERT().
 990   If EndBit is greater than 31, then ASSERT().
 991   If EndBit is less than StartBit, then ASSERT().
 992
 993   @param  Address   PCI configuration register to write.
 994   @param  StartBit  The ordinal of the least significant bit in the bit field.
 995                     Range 0..31.
 996   @param  EndBit    The ordinal of the most significant bit in the bit field.
 997                     Range 0..31.
 998   @param  AndData   The value to AND with the PCI configuration register.
 999   @param  OrData    The value to OR with the result of the AND operation.
1000
1001   @return The value written back to the PCI configuration register.
1002
1003 **/
1004 UINT32
1005 EFIAPI
1006 PciCf8BitFieldAndThenOr32 (
1007   IN      UINTN                     Address,
1008   IN      UINTN                     StartBit,
1009   IN      UINTN                     EndBit,
1010   IN      UINT32                    AndData,
1011   IN      UINT32                    OrData
1012   );
1013
1014 /**
1015   Reads a range of PCI configuration registers into a caller supplied buffer.
1016
1017   Reads the range of PCI configuration registers specified by StartAddress and
1018   Size into the buffer specified by Buffer. This function only allows the PCI
1019   configuration registers from a single PCI function to be read. Size is
1020   returned. When possible 32-bit PCI configuration read cycles are used to read
1021   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1022   and 16-bit PCI configuration read cycles may be used at the beginning and the
1023   end of the range.
1024
1025   If StartAddress > 0x0FFFFFFF, then ASSERT().
1026   If the register specified by StartAddress >= 0x100, then ASSERT().
1027   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1028   If Size > 0 and Buffer is NULL, then ASSERT().
1029
1030   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1031                         Function and Register.
1032   @param  Size          Size in bytes of the transfer.
1033   @param  Buffer        Pointer to a buffer receiving the data read.
1034
1035   @return Size read from StartAddress.
1036
1037 **/
1038 UINTN
1039 EFIAPI
1040 PciCf8ReadBuffer (
1041   IN      UINTN                     StartAddress,
1042   IN      UINTN                     Size,
1043   OUT     VOID                      *Buffer
1044   );
1045
1046 /**
1047   Copies the data in a caller supplied buffer to a specified range of PCI
1048   configuration space.
1049
1050   Writes the range of PCI configuration registers specified by StartAddress and
1051   Size from the buffer specified by Buffer. This function only allows the PCI
1052   configuration registers from a single PCI function to be written. Size is
1053   returned. When possible 32-bit PCI configuration write cycles are used to
1054   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1055   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1056   and the end of the range.
1057
1058   If StartAddress > 0x0FFFFFFF, then ASSERT().
1059   If the register specified by StartAddress >= 0x100, then ASSERT().
1060   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1061   If Size > 0 and Buffer is NULL, then ASSERT().
1062
1063   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1064                         Function and Register.
1065   @param  Size          Size in bytes of the transfer.
1066   @param  Buffer        Pointer to a buffer containing the data to write.
1067
1068   @return Size written to StartAddress.
1069
1070 **/
1071 UINTN
1072 EFIAPI
1073 PciCf8WriteBuffer (
1074   IN      UINTN                     StartAddress,
1075   IN      UINTN                     Size,
1076   IN      VOID                      *Buffer
1077   );
1078
1079 #endif