MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be though I/O ports 0xCF8 and 0xCFC.  This library only allows
   6   access to PCI Segment #0.
   7
   8 Copyright (c) 2006 - 2008, Intel Corporation
   9 All rights reserved. This program and the accompanying materials
  10 are licensed and made available under the terms and conditions of the BSD License
  11 which accompanies this distribution.  The full text of the license may be found at
  12 http://opensource.org/licenses/bsd-license.php
  13
  14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17 **/
  18
  19 #ifndef __PCI_CF8_LIB_H__
  20 #define __PCI_CF8_LIB_H__
  21
  22
  23 /**
  24   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  25   address that can be passed to the PCI Library functions.
  26
  27   Computes an address that is compatible with the PCI Library functions. The
  28   unused upper bits of Bus, Device, Function and Register are stripped prior to
  29   the generation of the address.
  30
  31   @param  Bus       PCI Bus number. Range 0..255.
  32   @param  Device    PCI Device number. Range 0..31.
  33   @param  Function  PCI Function number. Range 0..7.
  34   @param  Register  PCI Register number. Range 0..255.
  35
  36   @return The encode PCI address.
  37
  38 **/
  39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  40   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  41
  42 /**
  43   Reads an 8-bit PCI configuration register.
  44
  45   Reads and returns the 8-bit PCI configuration register specified by Address.
  46   This function must guarantee that all PCI read and write operations are
  47   serialized.
  48
  49   If Address > 0x0FFFFFFF, then ASSERT().
  50   If the register specified by Address >= 0x100, then ASSERT().
  51
  52   @param  Address Address that encodes the PCI Bus, Device, Function and
  53                   Register.
  54
  55   @return The read value from the PCI configuration register.
  56
  57 **/
  58 UINT8
  59 EFIAPI
  60 PciCf8Read8 (
  61   IN      UINTN                     Address
  62   );
  63
  64 /**
  65   Writes an 8-bit PCI configuration register.
  66
  67   Writes the 8-bit PCI configuration register specified by Address with the
  68   value specified by Value. Value is returned. This function must guarantee
  69   that all PCI read and write operations are serialized.
  70
  71   If Address > 0x0FFFFFFF, then ASSERT().
  72   If the register specified by Address >= 0x100, then ASSERT().
  73
  74   @param  Address Address that encodes the PCI Bus, Device, Function and
  75                   Register.
  76   @param  Value   The value to write.
  77
  78   @return The value written to the PCI configuration register.
  79
  80 **/
  81 UINT8
  82 EFIAPI
  83 PciCf8Write8 (
  84   IN      UINTN                     Address,
  85   IN      UINT8                     Value
  86   );
  87
  88 /**
  89   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  90   an 8-bit value.
  91
  92   Reads the 8-bit PCI configuration register specified by Address, performs a
  93   bitwise inclusive OR between the read result and the value specified by
  94   OrData, and writes the result to the 8-bit PCI configuration register
  95   specified by Address. The value written to the PCI configuration register is
  96   returned. This function must guarantee that all PCI read and write operations
  97   are serialized.
  98
  99   If Address > 0x0FFFFFFF, then ASSERT().
 100   If the register specified by Address >= 0x100, then ASSERT().
 101
 102   @param  Address Address that encodes the PCI Bus, Device, Function and
 103                   Register.
 104   @param  OrData  The value to OR with the PCI configuration register.
 105
 106   @return The value written back to the PCI configuration register.
 107
 108 **/
 109 UINT8
 110 EFIAPI
 111 PciCf8Or8 (
 112   IN      UINTN                     Address,
 113   IN      UINT8                     OrData
 114   );
 115
 116 /**
 117   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 118   value.
 119
 120   Reads the 8-bit PCI configuration register specified by Address, performs a
 121   bitwise AND between the read result and the value specified by AndData, and
 122   writes the result to the 8-bit PCI configuration register specified by
 123   Address. The value written to the PCI configuration register is returned.
 124   This function must guarantee that all PCI read and write operations are
 125   serialized.
 126
 127   If Address > 0x0FFFFFFF, then ASSERT().
 128   If the register specified by Address >= 0x100, then ASSERT().
 129
 130   @param  Address Address that encodes the PCI Bus, Device, Function and
 131                   Register.
 132   @param  AndData The value to AND with the PCI configuration register.
 133
 134   @return The value written back to the PCI configuration register.
 135
 136 **/
 137 UINT8
 138 EFIAPI
 139 PciCf8And8 (
 140   IN      UINTN                     Address,
 141   IN      UINT8                     AndData
 142   );
 143
 144 /**
 145   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 146   value, followed a  bitwise inclusive OR with another 8-bit value.
 147
 148   Reads the 8-bit PCI configuration register specified by Address, performs a
 149   bitwise AND between the read result and the value specified by AndData,
 150   performs a bitwise inclusive OR between the result of the AND operation and
 151   the value specified by OrData, and writes the result to the 8-bit PCI
 152   configuration register specified by Address. The value written to the PCI
 153   configuration register is returned. This function must guarantee that all PCI
 154   read and write operations are serialized.
 155
 156   If Address > 0x0FFFFFFF, then ASSERT().
 157   If the register specified by Address >= 0x100, then ASSERT().
 158
 159   @param  Address Address that encodes the PCI Bus, Device, Function and
 160                   Register.
 161   @param  AndData The value to AND with the PCI configuration register.
 162   @param  OrData  The value to OR with the result of the AND operation.
 163
 164   @return The value written back to the PCI configuration register.
 165
 166 **/
 167 UINT8
 168 EFIAPI
 169 PciCf8AndThenOr8 (
 170   IN      UINTN                     Address,
 171   IN      UINT8                     AndData,
 172   IN      UINT8                     OrData
 173   );
 174
 175 /**
 176   Reads a bit field of a PCI configuration register.
 177
 178   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 179   specified by the StartBit and the EndBit. The value of the bit field is
 180   returned.
 181
 182   If Address > 0x0FFFFFFF, then ASSERT().
 183   If the register specified by Address >= 0x100, then ASSERT().
 184   If StartBit is greater than 7, then ASSERT().
 185   If EndBit is greater than 7, then ASSERT().
 186   If EndBit is less than StartBit, then ASSERT().
 187
 188   @param  Address   PCI configuration register to read.
 189   @param  StartBit  The ordinal of the least significant bit in the bit field.
 190                     Range 0..7.
 191   @param  EndBit    The ordinal of the most significant bit in the bit field.
 192                     Range 0..7.
 193
 194   @return The value of the bit field read from the PCI configuration register.
 195
 196 **/
 197 UINT8
 198 EFIAPI
 199 PciCf8BitFieldRead8 (
 200   IN      UINTN                     Address,
 201   IN      UINTN                     StartBit,
 202   IN      UINTN                     EndBit
 203   );
 204
 205 /**
 206   Writes a bit field to a PCI configuration register.
 207
 208   Writes Value to the bit field of the PCI configuration register. The bit
 209   field is specified by the StartBit and the EndBit. All other bits in the
 210   destination PCI configuration register are preserved. The new value of the
 211   8-bit register is returned.
 212
 213   If Address > 0x0FFFFFFF, then ASSERT().
 214   If the register specified by Address >= 0x100, then ASSERT().
 215   If StartBit is greater than 7, then ASSERT().
 216   If EndBit is greater than 7, then ASSERT().
 217   If EndBit is less than StartBit, then ASSERT().
 218
 219   @param  Address   PCI configuration register to write.
 220   @param  StartBit  The ordinal of the least significant bit in the bit field.
 221                     Range 0..7.
 222   @param  EndBit    The ordinal of the most significant bit in the bit field.
 223                     Range 0..7.
 224   @param  Value     New value of the bit field.
 225
 226   @return The value written back to the PCI configuration register.
 227
 228 **/
 229 UINT8
 230 EFIAPI
 231 PciCf8BitFieldWrite8 (
 232   IN      UINTN                     Address,
 233   IN      UINTN                     StartBit,
 234   IN      UINTN                     EndBit,
 235   IN      UINT8                     Value
 236   );
 237
 238 /**
 239   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 240   writes the result back to the bit field in the 8-bit port.
 241
 242   Reads the 8-bit PCI configuration register specified by Address, performs a
 243   bitwise inclusive OR between the read result and the value specified by
 244   OrData, and writes the result to the 8-bit PCI configuration register
 245   specified by Address. The value written to the PCI configuration register is
 246   returned. This function must guarantee that all PCI read and write operations
 247   are serialized. Extra left bits in OrData are stripped.
 248
 249   If Address > 0x0FFFFFFF, then ASSERT().
 250   If the register specified by Address >= 0x100, then ASSERT().
 251   If StartBit is greater than 7, then ASSERT().
 252   If EndBit is greater than 7, then ASSERT().
 253   If EndBit is less than StartBit, then ASSERT().
 254
 255   @param  Address   PCI configuration register to write.
 256   @param  StartBit  The ordinal of the least significant bit in the bit field.
 257                     Range 0..7.
 258   @param  EndBit    The ordinal of the most significant bit in the bit field.
 259                     Range 0..7.
 260   @param  OrData    The value to OR with the PCI configuration register.
 261
 262   @return The value written back to the PCI configuration register.
 263
 264 **/
 265 UINT8
 266 EFIAPI
 267 PciCf8BitFieldOr8 (
 268   IN      UINTN                     Address,
 269   IN      UINTN                     StartBit,
 270   IN      UINTN                     EndBit,
 271   IN      UINT8                     OrData
 272   );
 273
 274 /**
 275   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 276   AND, and writes the result back to the bit field in the 8-bit register.
 277
 278   Reads the 8-bit PCI configuration register specified by Address, performs a
 279   bitwise AND between the read result and the value specified by AndData, and
 280   writes the result to the 8-bit PCI configuration register specified by
 281   Address. The value written to the PCI configuration register is returned.
 282   This function must guarantee that all PCI read and write operations are
 283   serialized. Extra left bits in AndData are stripped.
 284
 285   If Address > 0x0FFFFFFF, then ASSERT().
 286   If the register specified by Address >= 0x100, then ASSERT().
 287   If StartBit is greater than 7, then ASSERT().
 288   If EndBit is greater than 7, then ASSERT().
 289   If EndBit is less than StartBit, then ASSERT().
 290
 291   @param  Address   PCI configuration register to write.
 292   @param  StartBit  The ordinal of the least significant bit in the bit field.
 293                     Range 0..7.
 294   @param  EndBit    The ordinal of the most significant bit in the bit field.
 295                     Range 0..7.
 296   @param  AndData   The value to AND with the PCI configuration register.
 297
 298   @return The value written back to the PCI configuration register.
 299
 300 **/
 301 UINT8
 302 EFIAPI
 303 PciCf8BitFieldAnd8 (
 304   IN      UINTN                     Address,
 305   IN      UINTN                     StartBit,
 306   IN      UINTN                     EndBit,
 307   IN      UINT8                     AndData
 308   );
 309
 310 /**
 311   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 312   bitwise inclusive OR, and writes the result back to the bit field in the
 313   8-bit port.
 314
 315   Reads the 8-bit PCI configuration register specified by Address, performs a
 316   bitwise AND followed by a bitwise inclusive OR between the read result and
 317   the value specified by AndData, and writes the result to the 8-bit PCI
 318   configuration register specified by Address. The value written to the PCI
 319   configuration register is returned. This function must guarantee that all PCI
 320   read and write operations are serialized. Extra left bits in both AndData and
 321   OrData are stripped.
 322
 323   If Address > 0x0FFFFFFF, then ASSERT().
 324   If the register specified by Address >= 0x100, then ASSERT().
 325   If StartBit is greater than 7, then ASSERT().
 326   If EndBit is greater than 7, then ASSERT().
 327   If EndBit is less than StartBit, then ASSERT().
 328
 329   @param  Address   PCI configuration register to write.
 330   @param  StartBit  The ordinal of the least significant bit in the bit field.
 331                     Range 0..7.
 332   @param  EndBit    The ordinal of the most significant bit in the bit field.
 333                     Range 0..7.
 334   @param  AndData   The value to AND with the PCI configuration register.
 335   @param  OrData    The value to OR with the result of the AND operation.
 336
 337   @return The value written back to the PCI configuration register.
 338
 339 **/
 340 UINT8
 341 EFIAPI
 342 PciCf8BitFieldAndThenOr8 (
 343   IN      UINTN                     Address,
 344   IN      UINTN                     StartBit,
 345   IN      UINTN                     EndBit,
 346   IN      UINT8                     AndData,
 347   IN      UINT8                     OrData
 348   );
 349
 350 /**
 351   Reads a 16-bit PCI configuration register.
 352
 353   Reads and returns the 16-bit PCI configuration register specified by Address.
 354   This function must guarantee that all PCI read and write operations are
 355   serialized.
 356
 357   If Address > 0x0FFFFFFF, then ASSERT().
 358   If Address is not aligned on a 16-bit boundary, then ASSERT().
 359   If the register specified by Address >= 0x100, then ASSERT().
 360
 361   @param  Address Address that encodes the PCI Bus, Device, Function and
 362                   Register.
 363
 364   @return The read value from the PCI configuration register.
 365
 366 **/
 367 UINT16
 368 EFIAPI
 369 PciCf8Read16 (
 370   IN      UINTN                     Address
 371   );
 372
 373 /**
 374   Writes a 16-bit PCI configuration register.
 375
 376   Writes the 16-bit PCI configuration register specified by Address with the
 377   value specified by Value. Value is returned. This function must guarantee
 378   that all PCI read and write operations are serialized.
 379
 380   If Address > 0x0FFFFFFF, then ASSERT().
 381   If Address is not aligned on a 16-bit boundary, then ASSERT().
 382   If the register specified by Address >= 0x100, then ASSERT().
 383
 384   @param  Address Address that encodes the PCI Bus, Device, Function and
 385                   Register.
 386   @param  Value   The value to write.
 387
 388   @return The value written to the PCI configuration register.
 389
 390 **/
 391 UINT16
 392 EFIAPI
 393 PciCf8Write16 (
 394   IN      UINTN                     Address,
 395   IN      UINT16                    Value
 396   );
 397
 398 /**
 399   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 400   a 16-bit value.
 401
 402   Reads the 16-bit PCI configuration register specified by Address, performs a
 403   bitwise inclusive OR between the read result and the value specified by
 404   OrData, and writes the result to the 16-bit PCI configuration register
 405   specified by Address. The value written to the PCI configuration register is
 406   returned. This function must guarantee that all PCI read and write operations
 407   are serialized.
 408
 409   If Address > 0x0FFFFFFF, then ASSERT().
 410   If Address is not aligned on a 16-bit boundary, then ASSERT().
 411   If the register specified by Address >= 0x100, then ASSERT().
 412
 413   @param  Address Address that encodes the PCI Bus, Device, Function and
 414                   Register.
 415   @param  OrData  The value to OR with the PCI configuration register.
 416
 417   @return The value written back to the PCI configuration register.
 418
 419 **/
 420 UINT16
 421 EFIAPI
 422 PciCf8Or16 (
 423   IN      UINTN                     Address,
 424   IN      UINT16                    OrData
 425   );
 426
 427 /**
 428   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 429   value.
 430
 431   Reads the 16-bit PCI configuration register specified by Address, performs a
 432   bitwise AND between the read result and the value specified by AndData, and
 433   writes the result to the 16-bit PCI configuration register specified by
 434   Address. The value written to the PCI configuration register is returned.
 435   This function must guarantee that all PCI read and write operations are
 436   serialized.
 437
 438   If Address > 0x0FFFFFFF, then ASSERT().
 439   If Address is not aligned on a 16-bit boundary, then ASSERT().
 440   If the register specified by Address >= 0x100, then ASSERT().
 441
 442   @param  Address Address that encodes the PCI Bus, Device, Function and
 443                   Register.
 444   @param  AndData The value to AND with the PCI configuration register.
 445
 446   @return The value written back to the PCI configuration register.
 447
 448 **/
 449 UINT16
 450 EFIAPI
 451 PciCf8And16 (
 452   IN      UINTN                     Address,
 453   IN      UINT16                    AndData
 454   );
 455
 456 /**
 457   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 458   value, followed a  bitwise inclusive OR with another 16-bit value.
 459
 460   Reads the 16-bit PCI configuration register specified by Address, performs a
 461   bitwise AND between the read result and the value specified by AndData,
 462   performs a bitwise inclusive OR between the result of the AND operation and
 463   the value specified by OrData, and writes the result to the 16-bit PCI
 464   configuration register specified by Address. The value written to the PCI
 465   configuration register is returned. This function must guarantee that all PCI
 466   read and write operations are serialized.
 467
 468   If Address > 0x0FFFFFFF, then ASSERT().
 469   If Address is not aligned on a 16-bit boundary, then ASSERT().
 470   If the register specified by Address >= 0x100, then ASSERT().
 471
 472   @param  Address Address that encodes the PCI Bus, Device, Function and
 473                   Register.
 474   @param  AndData The value to AND with the PCI configuration register.
 475   @param  OrData  The value to OR with the result of the AND operation.
 476
 477   @return The value written back to the PCI configuration register.
 478
 479 **/
 480 UINT16
 481 EFIAPI
 482 PciCf8AndThenOr16 (
 483   IN      UINTN                     Address,
 484   IN      UINT16                    AndData,
 485   IN      UINT16                    OrData
 486   );
 487
 488 /**
 489   Reads a bit field of a PCI configuration register.
 490
 491   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 492   specified by the StartBit and the EndBit. The value of the bit field is
 493   returned.
 494
 495   If Address > 0x0FFFFFFF, then ASSERT().
 496   If Address is not aligned on a 16-bit boundary, then ASSERT().
 497   If the register specified by Address >= 0x100, then ASSERT().
 498   If StartBit is greater than 15, then ASSERT().
 499   If EndBit is greater than 15, then ASSERT().
 500   If EndBit is less than StartBit, then ASSERT().
 501
 502   @param  Address   PCI configuration register to read.
 503   @param  StartBit  The ordinal of the least significant bit in the bit field.
 504                     Range 0..15.
 505   @param  EndBit    The ordinal of the most significant bit in the bit field.
 506                     Range 0..15.
 507
 508   @return The value of the bit field read from the PCI configuration register.
 509
 510 **/
 511 UINT16
 512 EFIAPI
 513 PciCf8BitFieldRead16 (
 514   IN      UINTN                     Address,
 515   IN      UINTN                     StartBit,
 516   IN      UINTN                     EndBit
 517   );
 518
 519 /**
 520   Writes a bit field to a PCI configuration register.
 521
 522   Writes Value to the bit field of the PCI configuration register. The bit
 523   field is specified by the StartBit and the EndBit. All other bits in the
 524   destination PCI configuration register are preserved. The new value of the
 525   16-bit register is returned.
 526
 527   If Address > 0x0FFFFFFF, then ASSERT().
 528   If Address is not aligned on a 16-bit boundary, then ASSERT().
 529   If the register specified by Address >= 0x100, then ASSERT().
 530   If StartBit is greater than 15, then ASSERT().
 531   If EndBit is greater than 15, then ASSERT().
 532   If EndBit is less than StartBit, then ASSERT().
 533
 534   @param  Address   PCI configuration register to write.
 535   @param  StartBit  The ordinal of the least significant bit in the bit field.
 536                     Range 0..15.
 537   @param  EndBit    The ordinal of the most significant bit in the bit field.
 538                     Range 0..15.
 539   @param  Value     New value of the bit field.
 540
 541   @return The value written back to the PCI configuration register.
 542
 543 **/
 544 UINT16
 545 EFIAPI
 546 PciCf8BitFieldWrite16 (
 547   IN      UINTN                     Address,
 548   IN      UINTN                     StartBit,
 549   IN      UINTN                     EndBit,
 550   IN      UINT16                    Value
 551   );
 552
 553 /**
 554   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 555   writes the result back to the bit field in the 16-bit port.
 556
 557   Reads the 16-bit PCI configuration register specified by Address, performs a
 558   bitwise inclusive OR between the read result and the value specified by
 559   OrData, and writes the result to the 16-bit PCI configuration register
 560   specified by Address. The value written to the PCI configuration register is
 561   returned. This function must guarantee that all PCI read and write operations
 562   are serialized. Extra left bits in OrData are stripped.
 563
 564   If Address > 0x0FFFFFFF, then ASSERT().
 565   If Address is not aligned on a 16-bit boundary, then ASSERT().
 566   If the register specified by Address >= 0x100, then ASSERT().
 567   If StartBit is greater than 15, then ASSERT().
 568   If EndBit is greater than 15, then ASSERT().
 569   If EndBit is less than StartBit, then ASSERT().
 570
 571   @param  Address   PCI configuration register to write.
 572   @param  StartBit  The ordinal of the least significant bit in the bit field.
 573                     Range 0..15.
 574   @param  EndBit    The ordinal of the most significant bit in the bit field.
 575                     Range 0..15.
 576   @param  OrData    The value to OR with the PCI configuration register.
 577
 578   @return The value written back to the PCI configuration register.
 579
 580 **/
 581 UINT16
 582 EFIAPI
 583 PciCf8BitFieldOr16 (
 584   IN      UINTN                     Address,
 585   IN      UINTN                     StartBit,
 586   IN      UINTN                     EndBit,
 587   IN      UINT16                    OrData
 588   );
 589
 590 /**
 591   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 592   AND, and writes the result back to the bit field in the 16-bit register.
 593
 594   Reads the 16-bit PCI configuration register specified by Address, performs a
 595   bitwise AND between the read result and the value specified by AndData, and
 596   writes the result to the 16-bit PCI configuration register specified by
 597   Address. The value written to the PCI configuration register is returned.
 598   This function must guarantee that all PCI read and write operations are
 599   serialized. Extra left bits in AndData are stripped.
 600
 601   If Address > 0x0FFFFFFF, then ASSERT().
 602   If Address is not aligned on a 16-bit boundary, then ASSERT().
 603   If the register specified by Address >= 0x100, then ASSERT().
 604   If StartBit is greater than 15, then ASSERT().
 605   If EndBit is greater than 15, then ASSERT().
 606   If EndBit is less than StartBit, then ASSERT().
 607
 608   @param  Address   PCI configuration register to write.
 609   @param  StartBit  The ordinal of the least significant bit in the bit field.
 610                     Range 0..15.
 611   @param  EndBit    The ordinal of the most significant bit in the bit field.
 612                     Range 0..15.
 613   @param  AndData   The value to AND with the PCI configuration register.
 614
 615   @return The value written back to the PCI configuration register.
 616
 617 **/
 618 UINT16
 619 EFIAPI
 620 PciCf8BitFieldAnd16 (
 621   IN      UINTN                     Address,
 622   IN      UINTN                     StartBit,
 623   IN      UINTN                     EndBit,
 624   IN      UINT16                    AndData
 625   );
 626
 627 /**
 628   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 629   bitwise inclusive OR, and writes the result back to the bit field in the
 630   16-bit port.
 631
 632   Reads the 16-bit PCI configuration register specified by Address, performs a
 633   bitwise AND followed by a bitwise inclusive OR between the read result and
 634   the value specified by AndData, and writes the result to the 16-bit PCI
 635   configuration register specified by Address. The value written to the PCI
 636   configuration register is returned. This function must guarantee that all PCI
 637   read and write operations are serialized. Extra left bits in both AndData and
 638   OrData are stripped.
 639
 640   If Address > 0x0FFFFFFF, then ASSERT().
 641   If Address is not aligned on a 16-bit boundary, then ASSERT().
 642   If the register specified by Address >= 0x100, then ASSERT().
 643   If StartBit is greater than 15, then ASSERT().
 644   If EndBit is greater than 15, then ASSERT().
 645   If EndBit is less than StartBit, then ASSERT().
 646
 647   @param  Address   PCI configuration register to write.
 648   @param  StartBit  The ordinal of the least significant bit in the bit field.
 649                     Range 0..15.
 650   @param  EndBit    The ordinal of the most significant bit in the bit field.
 651                     Range 0..15.
 652   @param  AndData   The value to AND with the PCI configuration register.
 653   @param  OrData    The value to OR with the result of the AND operation.
 654
 655   @return The value written back to the PCI configuration register.
 656
 657 **/
 658 UINT16
 659 EFIAPI
 660 PciCf8BitFieldAndThenOr16 (
 661   IN      UINTN                     Address,
 662   IN      UINTN                     StartBit,
 663   IN      UINTN                     EndBit,
 664   IN      UINT16                    AndData,
 665   IN      UINT16                    OrData
 666   );
 667
 668 /**
 669   Reads a 32-bit PCI configuration register.
 670
 671   Reads and returns the 32-bit PCI configuration register specified by Address.
 672   This function must guarantee that all PCI read and write operations are
 673   serialized.
 674
 675   If Address > 0x0FFFFFFF, then ASSERT().
 676   If Address is not aligned on a 32-bit boundary, then ASSERT().
 677   If the register specified by Address >= 0x100, then ASSERT().
 678
 679   @param  Address Address that encodes the PCI Bus, Device, Function and
 680                   Register.
 681
 682   @return The read value from the PCI configuration register.
 683
 684 **/
 685 UINT32
 686 EFIAPI
 687 PciCf8Read32 (
 688   IN      UINTN                     Address
 689   );
 690
 691 /**
 692   Writes a 32-bit PCI configuration register.
 693
 694   Writes the 32-bit PCI configuration register specified by Address with the
 695   value specified by Value. Value is returned. This function must guarantee
 696   that all PCI read and write operations are serialized.
 697
 698   If Address > 0x0FFFFFFF, then ASSERT().
 699   If Address is not aligned on a 32-bit boundary, then ASSERT().
 700   If the register specified by Address >= 0x100, then ASSERT().
 701
 702   @param  Address Address that encodes the PCI Bus, Device, Function and
 703                   Register.
 704   @param  Value   The value to write.
 705
 706   @return The value written to the PCI configuration register.
 707
 708 **/
 709 UINT32
 710 EFIAPI
 711 PciCf8Write32 (
 712   IN      UINTN                     Address,
 713   IN      UINT32                    Value
 714   );
 715
 716 /**
 717   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 718   a 32-bit value.
 719
 720   Reads the 32-bit PCI configuration register specified by Address, performs a
 721   bitwise inclusive OR between the read result and the value specified by
 722   OrData, and writes the result to the 32-bit PCI configuration register
 723   specified by Address. The value written to the PCI configuration register is
 724   returned. This function must guarantee that all PCI read and write operations
 725   are serialized.
 726
 727   If Address > 0x0FFFFFFF, then ASSERT().
 728   If Address is not aligned on a 32-bit boundary, then ASSERT().
 729   If the register specified by Address >= 0x100, then ASSERT().
 730
 731   @param  Address Address that encodes the PCI Bus, Device, Function and
 732                   Register.
 733   @param  OrData  The value to OR with the PCI configuration register.
 734
 735   @return The value written back to the PCI configuration register.
 736
 737 **/
 738 UINT32
 739 EFIAPI
 740 PciCf8Or32 (
 741   IN      UINTN                     Address,
 742   IN      UINT32                    OrData
 743   );
 744
 745 /**
 746   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 747   value.
 748
 749   Reads the 32-bit PCI configuration register specified by Address, performs a
 750   bitwise AND between the read result and the value specified by AndData, and
 751   writes the result to the 32-bit PCI configuration register specified by
 752   Address. The value written to the PCI configuration register is returned.
 753   This function must guarantee that all PCI read and write operations are
 754   serialized.
 755
 756   If Address > 0x0FFFFFFF, then ASSERT().
 757   If Address is not aligned on a 32-bit boundary, then ASSERT().
 758   If the register specified by Address >= 0x100, then ASSERT().
 759
 760   @param  Address Address that encodes the PCI Bus, Device, Function and
 761                   Register.
 762   @param  AndData The value to AND with the PCI configuration register.
 763
 764   @return The value written back to the PCI configuration register.
 765
 766 **/
 767 UINT32
 768 EFIAPI
 769 PciCf8And32 (
 770   IN      UINTN                     Address,
 771   IN      UINT32                    AndData
 772   );
 773
 774 /**
 775   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 776   value, followed a  bitwise inclusive OR with another 32-bit value.
 777
 778   Reads the 32-bit PCI configuration register specified by Address, performs a
 779   bitwise AND between the read result and the value specified by AndData,
 780   performs a bitwise inclusive OR between the result of the AND operation and
 781   the value specified by OrData, and writes the result to the 32-bit PCI
 782   configuration register specified by Address. The value written to the PCI
 783   configuration register is returned. This function must guarantee that all PCI
 784   read and write operations are serialized.
 785
 786   If Address > 0x0FFFFFFF, then ASSERT().
 787   If Address is not aligned on a 32-bit boundary, then ASSERT().
 788   If the register specified by Address >= 0x100, then ASSERT().
 789
 790   @param  Address Address that encodes the PCI Bus, Device, Function and
 791                   Register.
 792   @param  AndData The value to AND with the PCI configuration register.
 793   @param  OrData  The value to OR with the result of the AND operation.
 794
 795   @return The value written back to the PCI configuration register.
 796
 797 **/
 798 UINT32
 799 EFIAPI
 800 PciCf8AndThenOr32 (
 801   IN      UINTN                     Address,
 802   IN      UINT32                    AndData,
 803   IN      UINT32                    OrData
 804   );
 805
 806 /**
 807   Reads a bit field of a PCI configuration register.
 808
 809   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 810   specified by the StartBit and the EndBit. The value of the bit field is
 811   returned.
 812
 813   If Address > 0x0FFFFFFF, then ASSERT().
 814   If Address is not aligned on a 32-bit boundary, then ASSERT().
 815   If the register specified by Address >= 0x100, then ASSERT().
 816   If StartBit is greater than 31, then ASSERT().
 817   If EndBit is greater than 31, then ASSERT().
 818   If EndBit is less than StartBit, then ASSERT().
 819
 820   @param  Address   PCI configuration register to read.
 821   @param  StartBit  The ordinal of the least significant bit in the bit field.
 822                     Range 0..31.
 823   @param  EndBit    The ordinal of the most significant bit in the bit field.
 824                     Range 0..31.
 825
 826   @return The value of the bit field read from the PCI configuration register.
 827
 828 **/
 829 UINT32
 830 EFIAPI
 831 PciCf8BitFieldRead32 (
 832   IN      UINTN                     Address,
 833   IN      UINTN                     StartBit,
 834   IN      UINTN                     EndBit
 835   );
 836
 837 /**
 838   Writes a bit field to a PCI configuration register.
 839
 840   Writes Value to the bit field of the PCI configuration register. The bit
 841   field is specified by the StartBit and the EndBit. All other bits in the
 842   destination PCI configuration register are preserved. The new value of the
 843   32-bit register is returned.
 844
 845   If Address > 0x0FFFFFFF, then ASSERT().
 846   If Address is not aligned on a 32-bit boundary, then ASSERT().
 847   If the register specified by Address >= 0x100, then ASSERT().
 848   If StartBit is greater than 31, then ASSERT().
 849   If EndBit is greater than 31, then ASSERT().
 850   If EndBit is less than StartBit, then ASSERT().
 851
 852   @param  Address   PCI configuration register to write.
 853   @param  StartBit  The ordinal of the least significant bit in the bit field.
 854                     Range 0..31.
 855   @param  EndBit    The ordinal of the most significant bit in the bit field.
 856                     Range 0..31.
 857   @param  Value     New value of the bit field.
 858
 859   @return The value written back to the PCI configuration register.
 860
 861 **/
 862 UINT32
 863 EFIAPI
 864 PciCf8BitFieldWrite32 (
 865   IN      UINTN                     Address,
 866   IN      UINTN                     StartBit,
 867   IN      UINTN                     EndBit,
 868   IN      UINT32                    Value
 869   );
 870
 871 /**
 872   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 873   writes the result back to the bit field in the 32-bit port.
 874
 875   Reads the 32-bit PCI configuration register specified by Address, performs a
 876   bitwise inclusive OR between the read result and the value specified by
 877   OrData, and writes the result to the 32-bit PCI configuration register
 878   specified by Address. The value written to the PCI configuration register is
 879   returned. This function must guarantee that all PCI read and write operations
 880   are serialized. Extra left bits in OrData are stripped.
 881
 882   If Address > 0x0FFFFFFF, then ASSERT().
 883   If Address is not aligned on a 32-bit boundary, then ASSERT().
 884   If the register specified by Address >= 0x100, then ASSERT().
 885   If StartBit is greater than 31, then ASSERT().
 886   If EndBit is greater than 31, then ASSERT().
 887   If EndBit is less than StartBit, then ASSERT().
 888
 889   @param  Address   PCI configuration register to write.
 890   @param  StartBit  The ordinal of the least significant bit in the bit field.
 891                     Range 0..31.
 892   @param  EndBit    The ordinal of the most significant bit in the bit field.
 893                     Range 0..31.
 894   @param  OrData    The value to OR with the PCI configuration register.
 895
 896   @return The value written back to the PCI configuration register.
 897
 898 **/
 899 UINT32
 900 EFIAPI
 901 PciCf8BitFieldOr32 (
 902   IN      UINTN                     Address,
 903   IN      UINTN                     StartBit,
 904   IN      UINTN                     EndBit,
 905   IN      UINT32                    OrData
 906   );
 907
 908 /**
 909   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 910   AND, and writes the result back to the bit field in the 32-bit register.
 911
 912   Reads the 32-bit PCI configuration register specified by Address, performs a
 913   bitwise AND between the read result and the value specified by AndData, and
 914   writes the result to the 32-bit PCI configuration register specified by
 915   Address. The value written to the PCI configuration register is returned.
 916   This function must guarantee that all PCI read and write operations are
 917   serialized. Extra left bits in AndData are stripped.
 918
 919   If Address > 0x0FFFFFFF, then ASSERT().
 920   If Address is not aligned on a 32-bit boundary, then ASSERT().
 921   If the register specified by Address >= 0x100, then ASSERT().
 922   If StartBit is greater than 31, then ASSERT().
 923   If EndBit is greater than 31, then ASSERT().
 924   If EndBit is less than StartBit, then ASSERT().
 925
 926   @param  Address   PCI configuration register to write.
 927   @param  StartBit  The ordinal of the least significant bit in the bit field.
 928                     Range 0..31.
 929   @param  EndBit    The ordinal of the most significant bit in the bit field.
 930                     Range 0..31.
 931   @param  AndData   The value to AND with the PCI configuration register.
 932
 933   @return The value written back to the PCI configuration register.
 934
 935 **/
 936 UINT32
 937 EFIAPI
 938 PciCf8BitFieldAnd32 (
 939   IN      UINTN                     Address,
 940   IN      UINTN                     StartBit,
 941   IN      UINTN                     EndBit,
 942   IN      UINT32                    AndData
 943   );
 944
 945 /**
 946   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 947   bitwise inclusive OR, and writes the result back to the bit field in the
 948   32-bit port.
 949
 950   Reads the 32-bit PCI configuration register specified by Address, performs a
 951   bitwise AND followed by a bitwise inclusive OR between the read result and
 952   the value specified by AndData, and writes the result to the 32-bit PCI
 953   configuration register specified by Address. The value written to the PCI
 954   configuration register is returned. This function must guarantee that all PCI
 955   read and write operations are serialized. Extra left bits in both AndData and
 956   OrData are stripped.
 957
 958   If Address > 0x0FFFFFFF, then ASSERT().
 959   If Address is not aligned on a 32-bit boundary, then ASSERT().
 960   If the register specified by Address >= 0x100, then ASSERT().
 961   If StartBit is greater than 31, then ASSERT().
 962   If EndBit is greater than 31, then ASSERT().
 963   If EndBit is less than StartBit, then ASSERT().
 964
 965   @param  Address   PCI configuration register to write.
 966   @param  StartBit  The ordinal of the least significant bit in the bit field.
 967                     Range 0..31.
 968   @param  EndBit    The ordinal of the most significant bit in the bit field.
 969                     Range 0..31.
 970   @param  AndData   The value to AND with the PCI configuration register.
 971   @param  OrData    The value to OR with the result of the AND operation.
 972
 973   @return The value written back to the PCI configuration register.
 974
 975 **/
 976 UINT32
 977 EFIAPI
 978 PciCf8BitFieldAndThenOr32 (
 979   IN      UINTN                     Address,
 980   IN      UINTN                     StartBit,
 981   IN      UINTN                     EndBit,
 982   IN      UINT32                    AndData,
 983   IN      UINT32                    OrData
 984   );
 985
 986 /**
 987   Reads a range of PCI configuration registers into a caller supplied buffer.
 988
 989   Reads the range of PCI configuration registers specified by StartAddress and
 990   Size into the buffer specified by Buffer. This function only allows the PCI
 991   configuration registers from a single PCI function to be read. Size is
 992   returned. When possible 32-bit PCI configuration read cycles are used to read
 993   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 994   and 16-bit PCI configuration read cycles may be used at the beginning and the
 995   end of the range.
 996
 997   If StartAddress > 0x0FFFFFFF, then ASSERT().
 998   If the register specified by StartAddress >= 0x100, then ASSERT().
 999   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1000   If Size > 0 and Buffer is NULL, then ASSERT().
1001
1002   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1003                         Function and Register.
1004   @param  Size          Size in bytes of the transfer.
1005   @param  Buffer        Pointer to a buffer receiving the data read.
1006
1007   @return Size read from StartAddress.
1008
1009 **/
1010 UINTN
1011 EFIAPI
1012 PciCf8ReadBuffer (
1013   IN      UINTN                     StartAddress,
1014   IN      UINTN                     Size,
1015   OUT     VOID                      *Buffer
1016   );
1017
1018 /**
1019   Copies the data in a caller supplied buffer to a specified range of PCI
1020   configuration space.
1021
1022   Writes the range of PCI configuration registers specified by StartAddress and
1023   Size from the buffer specified by Buffer. This function only allows the PCI
1024   configuration registers from a single PCI function to be written. Size is
1025   returned. When possible 32-bit PCI configuration write cycles are used to
1026   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1027   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1028   and the end of the range.
1029
1030   If StartAddress > 0x0FFFFFFF, then ASSERT().
1031   If the register specified by StartAddress >= 0x100, then ASSERT().
1032   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1033   If Size > 0 and Buffer is NULL, then ASSERT().
1034
1035   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1036                         Function and Register.
1037   @param  Size          Size in bytes of the transfer.
1038   @param  Buffer        Pointer to a buffer containing the data to write.
1039
1040   @return Size written to StartAddress.
1041
1042 **/
1043 UINTN
1044 EFIAPI
1045 PciCf8WriteBuffer (
1046   IN      UINTN                     StartAddress,
1047   IN      UINTN                     Size,
1048   IN      VOID                      *Buffer
1049   );
1050
1051 #endif