MdePkg/Include/Library/PciLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space.
   3
   4   These functions perform PCI configuration cycles using the default PCI configuration
   5   access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
   6   or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
   7   alternate access method.  Modules will typically use the PCI Library for its PCI configuration
   8   accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
   9   PCI Express Library may be used in conjunction with the PCI Library.  The functionality of
  10   these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use
  11   explicit access methods.
  12
  13 Copyright (c) 2006 - 2008, Intel Corporation
  14 All rights reserved. This program and the accompanying materials
  15 are licensed and made available under the terms and conditions of the BSD License
  16 which accompanies this distribution.  The full text of the license may be found at
  17 http://opensource.org/licenses/bsd-license.php
  18
  19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  21
  22 **/
  23
  24 #ifndef __PCI_LIB_H__
  25 #define __PCI_LIB_H__
  26
  27 /**
  28   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  29   address that can be passed to the PCI Library functions.
  30
  31   @param  Bus       PCI Bus number. Range 0..255.
  32   @param  Device    PCI Device number. Range 0..31.
  33   @param  Function  PCI Function number. Range 0..7.
  34   @param  Register  PCI Register number. Range 0..255 for PCI. Range 0..4095
  35                     for PCI Express.
  36
  37   @return The encoded PCI address.
  38
  39 **/
  40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset)   \
  41   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  42
  43 /**
  44   Reads an 8-bit PCI configuration register.
  45
  46   Reads and returns the 8-bit PCI configuration register specified by Address.
  47   This function must guarantee that all PCI read and write operations are
  48   serialized.
  49
  50   If Address > 0x0FFFFFFF, then ASSERT().
  51
  52   @param  Address Address that encodes the PCI Bus, Device, Function and
  53                   Register.
  54
  55   @return The read value from the PCI configuration register.
  56
  57 **/
  58 UINT8
  59 EFIAPI
  60 PciRead8 (
  61   IN      UINTN                     Address
  62   );
  63
  64 /**
  65   Writes an 8-bit PCI configuration register.
  66
  67   Writes the 8-bit PCI configuration register specified by Address with the
  68   value specified by Value. Value is returned. This function must guarantee
  69   that all PCI read and write operations are serialized.
  70
  71   If Address > 0x0FFFFFFF, then ASSERT().
  72
  73   @param  Address Address that encodes the PCI Bus, Device, Function and
  74                   Register.
  75   @param  Value   The value to write.
  76
  77   @return The value written to the PCI configuration register.
  78
  79 **/
  80 UINT8
  81 EFIAPI
  82 PciWrite8 (
  83   IN      UINTN                     Address,
  84   IN      UINT8                     Value
  85   );
  86
  87 /**
  88   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  89   an 8-bit value.
  90
  91   Reads the 8-bit PCI configuration register specified by Address, performs a
  92   bitwise inclusive OR between the read result and the value specified by
  93   OrData, and writes the result to the 8-bit PCI configuration register
  94   specified by Address. The value written to the PCI configuration register is
  95   returned. This function must guarantee that all PCI read and write operations
  96   are serialized.
  97
  98   If Address > 0x0FFFFFFF, then ASSERT().
  99
 100   @param  Address Address that encodes the PCI Bus, Device, Function and
 101                   Register.
 102   @param  OrData  The value to OR with the PCI configuration register.
 103
 104   @return The value written back to the PCI configuration register.
 105
 106 **/
 107 UINT8
 108 EFIAPI
 109 PciOr8 (
 110   IN      UINTN                     Address,
 111   IN      UINT8                     OrData
 112   );
 113
 114 /**
 115   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 116   value.
 117
 118   Reads the 8-bit PCI configuration register specified by Address, performs a
 119   bitwise AND between the read result and the value specified by AndData, and
 120   writes the result to the 8-bit PCI configuration register specified by
 121   Address. The value written to the PCI configuration register is returned.
 122   This function must guarantee that all PCI read and write operations are
 123   serialized.
 124
 125   If Address > 0x0FFFFFFF, then ASSERT().
 126
 127   @param  Address Address that encodes the PCI Bus, Device, Function and
 128                   Register.
 129   @param  AndData The value to AND with the PCI configuration register.
 130
 131   @return The value written back to the PCI configuration register.
 132
 133 **/
 134 UINT8
 135 EFIAPI
 136 PciAnd8 (
 137   IN      UINTN                     Address,
 138   IN      UINT8                     AndData
 139   );
 140
 141 /**
 142   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 143   value, followed a  bitwise inclusive OR with another 8-bit value.
 144
 145   Reads the 8-bit PCI configuration register specified by Address, performs a
 146   bitwise AND between the read result and the value specified by AndData,
 147   performs a bitwise inclusive OR between the result of the AND operation and
 148   the value specified by OrData, and writes the result to the 8-bit PCI
 149   configuration register specified by Address. The value written to the PCI
 150   configuration register is returned. This function must guarantee that all PCI
 151   read and write operations are serialized.
 152
 153   If Address > 0x0FFFFFFF, then ASSERT().
 154
 155   @param  Address Address that encodes the PCI Bus, Device, Function and
 156                   Register.
 157   @param  AndData The value to AND with the PCI configuration register.
 158   @param  OrData  The value to OR with the result of the AND operation.
 159
 160   @return The value written back to the PCI configuration register.
 161
 162 **/
 163 UINT8
 164 EFIAPI
 165 PciAndThenOr8 (
 166   IN      UINTN                     Address,
 167   IN      UINT8                     AndData,
 168   IN      UINT8                     OrData
 169   );
 170
 171 /**
 172   Reads a bit field of a PCI configuration register.
 173
 174   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 175   specified by the StartBit and the EndBit. The value of the bit field is
 176   returned.
 177
 178   If Address > 0x0FFFFFFF, then ASSERT().
 179   If StartBit is greater than 7, then ASSERT().
 180   If EndBit is greater than 7, then ASSERT().
 181   If EndBit is less than StartBit, then ASSERT().
 182
 183   @param  Address   PCI configuration register to read.
 184   @param  StartBit  The ordinal of the least significant bit in the bit field.
 185                     Range 0..7.
 186   @param  EndBit    The ordinal of the most significant bit in the bit field.
 187                     Range 0..7.
 188
 189   @return The value of the bit field read from the PCI configuration register.
 190
 191 **/
 192 UINT8
 193 EFIAPI
 194 PciBitFieldRead8 (
 195   IN      UINTN                     Address,
 196   IN      UINTN                     StartBit,
 197   IN      UINTN                     EndBit
 198   );
 199
 200 /**
 201   Writes a bit field to a PCI configuration register.
 202
 203   Writes Value to the bit field of the PCI configuration register. The bit
 204   field is specified by the StartBit and the EndBit. All other bits in the
 205   destination PCI configuration register are preserved. The new value of the
 206   8-bit register is returned.
 207
 208   If Address > 0x0FFFFFFF, then ASSERT().
 209   If StartBit is greater than 7, then ASSERT().
 210   If EndBit is greater than 7, then ASSERT().
 211   If EndBit is less than StartBit, then ASSERT().
 212
 213   @param  Address   PCI configuration register to write.
 214   @param  StartBit  The ordinal of the least significant bit in the bit field.
 215                     Range 0..7.
 216   @param  EndBit    The ordinal of the most significant bit in the bit field.
 217                     Range 0..7.
 218   @param  Value     New value of the bit field.
 219
 220   @return The value written back to the PCI configuration register.
 221
 222 **/
 223 UINT8
 224 EFIAPI
 225 PciBitFieldWrite8 (
 226   IN      UINTN                     Address,
 227   IN      UINTN                     StartBit,
 228   IN      UINTN                     EndBit,
 229   IN      UINT8                     Value
 230   );
 231
 232 /**
 233   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 234   writes the result back to the bit field in the 8-bit port.
 235
 236   Reads the 8-bit PCI configuration register specified by Address, performs a
 237   bitwise inclusive OR between the read result and the value specified by
 238   OrData, and writes the result to the 8-bit PCI configuration register
 239   specified by Address. The value written to the PCI configuration register is
 240   returned. This function must guarantee that all PCI read and write operations
 241   are serialized. Extra left bits in OrData are stripped.
 242
 243   If Address > 0x0FFFFFFF, then ASSERT().
 244   If StartBit is greater than 7, then ASSERT().
 245   If EndBit is greater than 7, then ASSERT().
 246   If EndBit is less than StartBit, then ASSERT().
 247
 248   @param  Address   PCI configuration register to write.
 249   @param  StartBit  The ordinal of the least significant bit in the bit field.
 250                     Range 0..7.
 251   @param  EndBit    The ordinal of the most significant bit in the bit field.
 252                     Range 0..7.
 253   @param  OrData    The value to OR with the PCI configuration register.
 254
 255   @return The value written back to the PCI configuration register.
 256
 257 **/
 258 UINT8
 259 EFIAPI
 260 PciBitFieldOr8 (
 261   IN      UINTN                     Address,
 262   IN      UINTN                     StartBit,
 263   IN      UINTN                     EndBit,
 264   IN      UINT8                     OrData
 265   );
 266
 267 /**
 268   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 269   AND, and writes the result back to the bit field in the 8-bit register.
 270
 271   Reads the 8-bit PCI configuration register specified by Address, performs a
 272   bitwise AND between the read result and the value specified by AndData, and
 273   writes the result to the 8-bit PCI configuration register specified by
 274   Address. The value written to the PCI configuration register is returned.
 275   This function must guarantee that all PCI read and write operations are
 276   serialized. Extra left bits in AndData are stripped.
 277
 278   If Address > 0x0FFFFFFF, then ASSERT().
 279   If StartBit is greater than 7, then ASSERT().
 280   If EndBit is greater than 7, then ASSERT().
 281   If EndBit is less than StartBit, then ASSERT().
 282
 283   @param  Address   PCI configuration register to write.
 284   @param  StartBit  The ordinal of the least significant bit in the bit field.
 285                     Range 0..7.
 286   @param  EndBit    The ordinal of the most significant bit in the bit field.
 287                     Range 0..7.
 288   @param  AndData   The value to AND with the PCI configuration register.
 289
 290   @return The value written back to the PCI configuration register.
 291
 292 **/
 293 UINT8
 294 EFIAPI
 295 PciBitFieldAnd8 (
 296   IN      UINTN                     Address,
 297   IN      UINTN                     StartBit,
 298   IN      UINTN                     EndBit,
 299   IN      UINT8                     AndData
 300   );
 301
 302 /**
 303   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 304   bitwise inclusive OR, and writes the result back to the bit field in the
 305   8-bit port.
 306
 307   Reads the 8-bit PCI configuration register specified by Address, performs a
 308   bitwise AND followed by a bitwise inclusive OR between the read result and
 309   the value specified by AndData, and writes the result to the 8-bit PCI
 310   configuration register specified by Address. The value written to the PCI
 311   configuration register is returned. This function must guarantee that all PCI
 312   read and write operations are serialized. Extra left bits in both AndData and
 313   OrData are stripped.
 314
 315   If Address > 0x0FFFFFFF, then ASSERT().
 316   If StartBit is greater than 7, then ASSERT().
 317   If EndBit is greater than 7, then ASSERT().
 318   If EndBit is less than StartBit, then ASSERT().
 319
 320   @param  Address   PCI configuration register to write.
 321   @param  StartBit  The ordinal of the least significant bit in the bit field.
 322                     Range 0..7.
 323   @param  EndBit    The ordinal of the most significant bit in the bit field.
 324                     Range 0..7.
 325   @param  AndData   The value to AND with the PCI configuration register.
 326   @param  OrData    The value to OR with the result of the AND operation.
 327
 328   @return The value written back to the PCI configuration register.
 329
 330 **/
 331 UINT8
 332 EFIAPI
 333 PciBitFieldAndThenOr8 (
 334   IN      UINTN                     Address,
 335   IN      UINTN                     StartBit,
 336   IN      UINTN                     EndBit,
 337   IN      UINT8                     AndData,
 338   IN      UINT8                     OrData
 339   );
 340
 341 /**
 342   Reads a 16-bit PCI configuration register.
 343
 344   Reads and returns the 16-bit PCI configuration register specified by Address.
 345   This function must guarantee that all PCI read and write operations are
 346   serialized.
 347
 348   If Address > 0x0FFFFFFF, then ASSERT().
 349   If Address is not aligned on a 16-bit boundary, then ASSERT().
 350
 351   @param  Address Address that encodes the PCI Bus, Device, Function and
 352                   Register.
 353
 354   @return The read value from the PCI configuration register.
 355
 356 **/
 357 UINT16
 358 EFIAPI
 359 PciRead16 (
 360   IN      UINTN                     Address
 361   );
 362
 363 /**
 364   Writes a 16-bit PCI configuration register.
 365
 366   Writes the 16-bit PCI configuration register specified by Address with the
 367   value specified by Value. Value is returned. This function must guarantee
 368   that all PCI read and write operations are serialized.
 369
 370   If Address > 0x0FFFFFFF, then ASSERT().
 371   If Address is not aligned on a 16-bit boundary, then ASSERT().
 372
 373   @param  Address Address that encodes the PCI Bus, Device, Function and
 374                   Register.
 375   @param  Value   The value to write.
 376
 377   @return The value written to the PCI configuration register.
 378
 379 **/
 380 UINT16
 381 EFIAPI
 382 PciWrite16 (
 383   IN      UINTN                     Address,
 384   IN      UINT16                    Value
 385   );
 386
 387 /**
 388   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 389   a 16-bit value.
 390
 391   Reads the 16-bit PCI configuration register specified by Address, performs a
 392   bitwise inclusive OR between the read result and the value specified by
 393   OrData, and writes the result to the 16-bit PCI configuration register
 394   specified by Address. The value written to the PCI configuration register is
 395   returned. This function must guarantee that all PCI read and write operations
 396   are serialized.
 397
 398   If Address > 0x0FFFFFFF, then ASSERT().
 399   If Address is not aligned on a 16-bit boundary, then ASSERT().
 400
 401   @param  Address Address that encodes the PCI Bus, Device, Function and
 402                   Register.
 403   @param  OrData  The value to OR with the PCI configuration register.
 404
 405   @return The value written back to the PCI configuration register.
 406
 407 **/
 408 UINT16
 409 EFIAPI
 410 PciOr16 (
 411   IN      UINTN                     Address,
 412   IN      UINT16                    OrData
 413   );
 414
 415 /**
 416   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 417   value.
 418
 419   Reads the 16-bit PCI configuration register specified by Address, performs a
 420   bitwise AND between the read result and the value specified by AndData, and
 421   writes the result to the 16-bit PCI configuration register specified by
 422   Address. The value written to the PCI configuration register is returned.
 423   This function must guarantee that all PCI read and write operations are
 424   serialized.
 425
 426   If Address > 0x0FFFFFFF, then ASSERT().
 427   If Address is not aligned on a 16-bit boundary, then ASSERT().
 428
 429   @param  Address Address that encodes the PCI Bus, Device, Function and
 430                   Register.
 431   @param  AndData The value to AND with the PCI configuration register.
 432
 433   @return The value written back to the PCI configuration register.
 434
 435 **/
 436 UINT16
 437 EFIAPI
 438 PciAnd16 (
 439   IN      UINTN                     Address,
 440   IN      UINT16                    AndData
 441   );
 442
 443 /**
 444   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 445   value, followed a  bitwise inclusive OR with another 16-bit value.
 446
 447   Reads the 16-bit PCI configuration register specified by Address, performs a
 448   bitwise AND between the read result and the value specified by AndData,
 449   performs a bitwise inclusive OR between the result of the AND operation and
 450   the value specified by OrData, and writes the result to the 16-bit PCI
 451   configuration register specified by Address. The value written to the PCI
 452   configuration register is returned. This function must guarantee that all PCI
 453   read and write operations are serialized.
 454
 455   If Address > 0x0FFFFFFF, then ASSERT().
 456   If Address is not aligned on a 16-bit boundary, then ASSERT().
 457
 458   @param  Address Address that encodes the PCI Bus, Device, Function and
 459                   Register.
 460   @param  AndData The value to AND with the PCI configuration register.
 461   @param  OrData  The value to OR with the result of the AND operation.
 462
 463   @return The value written back to the PCI configuration register.
 464
 465 **/
 466 UINT16
 467 EFIAPI
 468 PciAndThenOr16 (
 469   IN      UINTN                     Address,
 470   IN      UINT16                    AndData,
 471   IN      UINT16                    OrData
 472   );
 473
 474 /**
 475   Reads a bit field of a PCI configuration register.
 476
 477   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 478   specified by the StartBit and the EndBit. The value of the bit field is
 479   returned.
 480
 481   If Address > 0x0FFFFFFF, then ASSERT().
 482   If Address is not aligned on a 16-bit boundary, then ASSERT().
 483   If StartBit is greater than 15, then ASSERT().
 484   If EndBit is greater than 15, then ASSERT().
 485   If EndBit is less than StartBit, then ASSERT().
 486
 487   @param  Address   PCI configuration register to read.
 488   @param  StartBit  The ordinal of the least significant bit in the bit field.
 489                     Range 0..15.
 490   @param  EndBit    The ordinal of the most significant bit in the bit field.
 491                     Range 0..15.
 492
 493   @return The value of the bit field read from the PCI configuration register.
 494
 495 **/
 496 UINT16
 497 EFIAPI
 498 PciBitFieldRead16 (
 499   IN      UINTN                     Address,
 500   IN      UINTN                     StartBit,
 501   IN      UINTN                     EndBit
 502   );
 503
 504 /**
 505   Writes a bit field to a PCI configuration register.
 506
 507   Writes Value to the bit field of the PCI configuration register. The bit
 508   field is specified by the StartBit and the EndBit. All other bits in the
 509   destination PCI configuration register are preserved. The new value of the
 510   16-bit register is returned.
 511
 512   If Address > 0x0FFFFFFF, then ASSERT().
 513   If Address is not aligned on a 16-bit boundary, then ASSERT().
 514   If StartBit is greater than 15, then ASSERT().
 515   If EndBit is greater than 15, then ASSERT().
 516   If EndBit is less than StartBit, then ASSERT().
 517
 518   @param  Address   PCI configuration register to write.
 519   @param  StartBit  The ordinal of the least significant bit in the bit field.
 520                     Range 0..15.
 521   @param  EndBit    The ordinal of the most significant bit in the bit field.
 522                     Range 0..15.
 523   @param  Value     New value of the bit field.
 524
 525   @return The value written back to the PCI configuration register.
 526
 527 **/
 528 UINT16
 529 EFIAPI
 530 PciBitFieldWrite16 (
 531   IN      UINTN                     Address,
 532   IN      UINTN                     StartBit,
 533   IN      UINTN                     EndBit,
 534   IN      UINT16                    Value
 535   );
 536
 537 /**
 538   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 539   writes the result back to the bit field in the 16-bit port.
 540
 541   Reads the 16-bit PCI configuration register specified by Address, performs a
 542   bitwise inclusive OR between the read result and the value specified by
 543   OrData, and writes the result to the 16-bit PCI configuration register
 544   specified by Address. The value written to the PCI configuration register is
 545   returned. This function must guarantee that all PCI read and write operations
 546   are serialized. Extra left bits in OrData are stripped.
 547
 548   If Address > 0x0FFFFFFF, then ASSERT().
 549   If Address is not aligned on a 16-bit boundary, then ASSERT().
 550   If StartBit is greater than 15, then ASSERT().
 551   If EndBit is greater than 15, then ASSERT().
 552   If EndBit is less than StartBit, then ASSERT().
 553
 554   @param  Address   PCI configuration register to write.
 555   @param  StartBit  The ordinal of the least significant bit in the bit field.
 556                     Range 0..15.
 557   @param  EndBit    The ordinal of the most significant bit in the bit field.
 558                     Range 0..15.
 559   @param  OrData    The value to OR with the PCI configuration register.
 560
 561   @return The value written back to the PCI configuration register.
 562
 563 **/
 564 UINT16
 565 EFIAPI
 566 PciBitFieldOr16 (
 567   IN      UINTN                     Address,
 568   IN      UINTN                     StartBit,
 569   IN      UINTN                     EndBit,
 570   IN      UINT16                    OrData
 571   );
 572
 573 /**
 574   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 575   AND, and writes the result back to the bit field in the 16-bit register.
 576
 577   Reads the 16-bit PCI configuration register specified by Address, performs a
 578   bitwise AND between the read result and the value specified by AndData, and
 579   writes the result to the 16-bit PCI configuration register specified by
 580   Address. The value written to the PCI configuration register is returned.
 581   This function must guarantee that all PCI read and write operations are
 582   serialized. Extra left bits in AndData are stripped.
 583
 584   If Address > 0x0FFFFFFF, then ASSERT().
 585   If Address is not aligned on a 16-bit boundary, then ASSERT().
 586   If StartBit is greater than 15, then ASSERT().
 587   If EndBit is greater than 15, then ASSERT().
 588   If EndBit is less than StartBit, then ASSERT().
 589
 590   @param  Address   PCI configuration register to write.
 591   @param  StartBit  The ordinal of the least significant bit in the bit field.
 592                     Range 0..15.
 593   @param  EndBit    The ordinal of the most significant bit in the bit field.
 594                     Range 0..15.
 595   @param  AndData   The value to AND with the PCI configuration register.
 596
 597   @return The value written back to the PCI configuration register.
 598
 599 **/
 600 UINT16
 601 EFIAPI
 602 PciBitFieldAnd16 (
 603   IN      UINTN                     Address,
 604   IN      UINTN                     StartBit,
 605   IN      UINTN                     EndBit,
 606   IN      UINT16                    AndData
 607   );
 608
 609 /**
 610   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 611   bitwise inclusive OR, and writes the result back to the bit field in the
 612   16-bit port.
 613
 614   Reads the 16-bit PCI configuration register specified by Address, performs a
 615   bitwise AND followed by a bitwise inclusive OR between the read result and
 616   the value specified by AndData, and writes the result to the 16-bit PCI
 617   configuration register specified by Address. The value written to the PCI
 618   configuration register is returned. This function must guarantee that all PCI
 619   read and write operations are serialized. Extra left bits in both AndData and
 620   OrData are stripped.
 621
 622   If Address > 0x0FFFFFFF, then ASSERT().
 623   If Address is not aligned on a 16-bit boundary, then ASSERT().
 624   If StartBit is greater than 15, then ASSERT().
 625   If EndBit is greater than 15, then ASSERT().
 626   If EndBit is less than StartBit, then ASSERT().
 627
 628   @param  Address   PCI configuration register to write.
 629   @param  StartBit  The ordinal of the least significant bit in the bit field.
 630                     Range 0..15.
 631   @param  EndBit    The ordinal of the most significant bit in the bit field.
 632                     Range 0..15.
 633   @param  AndData   The value to AND with the PCI configuration register.
 634   @param  OrData    The value to OR with the result of the AND operation.
 635
 636   @return The value written back to the PCI configuration register.
 637
 638 **/
 639 UINT16
 640 EFIAPI
 641 PciBitFieldAndThenOr16 (
 642   IN      UINTN                     Address,
 643   IN      UINTN                     StartBit,
 644   IN      UINTN                     EndBit,
 645   IN      UINT16                    AndData,
 646   IN      UINT16                    OrData
 647   );
 648
 649 /**
 650   Reads a 32-bit PCI configuration register.
 651
 652   Reads and returns the 32-bit PCI configuration register specified by Address.
 653   This function must guarantee that all PCI read and write operations are
 654   serialized.
 655
 656   If Address > 0x0FFFFFFF, then ASSERT().
 657   If Address is not aligned on a 32-bit boundary, then ASSERT().
 658
 659   @param  Address Address that encodes the PCI Bus, Device, Function and
 660                   Register.
 661
 662   @return The read value from the PCI configuration register.
 663
 664 **/
 665 UINT32
 666 EFIAPI
 667 PciRead32 (
 668   IN      UINTN                     Address
 669   );
 670
 671 /**
 672   Writes a 32-bit PCI configuration register.
 673
 674   Writes the 32-bit PCI configuration register specified by Address with the
 675   value specified by Value. Value is returned. This function must guarantee
 676   that all PCI read and write operations are serialized.
 677
 678   If Address > 0x0FFFFFFF, then ASSERT().
 679   If Address is not aligned on a 32-bit boundary, then ASSERT().
 680
 681   @param  Address Address that encodes the PCI Bus, Device, Function and
 682                   Register.
 683   @param  Value   The value to write.
 684
 685   @return The value written to the PCI configuration register.
 686
 687 **/
 688 UINT32
 689 EFIAPI
 690 PciWrite32 (
 691   IN      UINTN                     Address,
 692   IN      UINT32                    Value
 693   );
 694
 695 /**
 696   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 697   a 32-bit value.
 698
 699   Reads the 32-bit PCI configuration register specified by Address, performs a
 700   bitwise inclusive OR between the read result and the value specified by
 701   OrData, and writes the result to the 32-bit PCI configuration register
 702   specified by Address. The value written to the PCI configuration register is
 703   returned. This function must guarantee that all PCI read and write operations
 704   are serialized.
 705
 706   If Address > 0x0FFFFFFF, then ASSERT().
 707   If Address is not aligned on a 32-bit boundary, then ASSERT().
 708
 709   @param  Address Address that encodes the PCI Bus, Device, Function and
 710                   Register.
 711   @param  OrData  The value to OR with the PCI configuration register.
 712
 713   @return The value written back to the PCI configuration register.
 714
 715 **/
 716 UINT32
 717 EFIAPI
 718 PciOr32 (
 719   IN      UINTN                     Address,
 720   IN      UINT32                    OrData
 721   );
 722
 723 /**
 724   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 725   value.
 726
 727   Reads the 32-bit PCI configuration register specified by Address, performs a
 728   bitwise AND between the read result and the value specified by AndData, and
 729   writes the result to the 32-bit PCI configuration register specified by
 730   Address. The value written to the PCI configuration register is returned.
 731   This function must guarantee that all PCI read and write operations are
 732   serialized.
 733
 734   If Address > 0x0FFFFFFF, then ASSERT().
 735   If Address is not aligned on a 32-bit boundary, then ASSERT().
 736
 737   @param  Address Address that encodes the PCI Bus, Device, Function and
 738                   Register.
 739   @param  AndData The value to AND with the PCI configuration register.
 740
 741   @return The value written back to the PCI configuration register.
 742
 743 **/
 744 UINT32
 745 EFIAPI
 746 PciAnd32 (
 747   IN      UINTN                     Address,
 748   IN      UINT32                    AndData
 749   );
 750
 751 /**
 752   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 753   value, followed a  bitwise inclusive OR with another 32-bit value.
 754
 755   Reads the 32-bit PCI configuration register specified by Address, performs a
 756   bitwise AND between the read result and the value specified by AndData,
 757   performs a bitwise inclusive OR between the result of the AND operation and
 758   the value specified by OrData, and writes the result to the 32-bit PCI
 759   configuration register specified by Address. The value written to the PCI
 760   configuration register is returned. This function must guarantee that all PCI
 761   read and write operations are serialized.
 762
 763   If Address > 0x0FFFFFFF, then ASSERT().
 764   If Address is not aligned on a 32-bit boundary, then ASSERT().
 765
 766   @param  Address Address that encodes the PCI Bus, Device, Function and
 767                   Register.
 768   @param  AndData The value to AND with the PCI configuration register.
 769   @param  OrData  The value to OR with the result of the AND operation.
 770
 771   @return The value written back to the PCI configuration register.
 772
 773 **/
 774 UINT32
 775 EFIAPI
 776 PciAndThenOr32 (
 777   IN      UINTN                     Address,
 778   IN      UINT32                    AndData,
 779   IN      UINT32                    OrData
 780   );
 781
 782 /**
 783   Reads a bit field of a PCI configuration register.
 784
 785   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 786   specified by the StartBit and the EndBit. The value of the bit field is
 787   returned.
 788
 789   If Address > 0x0FFFFFFF, then ASSERT().
 790   If Address is not aligned on a 32-bit boundary, then ASSERT().
 791   If StartBit is greater than 31, then ASSERT().
 792   If EndBit is greater than 31, then ASSERT().
 793   If EndBit is less than StartBit, then ASSERT().
 794
 795   @param  Address   PCI configuration register to read.
 796   @param  StartBit  The ordinal of the least significant bit in the bit field.
 797                     Range 0..31.
 798   @param  EndBit    The ordinal of the most significant bit in the bit field.
 799                     Range 0..31.
 800
 801   @return The value of the bit field read from the PCI configuration register.
 802
 803 **/
 804 UINT32
 805 EFIAPI
 806 PciBitFieldRead32 (
 807   IN      UINTN                     Address,
 808   IN      UINTN                     StartBit,
 809   IN      UINTN                     EndBit
 810   );
 811
 812 /**
 813   Writes a bit field to a PCI configuration register.
 814
 815   Writes Value to the bit field of the PCI configuration register. The bit
 816   field is specified by the StartBit and the EndBit. All other bits in the
 817   destination PCI configuration register are preserved. The new value of the
 818   32-bit register is returned.
 819
 820   If Address > 0x0FFFFFFF, then ASSERT().
 821   If Address is not aligned on a 32-bit boundary, then ASSERT().
 822   If StartBit is greater than 31, then ASSERT().
 823   If EndBit is greater than 31, then ASSERT().
 824   If EndBit is less than StartBit, then ASSERT().
 825
 826   @param  Address   PCI configuration register to write.
 827   @param  StartBit  The ordinal of the least significant bit in the bit field.
 828                     Range 0..31.
 829   @param  EndBit    The ordinal of the most significant bit in the bit field.
 830                     Range 0..31.
 831   @param  Value     New value of the bit field.
 832
 833   @return The value written back to the PCI configuration register.
 834
 835 **/
 836 UINT32
 837 EFIAPI
 838 PciBitFieldWrite32 (
 839   IN      UINTN                     Address,
 840   IN      UINTN                     StartBit,
 841   IN      UINTN                     EndBit,
 842   IN      UINT32                    Value
 843   );
 844
 845 /**
 846   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 847   writes the result back to the bit field in the 32-bit port.
 848
 849   Reads the 32-bit PCI configuration register specified by Address, performs a
 850   bitwise inclusive OR between the read result and the value specified by
 851   OrData, and writes the result to the 32-bit PCI configuration register
 852   specified by Address. The value written to the PCI configuration register is
 853   returned. This function must guarantee that all PCI read and write operations
 854   are serialized. Extra left bits in OrData are stripped.
 855
 856   If Address > 0x0FFFFFFF, then ASSERT().
 857   If Address is not aligned on a 32-bit boundary, then ASSERT().
 858   If StartBit is greater than 31, then ASSERT().
 859   If EndBit is greater than 31, then ASSERT().
 860   If EndBit is less than StartBit, then ASSERT().
 861
 862   @param  Address   PCI configuration register to write.
 863   @param  StartBit  The ordinal of the least significant bit in the bit field.
 864                     Range 0..31.
 865   @param  EndBit    The ordinal of the most significant bit in the bit field.
 866                     Range 0..31.
 867   @param  OrData    The value to OR with the PCI configuration register.
 868
 869   @return The value written back to the PCI configuration register.
 870
 871 **/
 872 UINT32
 873 EFIAPI
 874 PciBitFieldOr32 (
 875   IN      UINTN                     Address,
 876   IN      UINTN                     StartBit,
 877   IN      UINTN                     EndBit,
 878   IN      UINT32                    OrData
 879   );
 880
 881 /**
 882   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 883   AND, and writes the result back to the bit field in the 32-bit register.
 884
 885   Reads the 32-bit PCI configuration register specified by Address, performs a
 886   bitwise AND between the read result and the value specified by AndData, and
 887   writes the result to the 32-bit PCI configuration register specified by
 888   Address. The value written to the PCI configuration register is returned.
 889   This function must guarantee that all PCI read and write operations are
 890   serialized. Extra left bits in AndData are stripped.
 891
 892   If Address > 0x0FFFFFFF, then ASSERT().
 893   If Address is not aligned on a 32-bit boundary, then ASSERT().
 894   If StartBit is greater than 31, then ASSERT().
 895   If EndBit is greater than 31, then ASSERT().
 896   If EndBit is less than StartBit, then ASSERT().
 897
 898   @param  Address   PCI configuration register to write.
 899   @param  StartBit  The ordinal of the least significant bit in the bit field.
 900                     Range 0..31.
 901   @param  EndBit    The ordinal of the most significant bit in the bit field.
 902                     Range 0..31.
 903   @param  AndData   The value to AND with the PCI configuration register.
 904
 905   @return The value written back to the PCI configuration register.
 906
 907 **/
 908 UINT32
 909 EFIAPI
 910 PciBitFieldAnd32 (
 911   IN      UINTN                     Address,
 912   IN      UINTN                     StartBit,
 913   IN      UINTN                     EndBit,
 914   IN      UINT32                    AndData
 915   );
 916
 917 /**
 918   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 919   bitwise inclusive OR, and writes the result back to the bit field in the
 920   32-bit port.
 921
 922   Reads the 32-bit PCI configuration register specified by Address, performs a
 923   bitwise AND followed by a bitwise inclusive OR between the read result and
 924   the value specified by AndData, and writes the result to the 32-bit PCI
 925   configuration register specified by Address. The value written to the PCI
 926   configuration register is returned. This function must guarantee that all PCI
 927   read and write operations are serialized. Extra left bits in both AndData and
 928   OrData are stripped.
 929
 930   If Address > 0x0FFFFFFF, then ASSERT().
 931   If Address is not aligned on a 32-bit boundary, then ASSERT().
 932   If StartBit is greater than 31, then ASSERT().
 933   If EndBit is greater than 31, then ASSERT().
 934   If EndBit is less than StartBit, then ASSERT().
 935
 936   @param  Address   PCI configuration register to write.
 937   @param  StartBit  The ordinal of the least significant bit in the bit field.
 938                     Range 0..31.
 939   @param  EndBit    The ordinal of the most significant bit in the bit field.
 940                     Range 0..31.
 941   @param  AndData   The value to AND with the PCI configuration register.
 942   @param  OrData    The value to OR with the result of the AND operation.
 943
 944   @return The value written back to the PCI configuration register.
 945
 946 **/
 947 UINT32
 948 EFIAPI
 949 PciBitFieldAndThenOr32 (
 950   IN      UINTN                     Address,
 951   IN      UINTN                     StartBit,
 952   IN      UINTN                     EndBit,
 953   IN      UINT32                    AndData,
 954   IN      UINT32                    OrData
 955   );
 956
 957 /**
 958   Reads a range of PCI configuration registers into a caller supplied buffer.
 959
 960   Reads the range of PCI configuration registers specified by StartAddress and
 961   Size into the buffer specified by Buffer. This function only allows the PCI
 962   configuration registers from a single PCI function to be read. Size is
 963   returned. When possible 32-bit PCI configuration read cycles are used to read
 964   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 965   and 16-bit PCI configuration read cycles may be used at the beginning and the
 966   end of the range.
 967
 968   If StartAddress > 0x0FFFFFFF, then ASSERT().
 969   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 970   If Size > 0 and Buffer is NULL, then ASSERT().
 971
 972   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 973                         Function and Register.
 974   @param  Size          Size in bytes of the transfer.
 975   @param  Buffer        Pointer to a buffer receiving the data read.
 976
 977   @return Size
 978
 979 **/
 980 UINTN
 981 EFIAPI
 982 PciReadBuffer (
 983   IN      UINTN                     StartAddress,
 984   IN      UINTN                     Size,
 985   OUT     VOID                      *Buffer
 986   );
 987
 988 /**
 989   Copies the data in a caller supplied buffer to a specified range of PCI
 990   configuration space.
 991
 992   Writes the range of PCI configuration registers specified by StartAddress and
 993   Size from the buffer specified by Buffer. This function only allows the PCI
 994   configuration registers from a single PCI function to be written. Size is
 995   returned. When possible 32-bit PCI configuration write cycles are used to
 996   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
 997   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
 998   and the end of the range.
 999
1000   If StartAddress > 0x0FFFFFFF, then ASSERT().
1001   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1002   If Size > 0 and Buffer is NULL, then ASSERT().
1003
1004   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1005                         Function and Register.
1006   @param  Size          Size in bytes of the transfer.
1007   @param  Buffer        Pointer to a buffer containing the data to write.
1008
1009   @return Size written to StartAddress.
1010
1011 **/
1012 UINTN
1013 EFIAPI
1014 PciWriteBuffer (
1015   IN      UINTN                     StartAddress,
1016   IN      UINTN                     Size,
1017   IN      VOID                      *Buffer
1018   );
1019
1020 #endif