MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Functions accessing PCI configuration registers on any supported PCI segment
   3
   4   Copyright (c) 2006, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __PCI_SEGMENT_LIB__
  16 #define __PCI_SEGMENT_LIB__
  17
  18
  19 /**
  20   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  21   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  22
  23   Computes an address that is compatible with the PCI Segment Library functions.
  24   The unused upper bits of Segment, Bus, Device, Function,
  25   and Register are stripped prior to the generation of the address.
  26
  27   @param  Segment   PCI Segment number.  Range 0..65535.
  28   @param  Bus       PCI Bus number.  Range 0..255.
  29   @param  Device    PCI Device number.  Range 0..31.
  30   @param  Function  PCI Function number.  Range 0..7.
  31   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  32
  33   @return The address that is compatible with the PCI Segment Library functions.
  34
  35 **/
  36 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
  37   ( ((Register) & 0xfff)              | \
  38     (((Function) & 0x07) << 12)       | \
  39     (((Device) & 0x1f) << 15)         | \
  40     (((Bus) & 0xff) << 20)            | \
  41     (LShiftU64((Segment) & 0xffff, 32)) \
  42   )
  43
  44 /**
  45   Reads an 8-bit PCI configuration register.
  46
  47   Reads and returns the 8-bit PCI configuration register specified by Address.
  48   This function must guarantee that all PCI read and write operations are serialized.
  49   If any reserved bits in Address are set, then ASSERT().
  50
  51   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  52
  53   @return The 8-bit PCI configuration register specified by Address.
  54
  55 **/
  56 UINT8
  57 EFIAPI
  58 PciSegmentRead8 (
  59   IN UINT64                    Address
  60   )
  61 ;
  62
  63 /**
  64   Writes an 8-bit PCI configuration register.
  65
  66   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
  67   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
  68   If Address > 0x0FFFFFFF, then ASSERT().
  69
  70   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  71   @param  Value       The value to write.
  72
  73   @return The parameter of Value.
  74
  75 **/
  76 UINT8
  77 EFIAPI
  78 PciSegmentWrite8 (
  79   IN UINT64                    Address,
  80   IN UINT8                     Value
  81   )
  82 ;
  83
  84 /**
  85   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.
  86
  87   Reads the 8-bit PCI configuration register specified by Address,
  88   performs a bitwise inclusive OR between the read result and the value specified by OrData,
  89   and writes the result to the 8-bit PCI configuration register specified by Address.
  90   The value written to the PCI configuration register is returned.
  91   This function must guarantee that all PCI read and write operations are serialized.
  92   If any reserved bits in Address are set, then ASSERT().
  93
  94   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  95   @param  OrData    The value to OR with the PCI configuration register.
  96
  97   @return The value written to the PCI configuration register.
  98
  99 **/
 100 UINT8
 101 EFIAPI
 102 PciSegmentOr8 (
 103   IN UINT64                    Address,
 104   IN UINT8                     OrData
 105   )
 106 ;
 107
 108 /**
 109   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 110
 111   Reads the 8-bit PCI configuration register specified by Address,
 112   performs a bitwise AND between the read result and the value specified by AndData,
 113   and writes the result to the 8-bit PCI configuration register specified by Address.
 114   The value written to the PCI configuration register is returned.
 115   This function must guarantee that all PCI read and write operations are serialized.
 116   If any reserved bits in Address are set, then ASSERT().
 117
 118   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 119   @param  AndData   The value to AND with the PCI configuration register.
 120
 121   @return The value written to the PCI configuration register.
 122
 123 **/
 124 UINT8
 125 EFIAPI
 126 PciSegmentAnd8 (
 127   IN UINT64                    Address,
 128   IN UINT8                     AndData
 129   )
 130 ;
 131
 132 /**
 133   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 134   followed a  bitwise inclusive OR with another 8-bit value.
 135
 136   Reads the 8-bit PCI configuration register specified by Address,
 137   performs a bitwise AND between the read result and the value specified by AndData,
 138   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 139   and writes the result to the 8-bit PCI configuration register specified by Address.
 140   The value written to the PCI configuration register is returned.
 141   This function must guarantee that all PCI read and write operations are serialized.
 142   If any reserved bits in Address are set, then ASSERT().
 143
 144   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 145   @param  AndData    The value to AND with the PCI configuration register.
 146   @param  OrData    The value to OR with the PCI configuration register.
 147
 148   @return The value written to the PCI configuration register.
 149
 150 **/
 151 UINT8
 152 EFIAPI
 153 PciSegmentAndThenOr8 (
 154   IN UINT64                    Address,
 155   IN UINT8                     AndData,
 156   IN UINT8                     OrData
 157   )
 158 ;
 159
 160 /**
 161   Reads a bit field of a PCI configuration register.
 162
 163   Reads the bit field in an 8-bit PCI configuration register.
 164   The bit field is specified by the StartBit and the EndBit.
 165   The value of the bit field is returned.
 166   If any reserved bits in Address are set, then ASSERT().
 167   If StartBit is greater than 7, then ASSERT().
 168   If EndBit is greater than 7, then ASSERT().
 169   If EndBit is less than StartBit, then ASSERT().
 170
 171   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 172   @param  StartBit  The ordinal of the least significant bit in the bit field.
 173                     The ordinal of the least significant bit in a byte is bit 0.
 174   @param  EndBit    The ordinal of the most significant bit in the bit field.
 175                     The ordinal of the most significant bit in a byte is bit 7.
 176
 177   @return The value of the bit field.
 178
 179 **/
 180 UINT8
 181 EFIAPI
 182 PciSegmentBitFieldRead8 (
 183   IN UINT64                    Address,
 184   IN UINTN                     StartBit,
 185   IN UINTN                     EndBit
 186   )
 187 ;
 188
 189 /**
 190   Writes a bit field to a PCI configuration register.
 191
 192   Writes Value to the bit field of the PCI configuration register.
 193   The bit field is specified by the StartBit and the EndBit.
 194   All other bits in the destination PCI configuration register are preserved.
 195   The new value of the 8-bit register is returned.
 196   If any reserved bits in Address are set, then ASSERT().
 197   If StartBit is greater than 7, then ASSERT().
 198   If EndBit is greater than 7, then ASSERT().
 199   If EndBit is less than StartBit, then ASSERT().
 200
 201   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 202   @param  StartBit  The ordinal of the least significant bit in the bit field.
 203                     The ordinal of the least significant bit in a byte is bit 0.
 204   @param  EndBit    The ordinal of the most significant bit in the bit field.
 205                     The ordinal of the most significant bit in a byte is bit 7.
 206   @param  Value     New value of the bit field.
 207
 208   @return The new value of the 8-bit register.
 209
 210 **/
 211 UINT8
 212 EFIAPI
 213 PciSegmentBitFieldWrite8 (
 214   IN UINT64                    Address,
 215   IN UINTN                     StartBit,
 216   IN UINTN                     EndBit,
 217   IN UINT8                     Value
 218   )
 219 ;
 220
 221 /**
 222   Reads the 8-bit PCI configuration register specified by Address,
 223   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 224   and writes the result to the 8-bit PCI configuration register specified by Address.
 225
 226   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 227   @param  StartBit  The ordinal of the least significant bit in the bit field.
 228                     The ordinal of the least significant bit in a byte is bit 0.
 229   @param  EndBit    The ordinal of the most significant bit in the bit field.
 230                     The ordinal of the most significant bit in a byte is bit 7.
 231   @param  OrData    The value to OR with the read value from the PCI configuration register.
 232
 233   @return The value written to the PCI configuration register.
 234
 235 **/
 236 UINT8
 237 EFIAPI
 238 PciSegmentBitFieldOr8 (
 239   IN UINT64                    Address,
 240   IN UINTN                     StartBit,
 241   IN UINTN                     EndBit,
 242   IN UINT8                     OrData
 243   )
 244 ;
 245
 246 /**
 247   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,
 248   and writes the result back to the bit field in the 8-bit port.
 249
 250   Reads the 8-bit PCI configuration register specified by Address,
 251   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 252   and writes the result to the 8-bit PCI configuration register specified by Address.
 253   The value written to the PCI configuration register is returned.
 254   This function must guarantee that all PCI read and write operations are serialized.
 255   Extra left bits in OrData are stripped.
 256   If any reserved bits in Address are set, then ASSERT().
 257   If StartBit is greater than 7, then ASSERT().
 258   If EndBit is greater than 7, then ASSERT().
 259   If EndBit is less than StartBit, then ASSERT().
 260
 261   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 262   @param  StartBit  The ordinal of the least significant bit in the bit field.
 263                     The ordinal of the least significant bit in a byte is bit 0.
 264   @param  EndBit    The ordinal of the most significant bit in the bit field.
 265                     The ordinal of the most significant bit in a byte is bit 7.
 266   @param  AndData   The value to AND with the read value from the PCI configuration register.
 267
 268   @return The value written to the PCI configuration register.
 269
 270 **/
 271 UINT8
 272 EFIAPI
 273 PciSegmentBitFieldAnd8 (
 274   IN UINT64                    Address,
 275   IN UINTN                     StartBit,
 276   IN UINTN                     EndBit,
 277   IN UINT8                     AndData
 278   )
 279 ;
 280
 281 /**
 282   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,
 283   and writes the result back to the bit field in the 8-bit register.
 284
 285   Reads the 8-bit PCI configuration register specified by Address,
 286   performs a bitwise AND between the read result and the value specified by AndData,
 287   and writes the result to the 8-bit PCI configuration register specified by Address.
 288   The value written to the PCI configuration register is returned.
 289   This function must guarantee that all PCI read and write operations are serialized.
 290   Extra left bits in AndData are stripped.
 291   If any reserved bits in Address are set, then ASSERT().
 292   If StartBit is greater than 7, then ASSERT().
 293   If EndBit is greater than 7, then ASSERT().
 294   If EndBit is less than StartBit, then ASSERT().
 295
 296   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 297   @param  StartBit  The ordinal of the least significant bit in the bit field.
 298                     The ordinal of the least significant bit in a byte is bit 0.
 299   @param  EndBit    The ordinal of the most significant bit in the bit field.
 300                     The ordinal of the most significant bit in a byte is bit 7.
 301   @param  AndData   The value to AND with the read value from the PCI configuration register.
 302   @param  OrData    The value to OR with the read value from the PCI configuration register.
 303
 304   @return The value written to the PCI configuration register.
 305
 306 **/
 307 UINT8
 308 EFIAPI
 309 PciSegmentBitFieldAndThenOr8 (
 310   IN UINT64                    Address,
 311   IN UINTN                     StartBit,
 312   IN UINTN                     EndBit,
 313   IN UINT8                     AndData,
 314   IN UINT8                     OrData
 315   )
 316 ;
 317
 318 /**
 319   Reads a 16-bit PCI configuration register.
 320
 321   Reads and returns the 16-bit PCI configuration register specified by Address.
 322   This function must guarantee that all PCI read and write operations are serialized.
 323   If any reserved bits in Address are set, then ASSERT().
 324
 325   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 326
 327   @return The 16-bit PCI configuration register specified by Address.
 328
 329 **/
 330 UINT16
 331 EFIAPI
 332 PciSegmentRead16 (
 333   IN UINT64                    Address
 334   )
 335 ;
 336
 337 /**
 338   Writes a 16-bit PCI configuration register.
 339
 340   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 341   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 342   If Address > 0x0FFFFFFF, then ASSERT().
 343
 344   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 345   @param  Value       The value to write.
 346
 347   @return The parameter of Value.
 348
 349 **/
 350 UINT16
 351 EFIAPI
 352 PciSegmentWrite16 (
 353   IN UINT64                    Address,
 354   IN UINT16                    Value
 355   )
 356 ;
 357
 358 /**
 359   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.
 360
 361   Reads the 16-bit PCI configuration register specified by Address,
 362   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 363   and writes the result to the 16-bit PCI configuration register specified by Address.
 364   The value written to the PCI configuration register is returned.
 365   This function must guarantee that all PCI read and write operations are serialized.
 366   If any reserved bits in Address are set, then ASSERT().
 367
 368   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 369   @param  OrData    The value to OR with the PCI configuration register.
 370
 371   @return The value written to the PCI configuration register.
 372
 373 **/
 374 UINT16
 375 EFIAPI
 376 PciSegmentOr16 (
 377   IN UINT64                    Address,
 378   IN UINT16                    OrData
 379   )
 380 ;
 381
 382 /**
 383   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 384
 385   Reads the 16-bit PCI configuration register specified by Address,
 386   performs a bitwise AND between the read result and the value specified by AndData,
 387   and writes the result to the 16-bit PCI configuration register specified by Address.
 388   The value written to the PCI configuration register is returned.
 389   This function must guarantee that all PCI read and write operations are serialized.
 390   If any reserved bits in Address are set, then ASSERT().
 391
 392   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 393   @param  AndData   The value to AND with the PCI configuration register.
 394
 395   @return The value written to the PCI configuration register.
 396
 397 **/
 398 UINT16
 399 EFIAPI
 400 PciSegmentAnd16 (
 401   IN UINT64                    Address,
 402   IN UINT16                    AndData
 403   )
 404 ;
 405
 406 /**
 407   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 408   followed a  bitwise inclusive OR with another 16-bit value.
 409
 410   Reads the 16-bit PCI configuration register specified by Address,
 411   performs a bitwise AND between the read result and the value specified by AndData,
 412   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 413   and writes the result to the 16-bit PCI configuration register specified by Address.
 414   The value written to the PCI configuration register is returned.
 415   This function must guarantee that all PCI read and write operations are serialized.
 416   If any reserved bits in Address are set, then ASSERT().
 417
 418   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 419   @param  AndData    The value to AND with the PCI configuration register.
 420   @param  OrData    The value to OR with the PCI configuration register.
 421
 422   @return The value written to the PCI configuration register.
 423
 424 **/
 425 UINT16
 426 EFIAPI
 427 PciSegmentAndThenOr16 (
 428   IN UINT64                    Address,
 429   IN UINT16                    AndData,
 430   IN UINT16                    OrData
 431   )
 432 ;
 433
 434 /**
 435   Reads a bit field of a PCI configuration register.
 436
 437   Reads the bit field in a 16-bit PCI configuration register.
 438   The bit field is specified by the StartBit and the EndBit.
 439   The value of the bit field is returned.
 440   If any reserved bits in Address are set, then ASSERT().
 441   If StartBit is greater than 7, then ASSERT().
 442   If EndBit is greater than 7, then ASSERT().
 443   If EndBit is less than StartBit, then ASSERT().
 444
 445   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 446   @param  StartBit  The ordinal of the least significant bit in the bit field.
 447                     The ordinal of the least significant bit in a byte is bit 0.
 448   @param  EndBit    The ordinal of the most significant bit in the bit field.
 449                     The ordinal of the most significant bit in a byte is bit 7.
 450
 451   @return The value of the bit field.
 452
 453 **/
 454 UINT16
 455 EFIAPI
 456 PciSegmentBitFieldRead16 (
 457   IN UINT64                    Address,
 458   IN UINTN                     StartBit,
 459   IN UINTN                     EndBit
 460   )
 461 ;
 462
 463 /**
 464   Writes a bit field to a PCI configuration register.
 465
 466   Writes Value to the bit field of the PCI configuration register.
 467   The bit field is specified by the StartBit and the EndBit.
 468   All other bits in the destination PCI configuration register are preserved.
 469   The new value of the 16-bit register is returned.
 470   If any reserved bits in Address are set, then ASSERT().
 471   If StartBit is greater than 7, then ASSERT().
 472   If EndBit is greater than 7, then ASSERT().
 473   If EndBit is less than StartBit, then ASSERT().
 474
 475   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 476   @param  StartBit  The ordinal of the least significant bit in the bit field.
 477                     The ordinal of the least significant bit in a byte is bit 0.
 478   @param  EndBit    The ordinal of the most significant bit in the bit field.
 479                     The ordinal of the most significant bit in a byte is bit 7.
 480   @param  Value     New value of the bit field.
 481
 482   @return The new value of the 16-bit register.
 483
 484 **/
 485 UINT16
 486 EFIAPI
 487 PciSegmentBitFieldWrite16 (
 488   IN UINT64                    Address,
 489   IN UINTN                     StartBit,
 490   IN UINTN                     EndBit,
 491   IN UINT16                    Value
 492   )
 493 ;
 494
 495 /**
 496   Reads the 16-bit PCI configuration register specified by Address,
 497   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 498   and writes the result to the 16-bit PCI configuration register specified by Address.
 499
 500   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 501   @param  StartBit  The ordinal of the least significant bit in the bit field.
 502                     The ordinal of the least significant bit in a byte is bit 0.
 503   @param  EndBit    The ordinal of the most significant bit in the bit field.
 504                     The ordinal of the most significant bit in a byte is bit 7.
 505   @param  OrData    The value to OR with the read value from the PCI configuration register.
 506
 507   @return The value written to the PCI configuration register.
 508
 509 **/
 510 UINT16
 511 EFIAPI
 512 PciSegmentBitFieldOr16 (
 513   IN UINT64                    Address,
 514   IN UINTN                     StartBit,
 515   IN UINTN                     EndBit,
 516   IN UINT16                    OrData
 517   )
 518 ;
 519
 520 /**
 521   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
 522   and writes the result back to the bit field in the 16-bit port.
 523
 524   Reads the 16-bit PCI configuration register specified by Address,
 525   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 526   and writes the result to the 16-bit PCI configuration register specified by Address.
 527   The value written to the PCI configuration register is returned.
 528   This function must guarantee that all PCI read and write operations are serialized.
 529   Extra left bits in OrData are stripped.
 530   If any reserved bits in Address are set, then ASSERT().
 531   If StartBit is greater than 7, then ASSERT().
 532   If EndBit is greater than 7, then ASSERT().
 533   If EndBit is less than StartBit, then ASSERT().
 534
 535   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 536   @param  StartBit  The ordinal of the least significant bit in the bit field.
 537                     The ordinal of the least significant bit in a byte is bit 0.
 538   @param  EndBit    The ordinal of the most significant bit in the bit field.
 539                     The ordinal of the most significant bit in a byte is bit 7.
 540   @param  AndData   The value to AND with the read value from the PCI configuration register.
 541
 542   @return The value written to the PCI configuration register.
 543
 544 **/
 545 UINT16
 546 EFIAPI
 547 PciSegmentBitFieldAnd16 (
 548   IN UINT64                    Address,
 549   IN UINTN                     StartBit,
 550   IN UINTN                     EndBit,
 551   IN UINT16                    AndData
 552   )
 553 ;
 554
 555 /**
 556   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,
 557   and writes the result back to the bit field in the 16-bit register.
 558
 559   Reads the 16-bit PCI configuration register specified by Address,
 560   performs a bitwise AND between the read result and the value specified by AndData,
 561   and writes the result to the 16-bit PCI configuration register specified by Address.
 562   The value written to the PCI configuration register is returned.
 563   This function must guarantee that all PCI read and write operations are serialized.
 564   Extra left bits in AndData are stripped.
 565   If any reserved bits in Address are set, then ASSERT().
 566   If StartBit is greater than 7, then ASSERT().
 567   If EndBit is greater than 7, then ASSERT().
 568   If EndBit is less than StartBit, then ASSERT().
 569
 570   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 571   @param  StartBit  The ordinal of the least significant bit in the bit field.
 572                     The ordinal of the least significant bit in a byte is bit 0.
 573   @param  EndBit    The ordinal of the most significant bit in the bit field.
 574                     The ordinal of the most significant bit in a byte is bit 7.
 575   @param  AndData   The value to AND with the read value from the PCI configuration register.
 576   @param  OrData    The value to OR with the read value from the PCI configuration register.
 577
 578   @return The value written to the PCI configuration register.
 579
 580 **/
 581 UINT16
 582 EFIAPI
 583 PciSegmentBitFieldAndThenOr16 (
 584   IN UINT64                    Address,
 585   IN UINTN                     StartBit,
 586   IN UINTN                     EndBit,
 587   IN UINT16                    AndData,
 588   IN UINT16                    OrData
 589   )
 590 ;
 591
 592 /**
 593   Reads a 32-bit PCI configuration register.
 594
 595   Reads and returns the 32-bit PCI configuration register specified by Address.
 596   This function must guarantee that all PCI read and write operations are serialized.
 597   If any reserved bits in Address are set, then ASSERT().
 598
 599   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 600
 601   @return The 32-bit PCI configuration register specified by Address.
 602
 603 **/
 604 UINT32
 605 EFIAPI
 606 PciSegmentRead32 (
 607   IN UINT64                    Address
 608   )
 609 ;
 610
 611 /**
 612   Writes a 32-bit PCI configuration register.
 613
 614   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 615   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 616   If Address > 0x0FFFFFFF, then ASSERT().
 617
 618   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 619   @param  Value       The value to write.
 620
 621   @return The parameter of Value.
 622
 623 **/
 624 UINT32
 625 EFIAPI
 626 PciSegmentWrite32 (
 627   IN UINT64                    Address,
 628   IN UINT32                    Value
 629   )
 630 ;
 631
 632 /**
 633   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.
 634
 635   Reads the 32-bit PCI configuration register specified by Address,
 636   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 637   and writes the result to the 32-bit PCI configuration register specified by Address.
 638   The value written to the PCI configuration register is returned.
 639   This function must guarantee that all PCI read and write operations are serialized.
 640   If any reserved bits in Address are set, then ASSERT().
 641
 642   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 643   @param  OrData    The value to OR with the PCI configuration register.
 644
 645   @return The value written to the PCI configuration register.
 646
 647 **/
 648 UINT32
 649 EFIAPI
 650 PciSegmentOr32 (
 651   IN UINT64                    Address,
 652   IN UINT32                    OrData
 653   )
 654 ;
 655
 656 /**
 657   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 658
 659   Reads the 32-bit PCI configuration register specified by Address,
 660   performs a bitwise AND between the read result and the value specified by AndData,
 661   and writes the result to the 32-bit PCI configuration register specified by Address.
 662   The value written to the PCI configuration register is returned.
 663   This function must guarantee that all PCI read and write operations are serialized.
 664   If any reserved bits in Address are set, then ASSERT().
 665
 666   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 667   @param  AndData   The value to AND with the PCI configuration register.
 668
 669   @return The value written to the PCI configuration register.
 670
 671 **/
 672 UINT32
 673 EFIAPI
 674 PciSegmentAnd32 (
 675   IN UINT64                    Address,
 676   IN UINT32                    AndData
 677   )
 678 ;
 679
 680 /**
 681   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 682   followed a  bitwise inclusive OR with another 32-bit value.
 683
 684   Reads the 32-bit PCI configuration register specified by Address,
 685   performs a bitwise AND between the read result and the value specified by AndData,
 686   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 687   and writes the result to the 32-bit PCI configuration register specified by Address.
 688   The value written to the PCI configuration register is returned.
 689   This function must guarantee that all PCI read and write operations are serialized.
 690   If any reserved bits in Address are set, then ASSERT().
 691
 692   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 693   @param  AndData   The value to AND with the PCI configuration register.
 694   @param  OrData    The value to OR with the PCI configuration register.
 695
 696   @return The value written to the PCI configuration register.
 697
 698 **/
 699 UINT32
 700 EFIAPI
 701 PciSegmentAndThenOr32 (
 702   IN UINT64                    Address,
 703   IN UINT32                    AndData,
 704   IN UINT32                    OrData
 705   )
 706 ;
 707
 708 /**
 709   Reads a bit field of a PCI configuration register.
 710
 711   Reads the bit field in a 32-bit PCI configuration register.
 712   The bit field is specified by the StartBit and the EndBit.
 713   The value of the bit field is returned.
 714   If any reserved bits in Address are set, then ASSERT().
 715   If StartBit is greater than 7, then ASSERT().
 716   If EndBit is greater than 7, then ASSERT().
 717   If EndBit is less than StartBit, then ASSERT().
 718
 719   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 720   @param  StartBit  The ordinal of the least significant bit in the bit field.
 721                     The ordinal of the least significant bit in a byte is bit 0.
 722   @param  EndBit    The ordinal of the most significant bit in the bit field.
 723                     The ordinal of the most significant bit in a byte is bit 7.
 724
 725   @return The value of the bit field.
 726
 727 **/
 728 UINT32
 729 EFIAPI
 730 PciSegmentBitFieldRead32 (
 731   IN UINT64                    Address,
 732   IN UINTN                     StartBit,
 733   IN UINTN                     EndBit
 734   )
 735 ;
 736
 737 /**
 738   Writes a bit field to a PCI configuration register.
 739
 740   Writes Value to the bit field of the PCI configuration register.
 741   The bit field is specified by the StartBit and the EndBit.
 742   All other bits in the destination PCI configuration register are preserved.
 743   The new value of the 32-bit register is returned.
 744   If any reserved bits in Address are set, then ASSERT().
 745   If StartBit is greater than 7, then ASSERT().
 746   If EndBit is greater than 7, then ASSERT().
 747   If EndBit is less than StartBit, then ASSERT().
 748
 749   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 750   @param  StartBit  The ordinal of the least significant bit in the bit field.
 751                     The ordinal of the least significant bit in a byte is bit 0.
 752   @param  EndBit    The ordinal of the most significant bit in the bit field.
 753                     The ordinal of the most significant bit in a byte is bit 7.
 754   @param  Value     New value of the bit field.
 755
 756   @return The new value of the 32-bit register.
 757
 758 **/
 759 UINT32
 760 EFIAPI
 761 PciSegmentBitFieldWrite32 (
 762   IN UINT64                    Address,
 763   IN UINTN                     StartBit,
 764   IN UINTN                     EndBit,
 765   IN UINT32                    Value
 766   )
 767 ;
 768
 769 /**
 770   Reads the 32-bit PCI configuration register specified by Address,
 771   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 772   and writes the result to the 32-bit PCI configuration register specified by Address.
 773
 774   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 775   @param  StartBit  The ordinal of the least significant bit in the bit field.
 776                     The ordinal of the least significant bit in a byte is bit 0.
 777   @param  EndBit    The ordinal of the most significant bit in the bit field.
 778                     The ordinal of the most significant bit in a byte is bit 7.
 779   @param  OrData    The value to OR with the read value from the PCI configuration register.
 780
 781   @return The value written to the PCI configuration register.
 782
 783 **/
 784 UINT32
 785 EFIAPI
 786 PciSegmentBitFieldOr32 (
 787   IN UINT64                    Address,
 788   IN UINTN                     StartBit,
 789   IN UINTN                     EndBit,
 790   IN UINT32                    OrData
 791   )
 792 ;
 793
 794 /**
 795   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,
 796   and writes the result back to the bit field in the 32-bit port.
 797
 798   Reads the 32-bit PCI configuration register specified by Address,
 799   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 800   and writes the result to the 32-bit PCI configuration register specified by Address.
 801   The value written to the PCI configuration register is returned.
 802   This function must guarantee that all PCI read and write operations are serialized.
 803   Extra left bits in OrData are stripped.
 804   If any reserved bits in Address are set, then ASSERT().
 805   If StartBit is greater than 7, then ASSERT().
 806   If EndBit is greater than 7, then ASSERT().
 807   If EndBit is less than StartBit, then ASSERT().
 808
 809   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 810   @param  StartBit  The ordinal of the least significant bit in the bit field.
 811                     The ordinal of the least significant bit in a byte is bit 0.
 812   @param  EndBit    The ordinal of the most significant bit in the bit field.
 813                     The ordinal of the most significant bit in a byte is bit 7.
 814   @param  AndData   The value to AND with the read value from the PCI configuration register.
 815
 816   @return The value written to the PCI configuration register.
 817
 818 **/
 819 UINT32
 820 EFIAPI
 821 PciSegmentBitFieldAnd32 (
 822   IN UINT64                    Address,
 823   IN UINTN                     StartBit,
 824   IN UINTN                     EndBit,
 825   IN UINT32                    AndData
 826   )
 827 ;
 828
 829 /**
 830   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,
 831   and writes the result back to the bit field in the 32-bit register.
 832
 833   Reads the 32-bit PCI configuration register specified by Address,
 834   performs a bitwise AND between the read result and the value specified by AndData,
 835   and writes the result to the 32-bit PCI configuration register specified by Address.
 836   The value written to the PCI configuration register is returned.
 837   This function must guarantee that all PCI read and write operations are serialized.
 838   Extra left bits in AndData are stripped.
 839   If any reserved bits in Address are set, then ASSERT().
 840   If StartBit is greater than 7, then ASSERT().
 841   If EndBit is greater than 7, then ASSERT().
 842   If EndBit is less than StartBit, then ASSERT().
 843
 844   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 845   @param  StartBit  The ordinal of the least significant bit in the bit field.
 846                     The ordinal of the least significant bit in a byte is bit 0.
 847   @param  EndBit    The ordinal of the most significant bit in the bit field.
 848                     The ordinal of the most significant bit in a byte is bit 7.
 849   @param  AndData   The value to AND with the read value from the PCI configuration register.
 850   @param  OrData    The value to OR with the read value from the PCI configuration register.
 851
 852   @return The value written to the PCI configuration register.
 853
 854 **/
 855 UINT32
 856 EFIAPI
 857 PciSegmentBitFieldAndThenOr32 (
 858   IN UINT64                    Address,
 859   IN UINTN                     StartBit,
 860   IN UINTN                     EndBit,
 861   IN UINT32                    AndData,
 862   IN UINT32                    OrData
 863   )
 864 ;
 865
 866 /**
 867   Reads a range of PCI configuration registers into a caller supplied buffer.
 868
 869   Reads the range of PCI configuration registers specified by StartAddress
 870   and Size into the buffer specified by Buffer.
 871   This function only allows the PCI configuration registers from a single PCI function to be read.
 872   Size is returned.
 873   If any reserved bits in StartAddress are set, then ASSERT().
 874   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 875   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
 876   If Buffer is NULL, then ASSERT().
 877
 878   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
 879   @param  Size          Size in bytes of the transfer.
 880   @param  Buffer        Pointer to a buffer receiving the data read.
 881
 882   @return The paramter of Size.
 883
 884 **/
 885 UINTN
 886 EFIAPI
 887 PciSegmentReadBuffer (
 888   IN  UINT64                   StartAddress,
 889   IN  UINTN                    Size,
 890   OUT VOID                     *Buffer
 891   )
 892 ;
 893
 894 /**
 895   Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
 896
 897   Writes the range of PCI configuration registers specified by StartAddress
 898   and Size from the buffer specified by Buffer.
 899   This function only allows the PCI configuration registers from a single PCI function to be written.
 900   Size is returned.
 901   If any reserved bits in StartAddress are set, then ASSERT().
 902   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 903   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
 904   If Buffer is NULL, then ASSERT().
 905
 906   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
 907   @param  Size          Size in bytes of the transfer.
 908   @param  Buffer        Pointer to a buffer containing the data to write.
 909
 910   @return The paramter of Size.
 911
 912 **/
 913 UINTN
 914 EFIAPI
 915 PciSegmentWriteBuffer (
 916   IN UINT64                    StartAddress,
 917   IN UINTN                     Size,
 918   IN VOID                      *Buffer
 919   )
 920 ;
 921
 922 #endif