MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
   3
   4   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
   5   registers on PCI root bridges on any supported PCI segment.  These library services take a single
   6   address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   7   The layout of this address parameter is as follows:
   8
   9             PCI Register: Bits 0..11
  10             PCI Function  Bits 12..14
  11             PCI Device  Bits 15..19
  12             PCI Bus Bits 20..27
  13             Reserved  Bits 28..31.  Must be 0.
  14             PCI Segment Bits 32..47
  15             Reserved  Bits 48..63.  Must be 0.
  16
  17   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
  18   63             48  47    32  31           28 27         20 19    15 14      12 11         0
  19
  20   These functions perform PCI configuration cycles using the default PCI configuration access
  21   method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
  22   may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
  23   access method.  Modules will typically use the PCI Segment Library for its PCI configuration
  24   accesses when PCI Segments other than Segment #0 must be accessed.
  25
  26 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
  27 This program and the accompanying materials
  28 are licensed and made available under the terms and conditions of the BSD License
  29 which accompanies this distribution.  The full text of the license may be found at
  30 http://opensource.org/licenses/bsd-license.php
  31
  32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  34
  35 **/
  36
  37 #ifndef __PCI_SEGMENT_LIB__
  38 #define __PCI_SEGMENT_LIB__
  39
  40
  41 /**
  42   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  43   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  44
  45   Computes an address that is compatible with the PCI Segment Library functions.
  46   The unused upper bits of Segment, Bus, Device, Function,
  47   and Register are stripped prior to the generation of the address.
  48
  49   @param  Segment   PCI Segment number.  Range 0..65535.
  50   @param  Bus       PCI Bus number.  Range 0..255.
  51   @param  Device    PCI Device number.  Range 0..31.
  52   @param  Function  PCI Function number.  Range 0..7.
  53   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  54
  55   @return The address that is compatible with the PCI Segment Library functions.
  56
  57 **/
  58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
  59   ((Segment != 0) ? \
  60     ( ((Register) & 0xfff)                 | \
  61       (((Function) & 0x07) << 12)          | \
  62       (((Device) & 0x1f) << 15)            | \
  63       (((Bus) & 0xff) << 20)               | \
  64       (LShiftU64 ((Segment) & 0xffff, 32))   \
  65     ) :                                      \
  66     ( ((Register) & 0xfff)                 | \
  67       (((Function) & 0x07) << 12)          | \
  68       (((Device) & 0x1f) << 15)            | \
  69       (((Bus) & 0xff) << 20)                 \
  70     )                                        \
  71   )
  72
  73 /**
  74   Register a PCI device so PCI configuration registers may be accessed after
  75   SetVirtualAddressMap().
  76
  77   If any reserved bits in Address are set, then ASSERT().
  78
  79   @param  Address Address that encodes the PCI Bus, Device, Function and
  80                   Register.
  81
  82   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  83   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  84                                    after ExitBootServices().
  85   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  86                                    at runtime could not be mapped.
  87   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  88                                    complete the registration.
  89
  90 **/
  91 RETURN_STATUS
  92 EFIAPI
  93 PciSegmentRegisterForRuntimeAccess (
  94   IN UINTN  Address
  95   );
  96
  97 /**
  98   Reads an 8-bit PCI configuration register.
  99
 100   Reads and returns the 8-bit PCI configuration register specified by Address.
 101   This function must guarantee that all PCI read and write operations are serialized.
 102
 103   If any reserved bits in Address are set, then ASSERT().
 104
 105   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 106
 107   @return The 8-bit PCI configuration register specified by Address.
 108
 109 **/
 110 UINT8
 111 EFIAPI
 112 PciSegmentRead8 (
 113   IN UINT64                    Address
 114   );
 115
 116 /**
 117   Writes an 8-bit PCI configuration register.
 118
 119   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
 120   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 121
 122   If any reserved bits in Address are set, then ASSERT().
 123
 124   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 125   @param  Value       The value to write.
 126
 127   @return The value written to the PCI configuration register.
 128
 129 **/
 130 UINT8
 131 EFIAPI
 132 PciSegmentWrite8 (
 133   IN UINT64                    Address,
 134   IN UINT8                     Value
 135   );
 136
 137 /**
 138   Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
 139
 140   Reads the 8-bit PCI configuration register specified by Address,
 141   performs a bitwise OR between the read result and the value specified by OrData,
 142   and writes the result to the 8-bit PCI configuration register specified by Address.
 143   The value written to the PCI configuration register is returned.
 144   This function must guarantee that all PCI read and write operations are serialized.
 145
 146   If any reserved bits in Address are set, then ASSERT().
 147
 148   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 149   @param  OrData    The value to OR with the PCI configuration register.
 150
 151   @return The value written to the PCI configuration register.
 152
 153 **/
 154 UINT8
 155 EFIAPI
 156 PciSegmentOr8 (
 157   IN UINT64                    Address,
 158   IN UINT8                     OrData
 159   );
 160
 161 /**
 162   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 163
 164   Reads the 8-bit PCI configuration register specified by Address,
 165   performs a bitwise AND between the read result and the value specified by AndData,
 166   and writes the result to the 8-bit PCI configuration register specified by Address.
 167   The value written to the PCI configuration register is returned.
 168   This function must guarantee that all PCI read and write operations are serialized.
 169   If any reserved bits in Address are set, then ASSERT().
 170
 171   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 172   @param  AndData   The value to AND with the PCI configuration register.
 173
 174   @return The value written to the PCI configuration register.
 175
 176 **/
 177 UINT8
 178 EFIAPI
 179 PciSegmentAnd8 (
 180   IN UINT64                    Address,
 181   IN UINT8                     AndData
 182   );
 183
 184 /**
 185   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 186   followed a  bitwise OR with another 8-bit value.
 187
 188   Reads the 8-bit PCI configuration register specified by Address,
 189   performs a bitwise AND between the read result and the value specified by AndData,
 190   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 191   and writes the result to the 8-bit PCI configuration register specified by Address.
 192   The value written to the PCI configuration register is returned.
 193   This function must guarantee that all PCI read and write operations are serialized.
 194
 195   If any reserved bits in Address are set, then ASSERT().
 196
 197   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 198   @param  AndData   The value to AND with the PCI configuration register.
 199   @param  OrData    The value to OR with the PCI configuration register.
 200
 201   @return The value written to the PCI configuration register.
 202
 203 **/
 204 UINT8
 205 EFIAPI
 206 PciSegmentAndThenOr8 (
 207   IN UINT64                    Address,
 208   IN UINT8                     AndData,
 209   IN UINT8                     OrData
 210   );
 211
 212 /**
 213   Reads a bit field of a PCI configuration register.
 214
 215   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 216   specified by the StartBit and the EndBit. The value of the bit field is
 217   returned.
 218
 219   If any reserved bits in Address are set, then ASSERT().
 220   If StartBit is greater than 7, then ASSERT().
 221   If EndBit is greater than 7, then ASSERT().
 222   If EndBit is less than StartBit, then ASSERT().
 223
 224   @param  Address   PCI configuration register to read.
 225   @param  StartBit  The ordinal of the least significant bit in the bit field.
 226                     Range 0..7.
 227   @param  EndBit    The ordinal of the most significant bit in the bit field.
 228                     Range 0..7.
 229
 230   @return The value of the bit field read from the PCI configuration register.
 231
 232 **/
 233 UINT8
 234 EFIAPI
 235 PciSegmentBitFieldRead8 (
 236   IN UINT64                    Address,
 237   IN UINTN                     StartBit,
 238   IN UINTN                     EndBit
 239   );
 240
 241 /**
 242   Writes a bit field to a PCI configuration register.
 243
 244   Writes Value to the bit field of the PCI configuration register. The bit
 245   field is specified by the StartBit and the EndBit. All other bits in the
 246   destination PCI configuration register are preserved. The new value of the
 247   8-bit register is returned.
 248
 249   If any reserved bits in Address are set, then ASSERT().
 250   If StartBit is greater than 7, then ASSERT().
 251   If EndBit is greater than 7, then ASSERT().
 252   If EndBit is less than StartBit, then ASSERT().
 253   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 254
 255   @param  Address   PCI configuration register to write.
 256   @param  StartBit  The ordinal of the least significant bit in the bit field.
 257                     Range 0..7.
 258   @param  EndBit    The ordinal of the most significant bit in the bit field.
 259                     Range 0..7.
 260   @param  Value     New value of the bit field.
 261
 262   @return The value written back to the PCI configuration register.
 263
 264 **/
 265 UINT8
 266 EFIAPI
 267 PciSegmentBitFieldWrite8 (
 268   IN UINT64                    Address,
 269   IN UINTN                     StartBit,
 270   IN UINTN                     EndBit,
 271   IN UINT8                     Value
 272   );
 273
 274 /**
 275   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 276   writes the result back to the bit field in the 8-bit port.
 277
 278   Reads the 8-bit PCI configuration register specified by Address, performs a
 279   bitwise OR between the read result and the value specified by
 280   OrData, and writes the result to the 8-bit PCI configuration register
 281   specified by Address. The value written to the PCI configuration register is
 282   returned. This function must guarantee that all PCI read and write operations
 283   are serialized. Extra left bits in OrData are stripped.
 284
 285   If any reserved bits in Address are set, then ASSERT().
 286   If StartBit is greater than 7, then ASSERT().
 287   If EndBit is greater than 7, then ASSERT().
 288   If EndBit is less than StartBit, then ASSERT().
 289   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 290
 291   @param  Address   PCI configuration register to write.
 292   @param  StartBit  The ordinal of the least significant bit in the bit field.
 293                     Range 0..7.
 294   @param  EndBit    The ordinal of the most significant bit in the bit field.
 295                     Range 0..7.
 296   @param  OrData    The value to OR with the PCI configuration register.
 297
 298   @return The value written back to the PCI configuration register.
 299
 300 **/
 301 UINT8
 302 EFIAPI
 303 PciSegmentBitFieldOr8 (
 304   IN UINT64                    Address,
 305   IN UINTN                     StartBit,
 306   IN UINTN                     EndBit,
 307   IN UINT8                     OrData
 308   );
 309
 310 /**
 311   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 312   AND, and writes the result back to the bit field in the 8-bit register.
 313
 314   Reads the 8-bit PCI configuration register specified by Address, performs a
 315   bitwise AND between the read result and the value specified by AndData, and
 316   writes the result to the 8-bit PCI configuration register specified by
 317   Address. The value written to the PCI configuration register is returned.
 318   This function must guarantee that all PCI read and write operations are
 319   serialized. Extra left bits in AndData are stripped.
 320
 321   If any reserved bits in Address are set, then ASSERT().
 322   If StartBit is greater than 7, then ASSERT().
 323   If EndBit is greater than 7, then ASSERT().
 324   If EndBit is less than StartBit, then ASSERT().
 325   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 326
 327   @param  Address   PCI configuration register to write.
 328   @param  StartBit  The ordinal of the least significant bit in the bit field.
 329                     Range 0..7.
 330   @param  EndBit    The ordinal of the most significant bit in the bit field.
 331                     Range 0..7.
 332   @param  AndData   The value to AND with the PCI configuration register.
 333
 334   @return The value written back to the PCI configuration register.
 335
 336 **/
 337 UINT8
 338 EFIAPI
 339 PciSegmentBitFieldAnd8 (
 340   IN UINT64                    Address,
 341   IN UINTN                     StartBit,
 342   IN UINTN                     EndBit,
 343   IN UINT8                     AndData
 344   );
 345
 346 /**
 347   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 348   bitwise OR, and writes the result back to the bit field in the 8-bit port.
 349
 350   Reads the 8-bit PCI configuration register specified by Address, performs a
 351   bitwise AND followed by a bitwise OR between the read result and
 352   the value specified by AndData, and writes the result to the 8-bit PCI
 353   configuration register specified by Address. The value written to the PCI
 354   configuration register is returned. This function must guarantee that all PCI
 355   read and write operations are serialized. Extra left bits in both AndData and
 356   OrData are stripped.
 357
 358   If any reserved bits in Address are set, then ASSERT().
 359   If StartBit is greater than 7, then ASSERT().
 360   If EndBit is greater than 7, then ASSERT().
 361   If EndBit is less than StartBit, then ASSERT().
 362   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 363   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 364
 365   @param  Address   PCI configuration register to write.
 366   @param  StartBit  The ordinal of the least significant bit in the bit field.
 367                     Range 0..7.
 368   @param  EndBit    The ordinal of the most significant bit in the bit field.
 369                     Range 0..7.
 370   @param  AndData   The value to AND with the PCI configuration register.
 371   @param  OrData    The value to OR with the result of the AND operation.
 372
 373   @return The value written back to the PCI configuration register.
 374
 375 **/
 376 UINT8
 377 EFIAPI
 378 PciSegmentBitFieldAndThenOr8 (
 379   IN UINT64                    Address,
 380   IN UINTN                     StartBit,
 381   IN UINTN                     EndBit,
 382   IN UINT8                     AndData,
 383   IN UINT8                     OrData
 384   );
 385
 386 /**
 387   Reads a 16-bit PCI configuration register.
 388
 389   Reads and returns the 16-bit PCI configuration register specified by Address.
 390   This function must guarantee that all PCI read and write operations are serialized.
 391
 392   If any reserved bits in Address are set, then ASSERT().
 393   If Address is not aligned on a 16-bit boundary, then ASSERT().
 394
 395   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 396
 397   @return The 16-bit PCI configuration register specified by Address.
 398
 399 **/
 400 UINT16
 401 EFIAPI
 402 PciSegmentRead16 (
 403   IN UINT64                    Address
 404   );
 405
 406 /**
 407   Writes a 16-bit PCI configuration register.
 408
 409   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 410   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 411
 412   If any reserved bits in Address are set, then ASSERT().
 413   If Address is not aligned on a 16-bit boundary, then ASSERT().
 414
 415   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 416   @param  Value       The value to write.
 417
 418   @return The parameter of Value.
 419
 420 **/
 421 UINT16
 422 EFIAPI
 423 PciSegmentWrite16 (
 424   IN UINT64                    Address,
 425   IN UINT16                    Value
 426   );
 427
 428 /**
 429   Performs a bitwise OR of a 16-bit PCI configuration register with
 430   a 16-bit value.
 431
 432   Reads the 16-bit PCI configuration register specified by Address, performs a
 433   bitwise OR between the read result and the value specified by OrData, and
 434   writes the result to the 16-bit PCI configuration register specified by Address.
 435   The value written to the PCI configuration register is returned. This function
 436   must guarantee that all PCI read and write operations are serialized.
 437
 438   If any reserved bits in Address are set, then ASSERT().
 439   If Address is not aligned on a 16-bit boundary, then ASSERT().
 440
 441   @param  Address Address that encodes the PCI Segment, Bus, Device, Function and
 442                   Register.
 443   @param  OrData  The value to OR with the PCI configuration register.
 444
 445   @return The value written back to the PCI configuration register.
 446
 447 **/
 448 UINT16
 449 EFIAPI
 450 PciSegmentOr16 (
 451   IN UINT64                    Address,
 452   IN UINT16                    OrData
 453   );
 454
 455 /**
 456   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 457
 458   Reads the 16-bit PCI configuration register specified by Address,
 459   performs a bitwise AND between the read result and the value specified by AndData,
 460   and writes the result to the 16-bit PCI configuration register specified by Address.
 461   The value written to the PCI configuration register is returned.
 462   This function must guarantee that all PCI read and write operations are serialized.
 463
 464   If any reserved bits in Address are set, then ASSERT().
 465   If Address is not aligned on a 16-bit boundary, then ASSERT().
 466
 467   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 468   @param  AndData   The value to AND with the PCI configuration register.
 469
 470   @return The value written to the PCI configuration register.
 471
 472 **/
 473 UINT16
 474 EFIAPI
 475 PciSegmentAnd16 (
 476   IN UINT64                    Address,
 477   IN UINT16                    AndData
 478   );
 479
 480 /**
 481   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 482   followed a  bitwise OR with another 16-bit value.
 483
 484   Reads the 16-bit PCI configuration register specified by Address,
 485   performs a bitwise AND between the read result and the value specified by AndData,
 486   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 487   and writes the result to the 16-bit PCI configuration register specified by Address.
 488   The value written to the PCI configuration register is returned.
 489   This function must guarantee that all PCI read and write operations are serialized.
 490
 491   If any reserved bits in Address are set, then ASSERT().
 492   If Address is not aligned on a 16-bit boundary, then ASSERT().
 493
 494   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 495   @param  AndData   The value to AND with the PCI configuration register.
 496   @param  OrData    The value to OR with the PCI configuration register.
 497
 498   @return The value written to the PCI configuration register.
 499
 500 **/
 501 UINT16
 502 EFIAPI
 503 PciSegmentAndThenOr16 (
 504   IN UINT64                    Address,
 505   IN UINT16                    AndData,
 506   IN UINT16                    OrData
 507   );
 508
 509 /**
 510   Reads a bit field of a PCI configuration register.
 511
 512   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 513   specified by the StartBit and the EndBit. The value of the bit field is
 514   returned.
 515
 516   If any reserved bits in Address are set, then ASSERT().
 517   If Address is not aligned on a 16-bit boundary, then ASSERT().
 518   If StartBit is greater than 15, then ASSERT().
 519   If EndBit is greater than 15, then ASSERT().
 520   If EndBit is less than StartBit, then ASSERT().
 521
 522   @param  Address   PCI configuration register to read.
 523   @param  StartBit  The ordinal of the least significant bit in the bit field.
 524                     Range 0..15.
 525   @param  EndBit    The ordinal of the most significant bit in the bit field.
 526                     Range 0..15.
 527
 528   @return The value of the bit field read from the PCI configuration register.
 529
 530 **/
 531 UINT16
 532 EFIAPI
 533 PciSegmentBitFieldRead16 (
 534   IN UINT64                    Address,
 535   IN UINTN                     StartBit,
 536   IN UINTN                     EndBit
 537   );
 538
 539 /**
 540   Writes a bit field to a PCI configuration register.
 541
 542   Writes Value to the bit field of the PCI configuration register. The bit
 543   field is specified by the StartBit and the EndBit. All other bits in the
 544   destination PCI configuration register are preserved. The new value of the
 545   16-bit register is returned.
 546
 547   If any reserved bits in Address are set, then ASSERT().
 548   If Address is not aligned on a 16-bit boundary, then ASSERT().
 549   If StartBit is greater than 15, then ASSERT().
 550   If EndBit is greater than 15, then ASSERT().
 551   If EndBit is less than StartBit, then ASSERT().
 552   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 553
 554   @param  Address   PCI configuration register to write.
 555   @param  StartBit  The ordinal of the least significant bit in the bit field.
 556                     Range 0..15.
 557   @param  EndBit    The ordinal of the most significant bit in the bit field.
 558                     Range 0..15.
 559   @param  Value     New value of the bit field.
 560
 561   @return The value written back to the PCI configuration register.
 562
 563 **/
 564 UINT16
 565 EFIAPI
 566 PciSegmentBitFieldWrite16 (
 567   IN UINT64                    Address,
 568   IN UINTN                     StartBit,
 569   IN UINTN                     EndBit,
 570   IN UINT16                    Value
 571   );
 572
 573 /**
 574   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
 575   the result back to the bit field in the 16-bit port.
 576
 577   Reads the 16-bit PCI configuration register specified by Address, performs a
 578   bitwise OR between the read result and the value specified by
 579   OrData, and writes the result to the 16-bit PCI configuration register
 580   specified by Address. The value written to the PCI configuration register is
 581   returned. This function must guarantee that all PCI read and write operations
 582   are serialized. Extra left bits in OrData are stripped.
 583
 584   If any reserved bits in Address are set, then ASSERT().
 585   If Address is not aligned on a 16-bit boundary, then ASSERT().
 586   If StartBit is greater than 15, then ASSERT().
 587   If EndBit is greater than 15, then ASSERT().
 588   If EndBit is less than StartBit, then ASSERT().
 589   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 590
 591   @param  Address   PCI configuration register to write.
 592   @param  StartBit  The ordinal of the least significant bit in the bit field.
 593                     Range 0..15.
 594   @param  EndBit    The ordinal of the most significant bit in the bit field.
 595                     Range 0..15.
 596   @param  OrData    The value to OR with the PCI configuration register.
 597
 598   @return The value written back to the PCI configuration register.
 599
 600 **/
 601 UINT16
 602 EFIAPI
 603 PciSegmentBitFieldOr16 (
 604   IN UINT64                    Address,
 605   IN UINTN                     StartBit,
 606   IN UINTN                     EndBit,
 607   IN UINT16                    OrData
 608   );
 609
 610 /**
 611   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 612   AND, writes the result back to the bit field in the 16-bit register.
 613
 614   Reads the 16-bit PCI configuration register specified by Address, performs a
 615   bitwise AND between the read result and the value specified by AndData, and
 616   writes the result to the 16-bit PCI configuration register specified by
 617   Address. The value written to the PCI configuration register is returned.
 618   This function must guarantee that all PCI read and write operations are
 619   serialized. Extra left bits in AndData are stripped.
 620
 621   If any reserved bits in Address are set, then ASSERT().
 622   If Address is not aligned on a 16-bit boundary, then ASSERT().
 623   If StartBit is greater than 15, then ASSERT().
 624   If EndBit is greater than 15, then ASSERT().
 625   If EndBit is less than StartBit, then ASSERT().
 626   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 627
 628   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 629   @param  StartBit  The ordinal of the least significant bit in the bit field.
 630                     Range 0..15.
 631   @param  EndBit    The ordinal of the most significant bit in the bit field.
 632                     Range 0..15.
 633   @param  AndData   The value to AND with the PCI configuration register.
 634
 635   @return The value written back to the PCI configuration register.
 636
 637 **/
 638 UINT16
 639 EFIAPI
 640 PciSegmentBitFieldAnd16 (
 641   IN UINT64                    Address,
 642   IN UINTN                     StartBit,
 643   IN UINTN                     EndBit,
 644   IN UINT16                    AndData
 645   );
 646
 647 /**
 648   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 649   bitwise OR, and writes the result back to the bit field in the
 650   16-bit port.
 651
 652   Reads the 16-bit PCI configuration register specified by Address, performs a
 653   bitwise AND followed by a bitwise OR between the read result and
 654   the value specified by AndData, and writes the result to the 16-bit PCI
 655   configuration register specified by Address. The value written to the PCI
 656   configuration register is returned. This function must guarantee that all PCI
 657   read and write operations are serialized. Extra left bits in both AndData and
 658   OrData are stripped.
 659
 660   If any reserved bits in Address are set, then ASSERT().
 661   If StartBit is greater than 15, then ASSERT().
 662   If EndBit is greater than 15, then ASSERT().
 663   If EndBit is less than StartBit, then ASSERT().
 664   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 665   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 666
 667   @param  Address   PCI configuration register to write.
 668   @param  StartBit  The ordinal of the least significant bit in the bit field.
 669                     Range 0..15.
 670   @param  EndBit    The ordinal of the most significant bit in the bit field.
 671                     Range 0..15.
 672   @param  AndData   The value to AND with the PCI configuration register.
 673   @param  OrData    The value to OR with the result of the AND operation.
 674
 675   @return The value written back to the PCI configuration register.
 676
 677 **/
 678 UINT16
 679 EFIAPI
 680 PciSegmentBitFieldAndThenOr16 (
 681   IN UINT64                    Address,
 682   IN UINTN                     StartBit,
 683   IN UINTN                     EndBit,
 684   IN UINT16                    AndData,
 685   IN UINT16                    OrData
 686   );
 687
 688 /**
 689   Reads a 32-bit PCI configuration register.
 690
 691   Reads and returns the 32-bit PCI configuration register specified by Address.
 692   This function must guarantee that all PCI read and write operations are serialized.
 693
 694   If any reserved bits in Address are set, then ASSERT().
 695   If Address is not aligned on a 32-bit boundary, then ASSERT().
 696
 697   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 698
 699   @return The 32-bit PCI configuration register specified by Address.
 700
 701 **/
 702 UINT32
 703 EFIAPI
 704 PciSegmentRead32 (
 705   IN UINT64                    Address
 706   );
 707
 708 /**
 709   Writes a 32-bit PCI configuration register.
 710
 711   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 712   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 713
 714   If any reserved bits in Address are set, then ASSERT().
 715   If Address is not aligned on a 32-bit boundary, then ASSERT().
 716
 717   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 718   @param  Value       The value to write.
 719
 720   @return The parameter of Value.
 721
 722 **/
 723 UINT32
 724 EFIAPI
 725 PciSegmentWrite32 (
 726   IN UINT64                    Address,
 727   IN UINT32                    Value
 728   );
 729
 730 /**
 731   Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
 732
 733   Reads the 32-bit PCI configuration register specified by Address,
 734   performs a bitwise OR between the read result and the value specified by OrData,
 735   and writes the result to the 32-bit PCI configuration register specified by Address.
 736   The value written to the PCI configuration register is returned.
 737   This function must guarantee that all PCI read and write operations are serialized.
 738
 739   If any reserved bits in Address are set, then ASSERT().
 740   If Address is not aligned on a 32-bit boundary, then ASSERT().
 741
 742   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 743   @param  OrData    The value to OR with the PCI configuration register.
 744
 745   @return The value written to the PCI configuration register.
 746
 747 **/
 748 UINT32
 749 EFIAPI
 750 PciSegmentOr32 (
 751   IN UINT64                    Address,
 752   IN UINT32                    OrData
 753   );
 754
 755 /**
 756   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 757
 758   Reads the 32-bit PCI configuration register specified by Address,
 759   performs a bitwise AND between the read result and the value specified by AndData,
 760   and writes the result to the 32-bit PCI configuration register specified by Address.
 761   The value written to the PCI configuration register is returned.
 762   This function must guarantee that all PCI read and write operations are serialized.
 763
 764   If any reserved bits in Address are set, then ASSERT().
 765   If Address is not aligned on a 32-bit boundary, then ASSERT().
 766
 767   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 768   @param  AndData   The value to AND with the PCI configuration register.
 769
 770   @return The value written to the PCI configuration register.
 771
 772 **/
 773 UINT32
 774 EFIAPI
 775 PciSegmentAnd32 (
 776   IN UINT64                    Address,
 777   IN UINT32                    AndData
 778   );
 779
 780 /**
 781   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 782   followed a  bitwise OR with another 32-bit value.
 783
 784   Reads the 32-bit PCI configuration register specified by Address,
 785   performs a bitwise AND between the read result and the value specified by AndData,
 786   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 787   and writes the result to the 32-bit PCI configuration register specified by Address.
 788   The value written to the PCI configuration register is returned.
 789   This function must guarantee that all PCI read and write operations are serialized.
 790
 791   If any reserved bits in Address are set, then ASSERT().
 792   If Address is not aligned on a 32-bit boundary, then ASSERT().
 793
 794   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 795   @param  AndData   The value to AND with the PCI configuration register.
 796   @param  OrData    The value to OR with the PCI configuration register.
 797
 798   @return The value written to the PCI configuration register.
 799
 800 **/
 801 UINT32
 802 EFIAPI
 803 PciSegmentAndThenOr32 (
 804   IN UINT64                    Address,
 805   IN UINT32                    AndData,
 806   IN UINT32                    OrData
 807   );
 808
 809 /**
 810   Reads a bit field of a PCI configuration register.
 811
 812   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 813   specified by the StartBit and the EndBit. The value of the bit field is
 814   returned.
 815
 816   If any reserved bits in Address are set, then ASSERT().
 817   If Address is not aligned on a 32-bit boundary, then ASSERT().
 818   If StartBit is greater than 31, then ASSERT().
 819   If EndBit is greater than 31, then ASSERT().
 820   If EndBit is less than StartBit, then ASSERT().
 821
 822   @param  Address   PCI configuration register to read.
 823   @param  StartBit  The ordinal of the least significant bit in the bit field.
 824                     Range 0..31.
 825   @param  EndBit    The ordinal of the most significant bit in the bit field.
 826                     Range 0..31.
 827
 828   @return The value of the bit field read from the PCI configuration register.
 829
 830 **/
 831 UINT32
 832 EFIAPI
 833 PciSegmentBitFieldRead32 (
 834   IN UINT64                    Address,
 835   IN UINTN                     StartBit,
 836   IN UINTN                     EndBit
 837   );
 838
 839 /**
 840   Writes a bit field to a PCI configuration register.
 841
 842   Writes Value to the bit field of the PCI configuration register. The bit
 843   field is specified by the StartBit and the EndBit. All other bits in the
 844   destination PCI configuration register are preserved. The new value of the
 845   32-bit register is returned.
 846
 847   If any reserved bits in Address are set, then ASSERT().
 848   If Address is not aligned on a 32-bit boundary, then ASSERT().
 849   If StartBit is greater than 31, then ASSERT().
 850   If EndBit is greater than 31, then ASSERT().
 851   If EndBit is less than StartBit, then ASSERT().
 852   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 853
 854   @param  Address   PCI configuration register to write.
 855   @param  StartBit  The ordinal of the least significant bit in the bit field.
 856                     Range 0..31.
 857   @param  EndBit    The ordinal of the most significant bit in the bit field.
 858                     Range 0..31.
 859   @param  Value     New value of the bit field.
 860
 861   @return The value written back to the PCI configuration register.
 862
 863 **/
 864 UINT32
 865 EFIAPI
 866 PciSegmentBitFieldWrite32 (
 867   IN UINT64                    Address,
 868   IN UINTN                     StartBit,
 869   IN UINTN                     EndBit,
 870   IN UINT32                    Value
 871   );
 872
 873 /**
 874   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 875   writes the result back to the bit field in the 32-bit port.
 876
 877   Reads the 32-bit PCI configuration register specified by Address, performs a
 878   bitwise OR between the read result and the value specified by
 879   OrData, and writes the result to the 32-bit PCI configuration register
 880   specified by Address. The value written to the PCI configuration register is
 881   returned. This function must guarantee that all PCI read and write operations
 882   are serialized. Extra left bits in OrData are stripped.
 883
 884   If any reserved bits in Address are set, then ASSERT().
 885   If StartBit is greater than 31, then ASSERT().
 886   If EndBit is greater than 31, then ASSERT().
 887   If EndBit is less than StartBit, then ASSERT().
 888   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 889
 890   @param  Address   PCI configuration register to write.
 891   @param  StartBit  The ordinal of the least significant bit in the bit field.
 892                     Range 0..31.
 893   @param  EndBit    The ordinal of the most significant bit in the bit field.
 894                     Range 0..31.
 895   @param  OrData    The value to OR with the PCI configuration register.
 896
 897   @return The value written back to the PCI configuration register.
 898
 899 **/
 900 UINT32
 901 EFIAPI
 902 PciSegmentBitFieldOr32 (
 903   IN UINT64                    Address,
 904   IN UINTN                     StartBit,
 905   IN UINTN                     EndBit,
 906   IN UINT32                    OrData
 907   );
 908
 909 /**
 910   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 911   AND, and writes the result back to the bit field in the 32-bit register.
 912
 913
 914   Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
 915   AND between the read result and the value specified by AndData, and writes the result
 916   to the 32-bit PCI configuration register specified by Address. The value written to
 917   the PCI configuration register is returned.  This function must guarantee that all PCI
 918   read and write operations are serialized.  Extra left bits in AndData are stripped.
 919   If any reserved bits in Address are set, then ASSERT().
 920   If Address is not aligned on a 32-bit boundary, then ASSERT().
 921   If StartBit is greater than 31, then ASSERT().
 922   If EndBit is greater than 31, then ASSERT().
 923   If EndBit is less than StartBit, then ASSERT().
 924   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 925
 926   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 927   @param  StartBit  The ordinal of the least significant bit in the bit field.
 928                     Range 0..31.
 929   @param  EndBit    The ordinal of the most significant bit in the bit field.
 930                     Range 0..31.
 931   @param  AndData   The value to AND with the PCI configuration register.
 932
 933   @return The value written back to the PCI configuration register.
 934
 935 **/
 936 UINT32
 937 EFIAPI
 938 PciSegmentBitFieldAnd32 (
 939   IN UINT64                    Address,
 940   IN UINTN                     StartBit,
 941   IN UINTN                     EndBit,
 942   IN UINT32                    AndData
 943   );
 944
 945 /**
 946   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 947   bitwise OR, and writes the result back to the bit field in the
 948   32-bit port.
 949
 950   Reads the 32-bit PCI configuration register specified by Address, performs a
 951   bitwise AND followed by a bitwise OR between the read result and
 952   the value specified by AndData, and writes the result to the 32-bit PCI
 953   configuration register specified by Address. The value written to the PCI
 954   configuration register is returned. This function must guarantee that all PCI
 955   read and write operations are serialized. Extra left bits in both AndData and
 956   OrData are stripped.
 957
 958   If any reserved bits in Address are set, then ASSERT().
 959   If StartBit is greater than 31, then ASSERT().
 960   If EndBit is greater than 31, then ASSERT().
 961   If EndBit is less than StartBit, then ASSERT().
 962   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 963   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 964
 965   @param  Address   PCI configuration register to write.
 966   @param  StartBit  The ordinal of the least significant bit in the bit field.
 967                     Range 0..31.
 968   @param  EndBit    The ordinal of the most significant bit in the bit field.
 969                     Range 0..31.
 970   @param  AndData   The value to AND with the PCI configuration register.
 971   @param  OrData    The value to OR with the result of the AND operation.
 972
 973   @return The value written back to the PCI configuration register.
 974
 975 **/
 976 UINT32
 977 EFIAPI
 978 PciSegmentBitFieldAndThenOr32 (
 979   IN UINT64                    Address,
 980   IN UINTN                     StartBit,
 981   IN UINTN                     EndBit,
 982   IN UINT32                    AndData,
 983   IN UINT32                    OrData
 984   );
 985
 986 /**
 987   Reads a range of PCI configuration registers into a caller supplied buffer.
 988
 989   Reads the range of PCI configuration registers specified by StartAddress and
 990   Size into the buffer specified by Buffer. This function only allows the PCI
 991   configuration registers from a single PCI function to be read. Size is
 992   returned. When possible 32-bit PCI configuration read cycles are used to read
 993   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 994   and 16-bit PCI configuration read cycles may be used at the beginning and the
 995   end of the range.
 996
 997   If any reserved bits in StartAddress are set, then ASSERT().
 998   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 999   If Size > 0 and Buffer is NULL, then ASSERT().
1000
1001   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1002                         Function and Register.
1003   @param  Size          Size in bytes of the transfer.
1004   @param  Buffer        Pointer to a buffer receiving the data read.
1005
1006   @return Size
1007
1008 **/
1009 UINTN
1010 EFIAPI
1011 PciSegmentReadBuffer (
1012   IN  UINT64                   StartAddress,
1013   IN  UINTN                    Size,
1014   OUT VOID                     *Buffer
1015   );
1016
1017 /**
1018   Copies the data in a caller supplied buffer to a specified range of PCI
1019   configuration space.
1020
1021   Writes the range of PCI configuration registers specified by StartAddress and
1022   Size from the buffer specified by Buffer. This function only allows the PCI
1023   configuration registers from a single PCI function to be written. Size is
1024   returned. When possible 32-bit PCI configuration write cycles are used to
1025   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1026   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1027   and the end of the range.
1028
1029   If any reserved bits in StartAddress are set, then ASSERT().
1030   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1031   If Size > 0 and Buffer is NULL, then ASSERT().
1032
1033   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1034                         Function and Register.
1035   @param  Size          Size in bytes of the transfer.
1036   @param  Buffer        Pointer to a buffer containing the data to write.
1037
1038   @return The parameter of Size.
1039
1040 **/
1041 UINTN
1042 EFIAPI
1043 PciSegmentWriteBuffer (
1044   IN UINT64                    StartAddress,
1045   IN UINTN                     Size,
1046   IN VOID                      *Buffer
1047   );
1048
1049 #endif