MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
   3
   4   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
   5   registers on PCI root bridges on any supported PCI segment.  These library services take a single
   6   address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   7   The layout of this address parameter is as follows:
   8
   9             PCI Register:       Bits 0..11
  10             PCI Function        Bits 12..14
  11             PCI Device  Bits 15..19
  12             PCI Bus     Bits 20..27
  13             Reserved    Bits 28..31.  Must be 0.
  14             PCI Segment Bits 32..47
  15             Reserved    Bits 48..63.  Must be 0.
  16
  17   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
  18   63             48  47    32  31           28 27         20 19    15 14      12 11         0
  19
  20   These functions perform PCI configuration cycles using the default PCI configuration access
  21   method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
  22   may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
  23   access method.  Modules will typically use the PCI Segment Library for its PCI configuration
  24   accesses when PCI Segments other than Segment #0 must be accessed.
  25
  26 Copyright (c) 2006 - 2008, Intel Corporation
  27 All rights reserved. This program and the accompanying materials
  28 are licensed and made available under the terms and conditions of the BSD License
  29 which accompanies this distribution.  The full text of the license may be found at
  30 http://opensource.org/licenses/bsd-license.php
  31
  32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  34
  35 **/
  36
  37 #ifndef __PCI_SEGMENT_LIB__
  38 #define __PCI_SEGMENT_LIB__
  39
  40
  41 /**
  42   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  43   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  44
  45   Computes an address that is compatible with the PCI Segment Library functions.
  46   The unused upper bits of Segment, Bus, Device, Function,
  47   and Register are stripped prior to the generation of the address.
  48
  49   @param  Segment   PCI Segment number.  Range 0..65535.
  50   @param  Bus       PCI Bus number.  Range 0..255.
  51   @param  Device    PCI Device number.  Range 0..31.
  52   @param  Function  PCI Function number.  Range 0..7.
  53   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  54
  55   @return The address that is compatible with the PCI Segment Library functions.
  56
  57 **/
  58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
  59   ( ((Register) & 0xfff)              | \
  60     (((Function) & 0x07) << 12)       | \
  61     (((Device) & 0x1f) << 15)         | \
  62     (((Bus) & 0xff) << 20)            | \
  63     (LShiftU64((Segment) & 0xffff, 32)) \
  64   )
  65
  66 /**
  67   Register a PCI device so PCI configuration registers may be accessed after
  68   SetVirtualAddressMap().
  69
  70   If Address > 0x0FFFFFFF, then ASSERT().
  71
  72   @param  Address Address that encodes the PCI Bus, Device, Function and
  73                   Register.
  74
  75   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  76   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  77                                    after ExitBootServices().
  78   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  79                                    at runtime could not be mapped.
  80   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  81                                    complete the registration.
  82
  83 **/
  84 RETURN_STATUS
  85 EFIAPI
  86 PciSegmentRegisterForRuntimeAccess (
  87   IN UINTN  Address
  88   );
  89
  90 /**
  91   Reads an 8-bit PCI configuration register.
  92
  93   Reads and returns the 8-bit PCI configuration register specified by Address.
  94   This function must guarantee that all PCI read and write operations are serialized.
  95
  96   If any reserved bits in Address are set, then ASSERT().
  97
  98   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  99
 100   @return The 8-bit PCI configuration register specified by Address.
 101
 102 **/
 103 UINT8
 104 EFIAPI
 105 PciSegmentRead8 (
 106   IN UINT64                    Address
 107   );
 108
 109 /**
 110   Writes an 8-bit PCI configuration register.
 111
 112   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
 113   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 114
 115   If Address > 0x0FFFFFFF, then ASSERT().
 116
 117   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 118   @param  Value       The value to write.
 119
 120   @return The parameter of Value.
 121
 122 **/
 123 UINT8
 124 EFIAPI
 125 PciSegmentWrite8 (
 126   IN UINT64                    Address,
 127   IN UINT8                     Value
 128   );
 129
 130 /**
 131   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with an 8-bit value.
 132
 133   Reads the 8-bit PCI configuration register specified by Address,
 134   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 135   and writes the result to the 8-bit PCI configuration register specified by Address.
 136   The value written to the PCI configuration register is returned.
 137   This function must guarantee that all PCI read and write operations are serialized.
 138
 139   If any reserved bits in Address are set, then ASSERT().
 140
 141   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 142   @param  OrData    The value to OR with the PCI configuration register.
 143
 144   @return The value written to the PCI configuration register.
 145
 146 **/
 147 UINT8
 148 EFIAPI
 149 PciSegmentOr8 (
 150   IN UINT64                    Address,
 151   IN UINT8                     OrData
 152   );
 153
 154 /**
 155   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 156
 157   Reads the 8-bit PCI configuration register specified by Address,
 158   performs a bitwise AND between the read result and the value specified by AndData,
 159   and writes the result to the 8-bit PCI configuration register specified by Address.
 160   The value written to the PCI configuration register is returned.
 161   This function must guarantee that all PCI read and write operations are serialized.
 162   If any reserved bits in Address are set, then ASSERT().
 163
 164   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 165   @param  AndData   The value to AND with the PCI configuration register.
 166
 167   @return The value written to the PCI configuration register.
 168
 169 **/
 170 UINT8
 171 EFIAPI
 172 PciSegmentAnd8 (
 173   IN UINT64                    Address,
 174   IN UINT8                     AndData
 175   );
 176
 177 /**
 178   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 179   followed a  bitwise inclusive OR with another 8-bit value.
 180
 181   Reads the 8-bit PCI configuration register specified by Address,
 182   performs a bitwise AND between the read result and the value specified by AndData,
 183   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 184   and writes the result to the 8-bit PCI configuration register specified by Address.
 185   The value written to the PCI configuration register is returned.
 186   This function must guarantee that all PCI read and write operations are serialized.
 187
 188   If any reserved bits in Address are set, then ASSERT().
 189
 190   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 191   @param  AndData    The value to AND with the PCI configuration register.
 192   @param  OrData    The value to OR with the PCI configuration register.
 193
 194   @return The value written to the PCI configuration register.
 195
 196 **/
 197 UINT8
 198 EFIAPI
 199 PciSegmentAndThenOr8 (
 200   IN UINT64                    Address,
 201   IN UINT8                     AndData,
 202   IN UINT8                     OrData
 203   );
 204
 205 /**
 206   Reads a bit field of a PCI configuration register.
 207
 208   Reads the bit field in an 8-bit PCI configuration register.
 209   The bit field is specified by the StartBit and the EndBit.
 210   The value of the bit field is returned.
 211
 212   If any reserved bits in Address are set, then ASSERT().
 213   If StartBit is greater than 7, then ASSERT().
 214   If EndBit is greater than 7, then ASSERT().
 215   If EndBit is less than StartBit, then ASSERT().
 216
 217   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 218   @param  StartBit  The ordinal of the least significant bit in the bit field.
 219                     The ordinal of the least significant bit in a byte is bit 0.
 220   @param  EndBit    The ordinal of the most significant bit in the bit field.
 221                     The ordinal of the most significant bit in a byte is bit 7.
 222
 223   @return The value of the bit field.
 224
 225 **/
 226 UINT8
 227 EFIAPI
 228 PciSegmentBitFieldRead8 (
 229   IN UINT64                    Address,
 230   IN UINTN                     StartBit,
 231   IN UINTN                     EndBit
 232   );
 233
 234 /**
 235   Writes a bit field to a PCI configuration register.
 236
 237   Writes Value to the bit field of the PCI configuration register.
 238   The bit field is specified by the StartBit and the EndBit.
 239   All other bits in the destination PCI configuration register are preserved.
 240   The new value of the 8-bit register is returned.
 241   If any reserved bits in Address are set, then ASSERT().
 242   If StartBit is greater than 7, then ASSERT().
 243   If EndBit is greater than 7, then ASSERT().
 244   If EndBit is less than StartBit, then ASSERT().
 245
 246   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 247   @param  StartBit  The ordinal of the least significant bit in the bit field.
 248                     The ordinal of the least significant bit in a byte is bit 0.
 249   @param  EndBit    The ordinal of the most significant bit in the bit field.
 250                     The ordinal of the most significant bit in a byte is bit 7.
 251   @param  Value     New value of the bit field.
 252
 253   @return The new value of the 8-bit register.
 254
 255 **/
 256 UINT8
 257 EFIAPI
 258 PciSegmentBitFieldWrite8 (
 259   IN UINT64                    Address,
 260   IN UINTN                     StartBit,
 261   IN UINTN                     EndBit,
 262   IN UINT8                     Value
 263   );
 264
 265 /**
 266   Reads the 8-bit PCI configuration register specified by Address,
 267   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 268   and writes the result to the 8-bit PCI configuration register specified by Address.
 269
 270   If any reserved bits in Address are set, then ASSERT().
 271   If StartBit is greater than 7, then ASSERT().
 272   If EndBit is greater than 7, then ASSERT().
 273   If EndBit is less than StartBit, then ASSERT().
 274
 275   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 276   @param  StartBit  The ordinal of the least significant bit in the bit field.
 277                     The ordinal of the least significant bit in a byte is bit 0.
 278   @param  EndBit    The ordinal of the most significant bit in the bit field.
 279                     The ordinal of the most significant bit in a byte is bit 7.
 280   @param  OrData    The value to OR with the read value from the PCI configuration register.
 281
 282   @return The value written to the PCI configuration register.
 283
 284 **/
 285 UINT8
 286 EFIAPI
 287 PciSegmentBitFieldOr8 (
 288   IN UINT64                    Address,
 289   IN UINTN                     StartBit,
 290   IN UINTN                     EndBit,
 291   IN UINT8                     OrData
 292   );
 293
 294 /**
 295   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR,
 296   and writes the result back to the bit field in the 8-bit port.
 297
 298   Reads the 8-bit PCI configuration register specified by Address,
 299   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 300   and writes the result to the 8-bit PCI configuration register specified by Address.
 301   The value written to the PCI configuration register is returned.
 302   This function must guarantee that all PCI read and write operations are serialized.
 303   Extra left bits in OrData are stripped.
 304
 305   If any reserved bits in Address are set, then ASSERT().
 306   If StartBit is greater than 7, then ASSERT().
 307   If EndBit is greater than 7, then ASSERT().
 308   If EndBit is less than StartBit, then ASSERT().
 309
 310   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 311   @param  StartBit  The ordinal of the least significant bit in the bit field.
 312                     The ordinal of the least significant bit in a byte is bit 0.
 313   @param  EndBit    The ordinal of the most significant bit in the bit field.
 314                     The ordinal of the most significant bit in a byte is bit 7.
 315   @param  AndData   The value to AND with the read value from the PCI configuration register.
 316
 317   @return The value written to the PCI configuration register.
 318
 319 **/
 320 UINT8
 321 EFIAPI
 322 PciSegmentBitFieldAnd8 (
 323   IN UINT64                    Address,
 324   IN UINTN                     StartBit,
 325   IN UINTN                     EndBit,
 326   IN UINT8                     AndData
 327   );
 328
 329 /**
 330   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise AND,
 331   and writes the result back to the bit field in the 8-bit register.
 332
 333   Reads the 8-bit PCI configuration register specified by Address,
 334   performs a bitwise AND between the read result and the value specified by AndData,
 335   and writes the result to the 8-bit PCI configuration register specified by Address.
 336   The value written to the PCI configuration register is returned.
 337   This function must guarantee that all PCI read and write operations are serialized.
 338   Extra left bits in AndData are stripped.
 339
 340   If any reserved bits in Address are set, then ASSERT().
 341   If StartBit is greater than 7, then ASSERT().
 342   If EndBit is greater than 7, then ASSERT().
 343   If EndBit is less than StartBit, then ASSERT().
 344
 345   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 346   @param  StartBit  The ordinal of the least significant bit in the bit field.
 347                     The ordinal of the least significant bit in a byte is bit 0.
 348   @param  EndBit    The ordinal of the most significant bit in the bit field.
 349                     The ordinal of the most significant bit in a byte is bit 7.
 350   @param  AndData   The value to AND with the read value from the PCI configuration register.
 351   @param  OrData    The value to OR with the read value from the PCI configuration register.
 352
 353   @return The value written to the PCI configuration register.
 354
 355 **/
 356 UINT8
 357 EFIAPI
 358 PciSegmentBitFieldAndThenOr8 (
 359   IN UINT64                    Address,
 360   IN UINTN                     StartBit,
 361   IN UINTN                     EndBit,
 362   IN UINT8                     AndData,
 363   IN UINT8                     OrData
 364   );
 365
 366 /**
 367   Reads a 16-bit PCI configuration register.
 368
 369   Reads and returns the 16-bit PCI configuration register specified by Address.
 370   This function must guarantee that all PCI read and write operations are serialized.
 371
 372   If any reserved bits in Address are set, then ASSERT().
 373   If Address is not aligned on a 16-bit boundary, then ASSERT().
 374
 375   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 376
 377   @return The 16-bit PCI configuration register specified by Address.
 378
 379 **/
 380 UINT16
 381 EFIAPI
 382 PciSegmentRead16 (
 383   IN UINT64                    Address
 384   );
 385
 386 /**
 387   Writes a 16-bit PCI configuration register.
 388
 389   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 390   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 391
 392   If any reserved bits in Address are set, then ASSERT().
 393   If Address is not aligned on a 16-bit boundary, then ASSERT().
 394
 395   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 396   @param  Value       The value to write.
 397
 398   @return The parameter of Value.
 399
 400 **/
 401 UINT16
 402 EFIAPI
 403 PciSegmentWrite16 (
 404   IN UINT64                    Address,
 405   IN UINT16                    Value
 406   );
 407
 408 /**
 409   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with a 16-bit value.
 410
 411   Reads the 16-bit PCI configuration register specified by Address,
 412   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 413   and writes the result to the 16-bit PCI configuration register specified by Address.
 414   The value written to the PCI configuration register is returned.
 415   This function must guarantee that all PCI read and write operations are serialized.
 416
 417   If any reserved bits in Address are set, then ASSERT().
 418   If Address is not aligned on a 16-bit boundary, then ASSERT().
 419
 420   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 421   @param  OrData    The value to OR with the PCI configuration register.
 422
 423   @return The value written to the PCI configuration register.
 424
 425 **/
 426 UINT16
 427 EFIAPI
 428 PciSegmentOr16 (
 429   IN UINT64                    Address,
 430   IN UINT16                    OrData
 431   );
 432
 433 /**
 434   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 435
 436   Reads the 16-bit PCI configuration register specified by Address,
 437   performs a bitwise AND between the read result and the value specified by AndData,
 438   and writes the result to the 16-bit PCI configuration register specified by Address.
 439   The value written to the PCI configuration register is returned.
 440   This function must guarantee that all PCI read and write operations are serialized.
 441
 442   If any reserved bits in Address are set, then ASSERT().
 443   If Address is not aligned on a 16-bit boundary, then ASSERT().
 444
 445   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 446   @param  AndData   The value to AND with the PCI configuration register.
 447
 448   @return The value written to the PCI configuration register.
 449
 450 **/
 451 UINT16
 452 EFIAPI
 453 PciSegmentAnd16 (
 454   IN UINT64                    Address,
 455   IN UINT16                    AndData
 456   );
 457
 458 /**
 459   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 460   followed a  bitwise inclusive OR with another 16-bit value.
 461
 462   Reads the 16-bit PCI configuration register specified by Address,
 463   performs a bitwise AND between the read result and the value specified by AndData,
 464   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 465   and writes the result to the 16-bit PCI configuration register specified by Address.
 466   The value written to the PCI configuration register is returned.
 467   This function must guarantee that all PCI read and write operations are serialized.
 468
 469   If any reserved bits in Address are set, then ASSERT().
 470   If Address is not aligned on a 16-bit boundary, then ASSERT().
 471
 472   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 473   @param  AndData    The value to AND with the PCI configuration register.
 474   @param  OrData    The value to OR with the PCI configuration register.
 475
 476   @return The value written to the PCI configuration register.
 477
 478 **/
 479 UINT16
 480 EFIAPI
 481 PciSegmentAndThenOr16 (
 482   IN UINT64                    Address,
 483   IN UINT16                    AndData,
 484   IN UINT16                    OrData
 485   );
 486
 487 /**
 488   Reads a bit field of a PCI configuration register.
 489
 490   Reads the bit field in a 16-bit PCI configuration register.
 491   The bit field is specified by the StartBit and the EndBit.
 492   The value of the bit field is returned.
 493
 494   If any reserved bits in Address are set, then ASSERT().
 495   If Address is not aligned on a 16-bit boundary, then ASSERT().
 496   If StartBit is greater than 7, then ASSERT().
 497   If EndBit is greater than 7, then ASSERT().
 498   If EndBit is less than StartBit, then ASSERT().
 499
 500   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 501   @param  StartBit  The ordinal of the least significant bit in the bit field.
 502                     The ordinal of the least significant bit in a byte is bit 0.
 503   @param  EndBit    The ordinal of the most significant bit in the bit field.
 504                     The ordinal of the most significant bit in a byte is bit 7.
 505
 506   @return The value of the bit field.
 507
 508 **/
 509 UINT16
 510 EFIAPI
 511 PciSegmentBitFieldRead16 (
 512   IN UINT64                    Address,
 513   IN UINTN                     StartBit,
 514   IN UINTN                     EndBit
 515   );
 516
 517 /**
 518   Writes a bit field to a PCI configuration register.
 519
 520   Writes Value to the bit field of the PCI configuration register.
 521   The bit field is specified by the StartBit and the EndBit.
 522   All other bits in the destination PCI configuration register are preserved.
 523   The new value of the 16-bit register is returned.
 524
 525   If any reserved bits in Address are set, then ASSERT().
 526   If Address is not aligned on a 16-bit boundary, then ASSERT().
 527   If StartBit is greater than 7, then ASSERT().
 528   If EndBit is greater than 7, then ASSERT().
 529   If EndBit is less than StartBit, then ASSERT().
 530
 531   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 532   @param  StartBit  The ordinal of the least significant bit in the bit field.
 533                     The ordinal of the least significant bit in a byte is bit 0.
 534   @param  EndBit    The ordinal of the most significant bit in the bit field.
 535                     The ordinal of the most significant bit in a byte is bit 7.
 536   @param  Value     New value of the bit field.
 537
 538   @return The new value of the 16-bit register.
 539
 540 **/
 541 UINT16
 542 EFIAPI
 543 PciSegmentBitFieldWrite16 (
 544   IN UINT64                    Address,
 545   IN UINTN                     StartBit,
 546   IN UINTN                     EndBit,
 547   IN UINT16                    Value
 548   );
 549
 550 /**
 551   Reads the 16-bit PCI configuration register specified by Address,
 552   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 553   and writes the result to the 16-bit PCI configuration register specified by Address.
 554
 555   If any reserved bits in Address are set, then ASSERT().
 556   If Address is not aligned on a 16-bit boundary, then ASSERT().
 557   If StartBit is greater than 15, then ASSERT().
 558   If EndBit is greater than 15, then ASSERT().
 559   If EndBit is less than StartBit, then ASSERT().
 560
 561   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 562   @param  StartBit  The ordinal of the least significant bit in the bit field.
 563                     The ordinal of the least significant bit in a byte is bit 0.
 564   @param  EndBit    The ordinal of the most significant bit in the bit field.
 565                     The ordinal of the most significant bit in a byte is bit 7.
 566   @param  OrData    The value to OR with the read value from the PCI configuration register.
 567
 568   @return The value written to the PCI configuration register.
 569
 570 **/
 571 UINT16
 572 EFIAPI
 573 PciSegmentBitFieldOr16 (
 574   IN UINT64                    Address,
 575   IN UINTN                     StartBit,
 576   IN UINTN                     EndBit,
 577   IN UINT16                    OrData
 578   );
 579
 580 /**
 581   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
 582   and writes the result back to the bit field in the 16-bit port.
 583
 584   Reads the 16-bit PCI configuration register specified by Address,
 585   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 586   and writes the result to the 16-bit PCI configuration register specified by Address.
 587   The value written to the PCI configuration register is returned.
 588   This function must guarantee that all PCI read and write operations are serialized.
 589   Extra left bits in OrData are stripped.
 590
 591   If any reserved bits in Address are set, then ASSERT().
 592   If Address is not aligned on a 16-bit boundary, then ASSERT().
 593   If StartBit is greater than 7, then ASSERT().
 594   If EndBit is greater than 7, then ASSERT().
 595   If EndBit is less than StartBit, then ASSERT().
 596
 597   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 598   @param  StartBit  The ordinal of the least significant bit in the bit field.
 599                     The ordinal of the least significant bit in a byte is bit 0.
 600   @param  EndBit    The ordinal of the most significant bit in the bit field.
 601                     The ordinal of the most significant bit in a byte is bit 7.
 602   @param  AndData   The value to AND with the read value from the PCI configuration register.
 603
 604   @return The value written to the PCI configuration register.
 605
 606 **/
 607 UINT16
 608 EFIAPI
 609 PciSegmentBitFieldAnd16 (
 610   IN UINT64                    Address,
 611   IN UINTN                     StartBit,
 612   IN UINTN                     EndBit,
 613   IN UINT16                    AndData
 614   );
 615
 616 /**
 617   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise AND,
 618   and writes the result back to the bit field in the 16-bit register.
 619
 620   Reads the 16-bit PCI configuration register specified by Address,
 621   performs a bitwise AND between the read result and the value specified by AndData,
 622   and writes the result to the 16-bit PCI configuration register specified by Address.
 623   The value written to the PCI configuration register is returned.
 624   This function must guarantee that all PCI read and write operations are serialized.
 625   Extra left bits in AndData are stripped.
 626
 627   If any reserved bits in Address are set, then ASSERT().
 628   If Address is not aligned on a 16-bit boundary, then ASSERT()..
 629   If StartBit is greater than 7, then ASSERT().
 630   If EndBit is greater than 7, then ASSERT().
 631   If EndBit is less than StartBit, then ASSERT().
 632
 633   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 634   @param  StartBit  The ordinal of the least significant bit in the bit field.
 635                     The ordinal of the least significant bit in a byte is bit 0.
 636   @param  EndBit    The ordinal of the most significant bit in the bit field.
 637                     The ordinal of the most significant bit in a byte is bit 7.
 638   @param  AndData   The value to AND with the read value from the PCI configuration register.
 639   @param  OrData    The value to OR with the read value from the PCI configuration register.
 640
 641   @return The value written to the PCI configuration register.
 642
 643 **/
 644 UINT16
 645 EFIAPI
 646 PciSegmentBitFieldAndThenOr16 (
 647   IN UINT64                    Address,
 648   IN UINTN                     StartBit,
 649   IN UINTN                     EndBit,
 650   IN UINT16                    AndData,
 651   IN UINT16                    OrData
 652   );
 653
 654 /**
 655   Reads a 32-bit PCI configuration register.
 656
 657   Reads and returns the 32-bit PCI configuration register specified by Address.
 658   This function must guarantee that all PCI read and write operations are serialized.
 659
 660   If any reserved bits in Address are set, then ASSERT().
 661   If Address is not aligned on a 32-bit boundary, then ASSERT().
 662
 663   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 664
 665   @return The 32-bit PCI configuration register specified by Address.
 666
 667 **/
 668 UINT32
 669 EFIAPI
 670 PciSegmentRead32 (
 671   IN UINT64                    Address
 672   );
 673
 674 /**
 675   Writes a 32-bit PCI configuration register.
 676
 677   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 678   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 679
 680   If any reserved bits in Address are set, then ASSERT().
 681   If Address is not aligned on a 32-bit boundary, then ASSERT().
 682
 683   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 684   @param  Value       The value to write.
 685
 686   @return The parameter of Value.
 687
 688 **/
 689 UINT32
 690 EFIAPI
 691 PciSegmentWrite32 (
 692   IN UINT64                    Address,
 693   IN UINT32                    Value
 694   );
 695
 696 /**
 697   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with a 32-bit value.
 698
 699   Reads the 32-bit PCI configuration register specified by Address,
 700   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 701   and writes the result to the 32-bit PCI configuration register specified by Address.
 702   The value written to the PCI configuration register is returned.
 703   This function must guarantee that all PCI read and write operations are serialized.
 704
 705   If any reserved bits in Address are set, then ASSERT().
 706   If Address is not aligned on a 32-bit boundary, then ASSERT().
 707
 708   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 709   @param  OrData    The value to OR with the PCI configuration register.
 710
 711   @return The value written to the PCI configuration register.
 712
 713 **/
 714 UINT32
 715 EFIAPI
 716 PciSegmentOr32 (
 717   IN UINT64                    Address,
 718   IN UINT32                    OrData
 719   );
 720
 721 /**
 722   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 723
 724   Reads the 32-bit PCI configuration register specified by Address,
 725   performs a bitwise AND between the read result and the value specified by AndData,
 726   and writes the result to the 32-bit PCI configuration register specified by Address.
 727   The value written to the PCI configuration register is returned.
 728   This function must guarantee that all PCI read and write operations are serialized.
 729
 730   If any reserved bits in Address are set, then ASSERT().
 731   If Address is not aligned on a 32-bit boundary, then ASSERT().
 732
 733   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 734   @param  AndData   The value to AND with the PCI configuration register.
 735
 736   @return The value written to the PCI configuration register.
 737
 738 **/
 739 UINT32
 740 EFIAPI
 741 PciSegmentAnd32 (
 742   IN UINT64                    Address,
 743   IN UINT32                    AndData
 744   );
 745
 746 /**
 747   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 748   followed a  bitwise inclusive OR with another 32-bit value.
 749
 750   Reads the 32-bit PCI configuration register specified by Address,
 751   performs a bitwise AND between the read result and the value specified by AndData,
 752   performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,
 753   and writes the result to the 32-bit PCI configuration register specified by Address.
 754   The value written to the PCI configuration register is returned.
 755   This function must guarantee that all PCI read and write operations are serialized.
 756
 757   If any reserved bits in Address are set, then ASSERT().
 758   If Address is not aligned on a 32-bit boundary, then ASSERT().
 759
 760   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 761   @param  AndData   The value to AND with the PCI configuration register.
 762   @param  OrData    The value to OR with the PCI configuration register.
 763
 764   @return The value written to the PCI configuration register.
 765
 766 **/
 767 UINT32
 768 EFIAPI
 769 PciSegmentAndThenOr32 (
 770   IN UINT64                    Address,
 771   IN UINT32                    AndData,
 772   IN UINT32                    OrData
 773   );
 774
 775 /**
 776   Reads a bit field of a PCI configuration register.
 777
 778   Reads the bit field in a 32-bit PCI configuration register.
 779   The bit field is specified by the StartBit and the EndBit.
 780   The value of the bit field is returned.
 781
 782   If any reserved bits in Address are set, then ASSERT().
 783   If Address is not aligned on a 32-bit boundary, then ASSERT().
 784   If StartBit is greater than 7, then ASSERT().
 785   If EndBit is greater than 7, then ASSERT().
 786   If EndBit is less than StartBit, then ASSERT().
 787
 788   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 789   @param  StartBit  The ordinal of the least significant bit in the bit field.
 790                     The ordinal of the least significant bit in a byte is bit 0.
 791   @param  EndBit    The ordinal of the most significant bit in the bit field.
 792                     The ordinal of the most significant bit in a byte is bit 7.
 793
 794   @return The value of the bit field.
 795
 796 **/
 797 UINT32
 798 EFIAPI
 799 PciSegmentBitFieldRead32 (
 800   IN UINT64                    Address,
 801   IN UINTN                     StartBit,
 802   IN UINTN                     EndBit
 803   );
 804
 805 /**
 806   Writes a bit field to a PCI configuration register.
 807
 808   Writes Value to the bit field of the PCI configuration register.
 809   The bit field is specified by the StartBit and the EndBit.
 810   All other bits in the destination PCI configuration register are preserved.
 811   The new value of the 32-bit register is returned.
 812
 813   If any reserved bits in Address are set, then ASSERT().
 814   If Address is not aligned on a 32-bit boundary, then ASSERT().
 815   If StartBit is greater than 7, then ASSERT().
 816   If EndBit is greater than 7, then ASSERT().
 817   If EndBit is less than StartBit, then ASSERT().
 818
 819   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 820   @param  StartBit  The ordinal of the least significant bit in the bit field.
 821                     The ordinal of the least significant bit in a byte is bit 0.
 822   @param  EndBit    The ordinal of the most significant bit in the bit field.
 823                     The ordinal of the most significant bit in a byte is bit 7.
 824   @param  Value     New value of the bit field.
 825
 826   @return The new value of the 32-bit register.
 827
 828 **/
 829 UINT32
 830 EFIAPI
 831 PciSegmentBitFieldWrite32 (
 832   IN UINT64                    Address,
 833   IN UINTN                     StartBit,
 834   IN UINTN                     EndBit,
 835   IN UINT32                    Value
 836   );
 837
 838 /**
 839   Reads the 32-bit PCI configuration register specified by Address,
 840   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 841   and writes the result to the 32-bit PCI configuration register specified by Address.
 842
 843   If any reserved bits in Address are set, then ASSERT().
 844   If Address is not aligned on a 32-bit boundary, then ASSERT().
 845   If StartBit is greater than 7, then ASSERT().
 846   If EndBit is greater than 7, then ASSERT().
 847   If EndBit is less than StartBit, then ASSERT().
 848
 849   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 850   @param  StartBit  The ordinal of the least significant bit in the bit field.
 851                     The ordinal of the least significant bit in a byte is bit 0.
 852   @param  EndBit    The ordinal of the most significant bit in the bit field.
 853                     The ordinal of the most significant bit in a byte is bit 7.
 854   @param  OrData    The value to OR with the read value from the PCI configuration register.
 855
 856   @return The value written to the PCI configuration register.
 857
 858 **/
 859 UINT32
 860 EFIAPI
 861 PciSegmentBitFieldOr32 (
 862   IN UINT64                    Address,
 863   IN UINTN                     StartBit,
 864   IN UINTN                     EndBit,
 865   IN UINT32                    OrData
 866   );
 867
 868 /**
 869   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR,
 870   and writes the result back to the bit field in the 32-bit port.
 871
 872   Reads the 32-bit PCI configuration register specified by Address,
 873   performs a bitwise inclusive OR between the read result and the value specified by OrData,
 874   and writes the result to the 32-bit PCI configuration register specified by Address.
 875   The value written to the PCI configuration register is returned.
 876   This function must guarantee that all PCI read and write operations are serialized.
 877   Extra left bits in OrData are stripped.
 878
 879   If any reserved bits in Address are set, then ASSERT().
 880   If Address is not aligned on a 32-bit boundary, then ASSERT().
 881   If StartBit is greater than 7, then ASSERT().
 882   If EndBit is greater than 7, then ASSERT().
 883   If EndBit is less than StartBit, then ASSERT().
 884
 885   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 886   @param  StartBit  The ordinal of the least significant bit in the bit field.
 887                     The ordinal of the least significant bit in a byte is bit 0.
 888   @param  EndBit    The ordinal of the most significant bit in the bit field.
 889                     The ordinal of the most significant bit in a byte is bit 7.
 890   @param  AndData   The value to AND with the read value from the PCI configuration register.
 891
 892   @return The value written to the PCI configuration register.
 893
 894 **/
 895 UINT32
 896 EFIAPI
 897 PciSegmentBitFieldAnd32 (
 898   IN UINT64                    Address,
 899   IN UINTN                     StartBit,
 900   IN UINTN                     EndBit,
 901   IN UINT32                    AndData
 902   );
 903
 904 /**
 905   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND,
 906   and writes the result back to the bit field in the 32-bit register.
 907
 908   Reads the 32-bit PCI configuration register specified by Address,
 909   performs a bitwise AND between the read result and the value specified by AndData,
 910   and writes the result to the 32-bit PCI configuration register specified by Address.
 911   The value written to the PCI configuration register is returned.
 912   This function must guarantee that all PCI read and write operations are serialized.
 913   Extra left bits in AndData are stripped.
 914
 915   If any reserved bits in Address are set, then ASSERT().
 916   If Address is not aligned on a 32-bit boundary, then ASSERT().
 917   If StartBit is greater than 7, then ASSERT().
 918   If EndBit is greater than 7, then ASSERT().
 919   If EndBit is less than StartBit, then ASSERT().
 920
 921   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 922   @param  StartBit  The ordinal of the least significant bit in the bit field.
 923                     The ordinal of the least significant bit in a byte is bit 0.
 924   @param  EndBit    The ordinal of the most significant bit in the bit field.
 925                     The ordinal of the most significant bit in a byte is bit 7.
 926   @param  AndData   The value to AND with the read value from the PCI configuration register.
 927   @param  OrData    The value to OR with the read value from the PCI configuration register.
 928
 929   @return The value written to the PCI configuration register.
 930
 931 **/
 932 UINT32
 933 EFIAPI
 934 PciSegmentBitFieldAndThenOr32 (
 935   IN UINT64                    Address,
 936   IN UINTN                     StartBit,
 937   IN UINTN                     EndBit,
 938   IN UINT32                    AndData,
 939   IN UINT32                    OrData
 940   );
 941
 942 /**
 943   Reads a range of PCI configuration registers into a caller supplied buffer.
 944
 945   Reads the range of PCI configuration registers specified by StartAddress
 946   and Size into the buffer specified by Buffer.
 947   This function only allows the PCI configuration registers from a single PCI function to be read.
 948   Size is returned.
 949
 950   If any reserved bits in StartAddress are set, then ASSERT().
 951   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 952   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
 953   If Size > 0 and Buffer is NULL, then ASSERT().
 954
 955   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
 956   @param  Size          Size in bytes of the transfer.
 957   @param  Buffer        Pointer to a buffer receiving the data read.
 958
 959   @return The parameter of Size.
 960
 961 **/
 962 UINTN
 963 EFIAPI
 964 PciSegmentReadBuffer (
 965   IN  UINT64                   StartAddress,
 966   IN  UINTN                    Size,
 967   OUT VOID                     *Buffer
 968   );
 969
 970 /**
 971   Copies the data in a caller supplied buffer to a specified range of PCI configuration space.
 972
 973   Writes the range of PCI configuration registers specified by StartAddress
 974   and Size from the buffer specified by Buffer.
 975   This function only allows the PCI configuration registers from a single PCI function to be written.
 976   Size is returned.
 977
 978   If any reserved bits in StartAddress are set, then ASSERT().
 979   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 980   If (StartAddress + Size - 1)  > 0x0FFFFFFF, then ASSERT().
 981   If Buffer is NULL, then ASSERT().
 982
 983   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device, Function, and Register.
 984   @param  Size          Size in bytes of the transfer.
 985   @param  Buffer        Pointer to a buffer containing the data to write.
 986
 987   @return The parameter of Size.
 988
 989 **/
 990 UINTN
 991 EFIAPI
 992 PciSegmentWriteBuffer (
 993   IN UINT64                    StartAddress,
 994   IN UINTN                     Size,
 995   IN VOID                      *Buffer
 996   );
 997
 998 #endif