2 This file declares PciCfg2 PPI.
4 This ppi Provides platform or chipset-specific access to
5 the PCI configuration space for a specific PCI segment.
7 Copyright (c) 2006 - 2008, Intel Corporation
8 All rights reserved. This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 @par Revision Reference:
17 This PPI is defined in PI
22 #ifndef __PEI_PCI_CFG2_H__
23 #define __PEI_PCI_CFG2_H__
25 #include <Pi/PiPeiCis.h>
27 #define EFI_PEI_PCI_CFG2_PPI_GUID \
28 { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
31 typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI
;
33 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
37 ((reg) < 256 ? (reg) : ((UINT64)(reg) << 32)));
40 /// EFI_PEI_PCI_CFG_PPI_WIDTH
43 EfiPeiPciCfgWidthUint8
= 0,
44 EfiPeiPciCfgWidthUint16
= 1,
45 EfiPeiPciCfgWidthUint32
= 2,
46 EfiPeiPciCfgWidthUint64
= 3,
47 EfiPeiPciCfgWidthMaximum
48 } EFI_PEI_PCI_CFG_PPI_WIDTH
;
51 /// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
55 /// 8-bit register offset within the PCI configuration space for a given device's function
60 /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
65 /// Only the 5 least-significant bits are used to encode one of 32 possible devices.
69 /// 8-bit value to encode between 0 and 255 buses.
73 /// Register number in PCI configuration space. If this field is zero, then Register is used
74 /// for the register number. If this field is non-zero, then Register is ignored and this field
75 /// is used for the register number.
77 UINT32 ExtendedRegister
;
78 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
;
81 Reads from or write to a given location in the PCI configuration space.
83 @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
85 @param This Pointer to local data for the interface.
87 @param Width The width of the access. Enumerated in bytes.
88 See EFI_PEI_PCI_CFG_PPI_WIDTH above.
90 @param Address The physical address of the access. The format of
91 the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
93 @param Buffer A pointer to the buffer of data..
96 @retval EFI_SUCCESS The function completed successfully.
98 @retval EFI_DEVICE_ERROR There was a problem with the transaction.
100 @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this
106 (EFIAPI
*EFI_PEI_PCI_CFG2_PPI_IO
)(
107 IN CONST EFI_PEI_SERVICES
**PeiServices
,
108 IN CONST EFI_PEI_PCI_CFG2_PPI
*This
,
109 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
116 Performs a read-modify-write operation on the contents
117 from a given location in the PCI configuration space.
119 @param PeiServices An indirect pointer to the PEI Services Table
120 published by the PEI Foundation.
122 @param This Pointer to local data for the interface.
124 @param Width The width of the access. Enumerated in bytes. Type
125 EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
127 @param Address The physical address of the access.
129 @param SetBits Points to value to bitwise-OR with the read configuration value.
131 The size of the value is determined by Width.
133 @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.
134 The size of the value is determined by Width.
137 @retval EFI_SUCCESS The function completed successfully.
139 @retval EFI_DEVICE_ERROR There was a problem with the transaction.
141 @retval EFI_DEVICE_NOT_READY The device is not capable of supporting
142 the operation at this time.
147 (EFIAPI
*EFI_PEI_PCI_CFG2_PPI_RW
)(
148 IN CONST EFI_PEI_SERVICES
**PeiServices
,
149 IN CONST EFI_PEI_PCI_CFG2_PPI
*This
,
150 IN EFI_PEI_PCI_CFG_PPI_WIDTH Width
,
157 @par Ppi Description:
158 The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
159 controllers behind a PCI root bridge controller.
161 @param Read PCI read services. See the Read() function description.
163 @param Write PCI write services. See the Write() function description.
165 @param Modify PCI read-modify-write services. See the Modify() function description.
167 @param Segment The PCI bus segment which the specified functions will access.
170 struct _EFI_PEI_PCI_CFG2_PPI
{
171 EFI_PEI_PCI_CFG2_PPI_IO Read
;
172 EFI_PEI_PCI_CFG2_PPI_IO Write
;
173 EFI_PEI_PCI_CFG2_PPI_RW Modify
;
178 extern EFI_GUID gEfiPciCfg2PpiGuid
;