]> git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Include/Uefi/UefiPxe.h
Add media status relative definition to UEFI PXE header file.
[mirror_edk2.git] / MdePkg / Include / Uefi / UefiPxe.h
1 /** @file
2 This header file contains all of the PXE type definitions,
3 structure prototypes, global variables and constants that
4 are needed for porting PXE to EFI.
5
6 Copyright (c) 2006 - 2010, Intel Corporation
7 All rights reserved. This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 @par Revision Reference:
16 32/64-bit PXE specification:
17 alpha-4, 99-Dec-17
18
19 @attention The PXE_OPFLAGS_GET_MEDIA_STATUS and PXE_STATFLAGS_GET_STATUS_NO_MEDIA_xxx
20 are not defined in current UEFI spec (v2.3, approved May, 09), they will be
21 added by following erratas.
22
23 **/
24
25 #ifndef __EFI_PXE_H__
26 #define __EFI_PXE_H__
27
28 #pragma pack(1)
29
30 #define PXE_BUSTYPE(a, b, c, d) \
31 ( \
32 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
33 ((PXE_UINT32) (a) & 0xFF) \
34 )
35
36 ///
37 /// UNDI ROM ID and devive ID signature
38 ///
39 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
40
41 ///
42 /// BUS ROM ID signatures
43 ///
44 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
45 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
46 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
47 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
48
49 #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
50
51 #define PXE_SWAP_UINT32(n) \
52 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
53 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
54 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
55 (((PXE_UINT32)(n) & 0xFF000000) >> 24))
56
57 #define PXE_SWAP_UINT64(n) \
58 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
59 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
60 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
61 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \
62 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \
63 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
64 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
65 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
66
67
68 #define PXE_CPBSIZE_NOT_USED 0 ///< zero
69 #define PXE_DBSIZE_NOT_USED 0 ///< zero
70 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero
71 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero
72 #define PXE_CONST CONST
73
74 #define PXE_VOLATILE volatile
75
76 typedef VOID PXE_VOID;
77 typedef UINT8 PXE_UINT8;
78 typedef UINT16 PXE_UINT16;
79 typedef UINT32 PXE_UINT32;
80 typedef UINTN PXE_UINTN;
81
82 ///
83 /// typedef unsigned long PXE_UINT64;
84 ///
85 typedef UINT64 PXE_UINT64;
86
87 typedef PXE_UINT8 PXE_BOOL;
88 #define PXE_FALSE 0 ///< zero
89 #define PXE_TRUE (!PXE_FALSE)
90
91 typedef PXE_UINT16 PXE_OPCODE;
92
93 ///
94 /// Return UNDI operational state.
95 ///
96 #define PXE_OPCODE_GET_STATE 0x0000
97
98 ///
99 /// Change UNDI operational state from Stopped to Started.
100 ///
101 #define PXE_OPCODE_START 0x0001
102
103 ///
104 /// Change UNDI operational state from Started to Stopped.
105 ///
106 #define PXE_OPCODE_STOP 0x0002
107
108 ///
109 /// Get UNDI initialization information.
110 ///
111 #define PXE_OPCODE_GET_INIT_INFO 0x0003
112
113 ///
114 /// Get NIC configuration information.
115 ///
116 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
117
118 ///
119 /// Changed UNDI operational state from Started to Initialized.
120 ///
121 #define PXE_OPCODE_INITIALIZE 0x0005
122
123 ///
124 /// Re-initialize the NIC H/W.
125 ///
126 #define PXE_OPCODE_RESET 0x0006
127
128 ///
129 /// Change the UNDI operational state from Initialized to Started.
130 ///
131 #define PXE_OPCODE_SHUTDOWN 0x0007
132
133 ///
134 /// Read & change state of external interrupt enables.
135 ///
136 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
137
138 ///
139 /// Read & change state of packet receive filters.
140 ///
141 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
142
143 ///
144 /// Read & change station MAC address.
145 ///
146 #define PXE_OPCODE_STATION_ADDRESS 0x000A
147
148 ///
149 /// Read traffic statistics.
150 ///
151 #define PXE_OPCODE_STATISTICS 0x000B
152
153 ///
154 /// Convert multicast IP address to multicast MAC address.
155 ///
156 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
157
158 ///
159 /// Read or change non-volatile storage on the NIC.
160 ///
161 #define PXE_OPCODE_NVDATA 0x000D
162
163 ///
164 /// Get & clear interrupt status.
165 ///
166 #define PXE_OPCODE_GET_STATUS 0x000E
167
168 ///
169 /// Fill media header in packet for transmit.
170 ///
171 #define PXE_OPCODE_FILL_HEADER 0x000F
172
173 ///
174 /// Transmit packet(s).
175 ///
176 #define PXE_OPCODE_TRANSMIT 0x0010
177
178 ///
179 /// Receive packet.
180 ///
181 #define PXE_OPCODE_RECEIVE 0x0011
182
183 ///
184 /// Last valid PXE UNDI OpCode number.
185 ///
186 #define PXE_OPCODE_LAST_VALID 0x0011
187
188 typedef PXE_UINT16 PXE_OPFLAGS;
189
190 #define PXE_OPFLAGS_NOT_USED 0x0000
191
192 //
193 // //////////////////////////////////////
194 // UNDI Get State
195 //
196 // No OpFlags
197
198 ////////////////////////////////////////
199 // UNDI Start
200 //
201 // No OpFlags
202
203 ////////////////////////////////////////
204 // UNDI Stop
205 //
206 // No OpFlags
207
208 ////////////////////////////////////////
209 // UNDI Get Init Info
210 //
211 // No Opflags
212
213 ////////////////////////////////////////
214 // UNDI Get Config Info
215 //
216 // No Opflags
217
218 ///
219 /// UNDI Initialize
220 ///
221 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
222 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
223 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
224
225 ///
226 ///
227 /// UNDI Reset
228 ///
229 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
230 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
231
232 ///
233 /// UNDI Shutdown
234 ///
235 /// No OpFlags
236
237 ///
238 /// UNDI Interrupt Enables
239 ///
240 ///
241 /// Select whether to enable or disable external interrupt signals.
242 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
243 ///
244 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
245 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
246 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
247 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
248
249 ///
250 /// Enable receive interrupts. An external interrupt will be generated
251 /// after a complete non-error packet has been received.
252 ///
253 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
254
255 ///
256 /// Enable transmit interrupts. An external interrupt will be generated
257 /// after a complete non-error packet has been transmitted.
258 ///
259 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
260
261 ///
262 /// Enable command interrupts. An external interrupt will be generated
263 /// when command execution stops.
264 ///
265 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
266
267 ///
268 /// Generate software interrupt. Setting this bit generates an external
269 /// interrupt, if it is supported by the hardware.
270 ///
271 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
272
273 ///
274 /// UNDI Receive Filters
275 ///
276 ///
277 /// Select whether to enable or disable receive filters.
278 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
279 ///
280 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
281 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
282 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
283 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
284
285 ///
286 /// To reset the contents of the multicast MAC address filter list,
287 /// set this OpFlag:
288 ///
289 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
290
291 ///
292 /// Enable unicast packet receiving. Packets sent to the current station
293 /// MAC address will be received.
294 ///
295 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
296
297 ///
298 /// Enable broadcast packet receiving. Packets sent to the broadcast
299 /// MAC address will be received.
300 ///
301 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
302
303 ///
304 /// Enable filtered multicast packet receiving. Packets sent to any
305 /// of the multicast MAC addresses in the multicast MAC address filter
306 /// list will be received. If the filter list is empty, no multicast
307 ///
308 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
309
310 ///
311 /// Enable promiscuous packet receiving. All packets will be received.
312 ///
313 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
314
315 ///
316 /// Enable promiscuous multicast packet receiving. All multicast
317 /// packets will be received.
318 ///
319 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
320
321 ///
322 /// UNDI Station Address
323 ///
324 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
325 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
326 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
327
328 ///
329 /// UNDI Statistics
330 ///
331 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
332 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
333
334 ///
335 /// UNDI MCast IP to MAC
336 ///
337 ///
338 /// Identify the type of IP address in the CPB.
339 ///
340 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
341 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
342 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
343
344 ///
345 /// UNDI NvData
346 ///
347 ///
348 /// Select the type of non-volatile data operation.
349 ///
350 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
351 #define PXE_OPFLAGS_NVDATA_READ 0x0000
352 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
353
354 ///
355 /// UNDI Get Status
356 ///
357 ///
358 /// Return current interrupt status. This will also clear any interrupts
359 /// that are currently set. This can be used in a polling routine. The
360 /// interrupt flags are still set and cleared even when the interrupts
361 /// are disabled.
362 ///
363 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
364
365 ///
366 /// Return list of transmitted buffers for recycling. Transmit buffers
367 /// must not be changed or unallocated until they have recycled. After
368 /// issuing a transmit command, wait for a transmit complete interrupt.
369 /// When a transmit complete interrupt is received, read the transmitted
370 /// buffers. Do not plan on getting one buffer per interrupt. Some
371 /// NICs and UNDIs may transmit multiple buffers per interrupt.
372 ///
373 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
374
375 ///
376 /// Return current media status.
377 ///
378 #define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004
379
380 ///
381 /// UNDI Fill Header
382 ///
383 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
384 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
385 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
386
387 ///
388 /// UNDI Transmit
389 ///
390 ///
391 /// S/W UNDI only. Return after the packet has been transmitted. A
392 /// transmit complete interrupt will still be generated and the transmit
393 /// buffer will have to be recycled.
394 ///
395 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
396 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
397 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
398
399 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
400 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
401 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
402
403 ///
404 /// UNDI Receive
405 ///
406 /// No OpFlags
407 ///
408
409 ///
410 /// PXE STATFLAGS
411 ///
412 typedef PXE_UINT16 PXE_STATFLAGS;
413
414 #define PXE_STATFLAGS_INITIALIZE 0x0000
415
416 ///
417 /// Common StatFlags that can be returned by all commands.
418 ///
419 ///
420 /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
421 /// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
422 /// that support command queuing.
423 ///
424 #define PXE_STATFLAGS_STATUS_MASK 0xC000
425 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
426 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
427 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
428
429 ///
430 /// UNDI Get State
431 ///
432 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
433 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
434 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
435 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
436
437 ///
438 /// UNDI Start
439 ///
440 /// No additional StatFlags
441 ///
442
443 ///
444 /// UNDI Get Init Info
445 ///
446 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
447 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
448 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
449
450 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002
451 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000
452 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002
453
454 ///
455 /// UNDI Initialize
456 ///
457 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
458
459 ///
460 /// UNDI Reset
461 ///
462 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
463
464 ///
465 /// UNDI Shutdown
466 ///
467 /// No additional StatFlags
468
469 ///
470 /// UNDI Interrupt Enables
471 ///
472 ///
473 /// If set, receive interrupts are enabled.
474 ///
475 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
476
477 ///
478 /// If set, transmit interrupts are enabled.
479 ///
480 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
481
482 ///
483 /// If set, command interrupts are enabled.
484 ///
485 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
486
487 ///
488 /// UNDI Receive Filters
489 ///
490
491 ///
492 /// If set, unicast packets will be received.
493 ///
494 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
495
496 ///
497 /// If set, broadcast packets will be received.
498 ///
499 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
500
501 ///
502 /// If set, multicast packets that match up with the multicast address
503 /// filter list will be received.
504 ///
505 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
506
507 ///
508 /// If set, all packets will be received.
509 ///
510 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
511
512 ///
513 /// If set, all multicast packets will be received.
514 ///
515 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
516
517 ///
518 /// UNDI Station Address
519 ///
520 /// No additional StatFlags
521 ///
522
523 ///
524 /// UNDI Statistics
525 ///
526 /// No additional StatFlags
527 ///
528
529 ///
530 //// UNDI MCast IP to MAC
531 ////
532 //// No additional StatFlags
533
534 ///
535 /// UNDI NvData
536 ///
537 /// No additional StatFlags
538 ///
539
540 ///
541 /// UNDI Get Status
542 ///
543
544 ///
545 /// Use to determine if an interrupt has occurred.
546 ///
547 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
548 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
549
550 ///
551 /// If set, at least one receive interrupt occurred.
552 ///
553 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
554
555 ///
556 /// If set, at least one transmit interrupt occurred.
557 ///
558 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
559
560 ///
561 /// If set, at least one command interrupt occurred.
562 ///
563 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
564
565 ///
566 /// If set, at least one software interrupt occurred.
567 ///
568 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
569
570 ///
571 /// This flag is set if the transmitted buffer queue is empty. This flag
572 /// will be set if all transmitted buffer addresses get written into the DB.
573 ///
574 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
575
576 ///
577 /// This flag is set if no transmitted buffer addresses were written
578 /// into the DB. (This could be because DBsize was too small.)
579 ///
580 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
581
582 ///
583 /// This flag is set if there is no media detected.
584 ///
585 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040
586
587 ///
588 /// UNDI Fill Header
589 ///
590 /// No additional StatFlags
591 ///
592
593 ///
594 /// UNDI Transmit
595 ///
596 /// No additional StatFlags.
597
598 ///
599 /// UNDI Receive
600 ///
601
602 ///
603 /// No additional StatFlags.
604 ///
605 typedef PXE_UINT16 PXE_STATCODE;
606
607 #define PXE_STATCODE_INITIALIZE 0x0000
608
609 ///
610 /// Common StatCodes returned by all UNDI commands, UNDI protocol functions
611 /// and BC protocol functions.
612 ///
613 #define PXE_STATCODE_SUCCESS 0x0000
614
615 #define PXE_STATCODE_INVALID_CDB 0x0001
616 #define PXE_STATCODE_INVALID_CPB 0x0002
617 #define PXE_STATCODE_BUSY 0x0003
618 #define PXE_STATCODE_QUEUE_FULL 0x0004
619 #define PXE_STATCODE_ALREADY_STARTED 0x0005
620 #define PXE_STATCODE_NOT_STARTED 0x0006
621 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
622 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
623 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
624 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
625 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
626 #define PXE_STATCODE_UNSUPPORTED 0x000C
627 #define PXE_STATCODE_BUFFER_FULL 0x000D
628 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
629 #define PXE_STATCODE_INVALID_UNDI 0x000F
630 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
631 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
632 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
633 #define PXE_STATCODE_NO_DATA 0x0013
634
635 typedef PXE_UINT16 PXE_IFNUM;
636
637 ///
638 /// This interface number must be passed to the S/W UNDI Start command.
639 ///
640 #define PXE_IFNUM_START 0x0000
641
642 ///
643 /// This interface number is returned by the S/W UNDI Get State and
644 /// Start commands if information in the CDB, CPB or DB is invalid.
645 ///
646 #define PXE_IFNUM_INVALID 0x0000
647
648 typedef PXE_UINT16 PXE_CONTROL;
649
650 ///
651 /// Setting this flag directs the UNDI to queue this command for later
652 /// execution if the UNDI is busy and it supports command queuing.
653 /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
654 /// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
655 /// error is returned.
656 ///
657 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
658
659 ///
660 /// These two bit values are used to determine if there are more UNDI
661 /// CDB structures following this one. If the link bit is set, there
662 /// must be a CDB structure following this one. Execution will start
663 /// on the next CDB structure as soon as this one completes successfully.
664 /// If an error is generated by this command, execution will stop.
665 ///
666 #define PXE_CONTROL_LINK 0x0001
667 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
668
669 typedef PXE_UINT8 PXE_FRAME_TYPE;
670
671 #define PXE_FRAME_TYPE_NONE 0x00
672 #define PXE_FRAME_TYPE_UNICAST 0x01
673 #define PXE_FRAME_TYPE_BROADCAST 0x02
674 #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
675 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
676 #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
677
678 #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST
679
680 typedef PXE_UINT32 PXE_IPV4;
681
682 typedef PXE_UINT32 PXE_IPV6[4];
683 #define PXE_MAC_LENGTH 32
684
685 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
686
687 typedef PXE_UINT8 PXE_IFTYPE;
688 typedef UINT16 PXE_MEDIA_PROTOCOL;
689
690 ///
691 /// This information is from the ARP section of RFC 1700.
692 ///
693 /// 1 Ethernet (10Mb) [JBP]
694 /// 2 Experimental Ethernet (3Mb) [JBP]
695 /// 3 Amateur Radio AX.25 [PXK]
696 /// 4 Proteon ProNET Token Ring [JBP]
697 /// 5 Chaos [GXP]
698 /// 6 IEEE 802 Networks [JBP]
699 /// 7 ARCNET [JBP]
700 /// 8 Hyperchannel [JBP]
701 /// 9 Lanstar [TU]
702 /// 10 Autonet Short Address [MXB1]
703 /// 11 LocalTalk [JKR1]
704 /// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
705 /// 13 Ultra link [RXD2]
706 /// 14 SMDS [GXC1]
707 /// 15 Frame Relay [AGM]
708 /// 16 Asynchronous Transmission Mode (ATM) [JXB2]
709 /// 17 HDLC [JBP]
710 /// 18 Fibre Channel [Yakov Rekhter]
711 /// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
712 /// 20 Serial Line [JBP]
713 /// 21 Asynchronous Transmission Mode (ATM) [MXB1]
714 ///
715 /// * Other names and brands may be claimed as the property of others.
716 ///
717 #define PXE_IFTYPE_ETHERNET 0x01
718 #define PXE_IFTYPE_TOKENRING 0x04
719 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
720
721 typedef struct s_pxe_hw_undi {
722 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE
723 PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI)
724 PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero
725 PXE_UINT8 Rev; ///< PXE_ROMID_REV
726 PXE_UINT8 IFcnt; ///< physical connector count
727 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER
728 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER
729 PXE_UINT16 reserved; ///< zero, not used
730 PXE_UINT32 Implementation; ///< implementation flags
731 ///< reserved ///< vendor use
732 ///< UINT32 Status; ///< status port
733 ///< UINT32 Command; ///< command port
734 ///< UINT64 CDBaddr; ///< CDB address port
735 ///<
736 } PXE_HW_UNDI;
737
738 ///
739 /// Status port bit definitions
740 ///
741
742 ///
743 /// UNDI operation state
744 ///
745 #define PXE_HWSTAT_STATE_MASK 0xC0000000
746 #define PXE_HWSTAT_BUSY 0xC0000000
747 #define PXE_HWSTAT_INITIALIZED 0x80000000
748 #define PXE_HWSTAT_STARTED 0x40000000
749 #define PXE_HWSTAT_STOPPED 0x00000000
750
751 ///
752 /// If set, last command failed
753 ///
754 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
755
756 ///
757 /// If set, identifies enabled receive filters
758 ///
759 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
760 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
761 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
762 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
763 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
764
765 ///
766 /// If set, identifies enabled external interrupts
767 ///
768 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
769 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
770 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
771 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
772
773 ///
774 /// If set, identifies pending interrupts
775 ///
776 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
777 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
778 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
779 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
780
781 ///
782 /// Command port definitions
783 ///
784
785 ///
786 /// If set, CDB identified in CDBaddr port is given to UNDI.
787 /// If not set, other bits in this word will be processed.
788 ///
789 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
790 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
791
792 ///
793 /// Use these to enable/disable receive filters.
794 ///
795 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
796 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
797 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
798 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
799 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
800
801 ///
802 /// Use these to enable/disable external interrupts
803 ///
804 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
805 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
806 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
807 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
808
809 ///
810 /// Use these to clear pending external interrupts
811 ///
812 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
813 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
814 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
815 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
816
817 typedef struct s_pxe_sw_undi {
818 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE
819 PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI)
820 PXE_UINT8 Fudge; ///< makes 8-bit cksum zero
821 PXE_UINT8 Rev; ///< PXE_ROMID_REV
822 PXE_UINT8 IFcnt; ///< physical connector count
823 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER
824 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER
825 PXE_UINT16 reserved1; ///< zero, not used
826 PXE_UINT32 Implementation; ///< Implementation flags
827 PXE_UINT64 EntryPoint; ///< API entry point
828 PXE_UINT8 reserved2[3]; ///< zero, not used
829 PXE_UINT8 BusCnt; ///< number of bustypes supported
830 PXE_UINT32 BusType[1]; ///< list of supported bustypes
831 } PXE_SW_UNDI;
832
833 typedef union u_pxe_undi {
834 PXE_HW_UNDI hw;
835 PXE_SW_UNDI sw;
836 } PXE_UNDI;
837
838 ///
839 /// Signature of !PXE structure
840 ///
841 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
842
843 ///
844 /// !PXE structure format revision
845 ///
846 #define PXE_ROMID_REV 0x02
847
848 ///
849 /// UNDI command interface revision. These are the values that get sent
850 /// in option 94 (Client Network Interface Identifier) in the DHCP Discover
851 /// and PXE Boot Server Request packets.
852 ///
853 #define PXE_ROMID_MAJORVER 0x03
854 #define PXE_ROMID_MINORVER 0x01
855
856 ///
857 /// Implementation flags
858 ///
859 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
860 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
861 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
862 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
863 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
864 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
865 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
866 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
867 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
868 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
869 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
870 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
871 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
872 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
873 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
874 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
875 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
876 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
877 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
878 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
879 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
880 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
881
882 typedef struct s_pxe_cdb {
883 PXE_OPCODE OpCode;
884 PXE_OPFLAGS OpFlags;
885 PXE_UINT16 CPBsize;
886 PXE_UINT16 DBsize;
887 PXE_UINT64 CPBaddr;
888 PXE_UINT64 DBaddr;
889 PXE_STATCODE StatCode;
890 PXE_STATFLAGS StatFlags;
891 PXE_UINT16 IFnum;
892 PXE_CONTROL Control;
893 } PXE_CDB;
894
895 typedef union u_pxe_ip_addr {
896 PXE_IPV6 IPv6;
897 PXE_IPV4 IPv4;
898 } PXE_IP_ADDR;
899
900 typedef union pxe_device {
901 ///
902 /// PCI and PC Card NICs are both identified using bus, device
903 /// and function numbers. For PC Card, this may require PC
904 /// Card services to be loaded in the BIOS or preboot
905 /// environment.
906 ///
907 struct {
908 ///
909 /// See S/W UNDI ROMID structure definition for PCI and
910 /// PCC BusType definitions.
911 ///
912 PXE_UINT32 BusType;
913
914 ///
915 /// Bus, device & function numbers that locate this device.
916 ///
917 PXE_UINT16 Bus;
918 PXE_UINT8 Device;
919 PXE_UINT8 Function;
920 }
921 PCI, PCC;
922
923 } PXE_DEVICE;
924
925 ///
926 /// cpb and db definitions
927 ///
928 #define MAX_PCI_CONFIG_LEN 64 ///< # of dwords
929 #define MAX_EEPROM_LEN 128 ///< # of dwords
930 #define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done
931 #define MAX_MCAST_ADDRESS_CNT 8
932
933 typedef struct s_pxe_cpb_start_30 {
934 ///
935 /// PXE_VOID Delay(UINTN microseconds);
936 ///
937 /// UNDI will never request a delay smaller than 10 microseconds
938 /// and will always request delays in increments of 10 microseconds.
939 /// The Delay() CallBack routine must delay between n and n + 10
940 /// microseconds before returning control to the UNDI.
941 ///
942 /// This field cannot be set to zero.
943 ///
944 UINT64 Delay;
945
946 ///
947 /// PXE_VOID Block(UINT32 enable);
948 ///
949 /// UNDI may need to block multi-threaded/multi-processor access to
950 /// critical code sections when programming or accessing the network
951 /// device. To this end, a blocking service is needed by the UNDI.
952 /// When UNDI needs a block, it will call Block() passing a non-zero
953 /// value. When UNDI no longer needs a block, it will call Block()
954 /// with a zero value. When called, if the Block() is already enabled,
955 /// do not return control to the UNDI until the previous Block() is
956 /// disabled.
957 ///
958 /// This field cannot be set to zero.
959 ///
960 UINT64 Block;
961
962 ///
963 /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
964 ///
965 /// UNDI will pass the virtual address of a buffer and the virtual
966 /// address of a 64-bit physical buffer. Convert the virtual address
967 /// to a physical address and write the result to the physical address
968 /// buffer. If virtual and physical addresses are the same, just
969 /// copy the virtual address to the physical address buffer.
970 ///
971 /// This field can be set to zero if virtual and physical addresses
972 /// are equal.
973 ///
974 UINT64 Virt2Phys;
975 ///
976 /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
977 /// UINT64 buf_addr);
978 ///
979 /// UNDI will read or write the device io space using this call back
980 /// function. It passes the number of bytes as the len parameter and it
981 /// will be either 1,2,4 or 8.
982 ///
983 /// This field can not be set to zero.
984 ///
985 UINT64 Mem_IO;
986 } PXE_CPB_START_30;
987
988 typedef struct s_pxe_cpb_start_31 {
989 ///
990 /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
991 ///
992 /// UNDI will never request a delay smaller than 10 microseconds
993 /// and will always request delays in increments of 10 microseconds.
994 /// The Delay() CallBack routine must delay between n and n + 10
995 /// microseconds before returning control to the UNDI.
996 ///
997 /// This field cannot be set to zero.
998 ///
999 UINT64 Delay;
1000
1001 ///
1002 /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);
1003 ///
1004 /// UNDI may need to block multi-threaded/multi-processor access to
1005 /// critical code sections when programming or accessing the network
1006 /// device. To this end, a blocking service is needed by the UNDI.
1007 /// When UNDI needs a block, it will call Block() passing a non-zero
1008 /// value. When UNDI no longer needs a block, it will call Block()
1009 /// with a zero value. When called, if the Block() is already enabled,
1010 /// do not return control to the UNDI until the previous Block() is
1011 /// disabled.
1012 ///
1013 /// This field cannot be set to zero.
1014 ///
1015 UINT64 Block;
1016
1017 ///
1018 /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1019 ///
1020 /// UNDI will pass the virtual address of a buffer and the virtual
1021 /// address of a 64-bit physical buffer. Convert the virtual address
1022 /// to a physical address and write the result to the physical address
1023 /// buffer. If virtual and physical addresses are the same, just
1024 /// copy the virtual address to the physical address buffer.
1025 ///
1026 /// This field can be set to zero if virtual and physical addresses
1027 /// are equal.
1028 ///
1029 UINT64 Virt2Phys;
1030 ///
1031 /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1032 /// UINT64 buf_addr);
1033 ///
1034 /// UNDI will read or write the device io space using this call back
1035 /// function. It passes the number of bytes as the len parameter and it
1036 /// will be either 1,2,4 or 8.
1037 ///
1038 /// This field can not be set to zero.
1039 ///
1040 UINT64 Mem_IO;
1041 ///
1042 /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1043 /// UINT32 Direction, UINT64 mapped_addr);
1044 ///
1045 /// UNDI will pass the virtual address of a buffer, direction of the data
1046 /// flow from/to the mapped buffer (the constants are defined below)
1047 /// and a place holder (pointer) for the mapped address.
1048 /// This call will Map the given address to a physical DMA address and write
1049 /// the result to the mapped_addr pointer. If there is no need to
1050 /// map the given address to a lower address (i.e. the given address is
1051 /// associated with a physical address that is already compatible to be
1052 /// used with the DMA, it converts the given virtual address to it's
1053 /// physical address and write that in the mapped address pointer.
1054 ///
1055 /// This field can be set to zero if there is no mapping service available
1056 ///
1057 UINT64 Map_Mem;
1058
1059 ///
1060 /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1061 /// UINT32 Direction, UINT64 mapped_addr);
1062 ///
1063 /// UNDI will pass the virtual and mapped addresses of a buffer
1064 /// This call will un map the given address
1065 ///
1066 /// This field can be set to zero if there is no unmapping service available
1067 ///
1068 UINT64 UnMap_Mem;
1069
1070 ///
1071 /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1072 /// UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1073 ///
1074 /// UNDI will pass the virtual and mapped addresses of a buffer
1075 /// This call will synchronize the contents of both the virtual and mapped
1076 /// buffers for the given Direction.
1077 ///
1078 /// This field can be set to zero if there is no service available
1079 ///
1080 UINT64 Sync_Mem;
1081
1082 ///
1083 /// protocol driver can provide anything for this Unique_ID, UNDI remembers
1084 /// that as just a 64bit value assocaited to the interface specified by
1085 /// the ifnum and gives it back as a parameter to all the call-back routines
1086 /// when calling for that interface!
1087 ///
1088 UINT64 Unique_ID;
1089 } PXE_CPB_START_31;
1090
1091 #define TO_AND_FROM_DEVICE 0
1092 #define FROM_DEVICE 1
1093 #define TO_DEVICE 2
1094
1095 #define PXE_DELAY_MILLISECOND 1000
1096 #define PXE_DELAY_SECOND 1000000
1097 #define PXE_IO_READ 0
1098 #define PXE_IO_WRITE 1
1099 #define PXE_MEM_READ 2
1100 #define PXE_MEM_WRITE 4
1101
1102 typedef struct s_pxe_db_get_init_info {
1103 ///
1104 /// Minimum length of locked memory buffer that must be given to
1105 /// the Initialize command. Giving UNDI more memory will generally
1106 /// give better performance.
1107 ///
1108 /// If MemoryRequired is zero, the UNDI does not need and will not
1109 /// use system memory to receive and transmit packets.
1110 ///
1111 PXE_UINT32 MemoryRequired;
1112
1113 ///
1114 /// Maximum frame data length for Tx/Rx excluding the media header.
1115 ///
1116 PXE_UINT32 FrameDataLen;
1117
1118 ///
1119 /// Supported link speeds are in units of mega bits. Common ethernet
1120 /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
1121 /// filled.
1122 ///
1123 PXE_UINT32 LinkSpeeds[4];
1124
1125 ///
1126 /// Number of non-volatile storage items.
1127 ///
1128 PXE_UINT32 NvCount;
1129
1130 ///
1131 /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4
1132 ///
1133 PXE_UINT16 NvWidth;
1134
1135 ///
1136 /// Media header length. This is the typical media header length for
1137 /// this UNDI. This information is needed when allocating receive
1138 /// and transmit buffers.
1139 ///
1140 PXE_UINT16 MediaHeaderLen;
1141
1142 ///
1143 /// Number of bytes in the NIC hardware (MAC) address.
1144 ///
1145 PXE_UINT16 HWaddrLen;
1146
1147 ///
1148 /// Maximum number of multicast MAC addresses in the multicast
1149 /// MAC address filter list.
1150 ///
1151 PXE_UINT16 MCastFilterCnt;
1152
1153 ///
1154 /// Default number and size of transmit and receive buffers that will
1155 /// be allocated by the UNDI. If MemoryRequired is non-zero, this
1156 /// allocation will come out of the memory buffer given to the Initialize
1157 /// command. If MemoryRequired is zero, this allocation will come out of
1158 /// memory on the NIC.
1159 ///
1160 PXE_UINT16 TxBufCnt;
1161 PXE_UINT16 TxBufSize;
1162 PXE_UINT16 RxBufCnt;
1163 PXE_UINT16 RxBufSize;
1164
1165 ///
1166 /// Hardware interface types defined in the Assigned Numbers RFC
1167 /// and used in DHCP and ARP packets.
1168 /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1169 ///
1170 PXE_UINT8 IFtype;
1171
1172 ///
1173 /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
1174 ///
1175 PXE_UINT8 SupportedDuplexModes;
1176
1177 ///
1178 /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
1179 ///
1180 PXE_UINT8 SupportedLoopBackModes;
1181 } PXE_DB_GET_INIT_INFO;
1182
1183 #define PXE_MAX_TXRX_UNIT_ETHER 1500
1184
1185 #define PXE_HWADDR_LEN_ETHER 0x0006
1186 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
1187
1188 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1189 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1190
1191 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1192 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1193
1194 typedef struct s_pxe_pci_config_info {
1195 ///
1196 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1197 /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1198 ///
1199 UINT32 BusType;
1200
1201 ///
1202 /// This identifies the PCI network device that this UNDI interface
1203 /// is bound to.
1204 ///
1205 UINT16 Bus;
1206 UINT8 Device;
1207 UINT8 Function;
1208
1209 ///
1210 /// This is a copy of the PCI configuration space for this
1211 /// network device.
1212 ///
1213 union {
1214 UINT8 Byte[256];
1215 UINT16 Word[128];
1216 UINT32 Dword[64];
1217 } Config;
1218 } PXE_PCI_CONFIG_INFO;
1219
1220 typedef struct s_pxe_pcc_config_info {
1221 ///
1222 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1223 /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1224 ///
1225 PXE_UINT32 BusType;
1226
1227 ///
1228 /// This identifies the PCC network device that this UNDI interface
1229 /// is bound to.
1230 ///
1231 PXE_UINT16 Bus;
1232 PXE_UINT8 Device;
1233 PXE_UINT8 Function;
1234
1235 ///
1236 /// This is a copy of the PCC configuration space for this
1237 /// network device.
1238 ///
1239 union {
1240 PXE_UINT8 Byte[256];
1241 PXE_UINT16 Word[128];
1242 PXE_UINT32 Dword[64];
1243 } Config;
1244 } PXE_PCC_CONFIG_INFO;
1245
1246 typedef union u_pxe_db_get_config_info {
1247 PXE_PCI_CONFIG_INFO pci;
1248 PXE_PCC_CONFIG_INFO pcc;
1249 } PXE_DB_GET_CONFIG_INFO;
1250
1251 typedef struct s_pxe_cpb_initialize {
1252 ///
1253 /// Address of first (lowest) byte of the memory buffer. This buffer must
1254 /// be in contiguous physical memory and cannot be swapped out. The UNDI
1255 /// will be using this for transmit and receive buffering.
1256 ///
1257 PXE_UINT64 MemoryAddr;
1258
1259 ///
1260 /// MemoryLength must be greater than or equal to MemoryRequired
1261 /// returned by the Get Init Info command.
1262 ///
1263 PXE_UINT32 MemoryLength;
1264
1265 ///
1266 /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100
1267 /// and 1000. Setting a value of zero will auto-detect and/or use the
1268 /// default link speed (operation depends on UNDI/NIC functionality).
1269 ///
1270 PXE_UINT32 LinkSpeed;
1271
1272 ///
1273 /// Suggested number and size of receive and transmit buffers to
1274 /// allocate. If MemoryAddr and MemoryLength are non-zero, this
1275 /// allocation comes out of the supplied memory buffer. If MemoryAddr
1276 /// and MemoryLength are zero, this allocation comes out of memory
1277 /// on the NIC.
1278 ///
1279 /// If these fields are set to zero, the UNDI will allocate buffer
1280 /// counts and sizes as it sees fit.
1281 ///
1282 PXE_UINT16 TxBufCnt;
1283 PXE_UINT16 TxBufSize;
1284 PXE_UINT16 RxBufCnt;
1285 PXE_UINT16 RxBufSize;
1286
1287 ///
1288 /// The following configuration parameters are optional and must be zero
1289 /// to use the default values.
1290 ///
1291 PXE_UINT8 DuplexMode;
1292
1293 PXE_UINT8 LoopBackMode;
1294 } PXE_CPB_INITIALIZE;
1295
1296 #define PXE_DUPLEX_DEFAULT 0x00
1297 #define PXE_FORCE_FULL_DUPLEX 0x01
1298 #define PXE_ENABLE_FULL_DUPLEX 0x02
1299 #define PXE_FORCE_HALF_DUPLEX 0x04
1300 #define PXE_DISABLE_FULL_DUPLEX 0x08
1301
1302 #define LOOPBACK_NORMAL 0
1303 #define LOOPBACK_INTERNAL 1
1304 #define LOOPBACK_EXTERNAL 2
1305
1306 typedef struct s_pxe_db_initialize {
1307 ///
1308 /// Actual amount of memory used from the supplied memory buffer. This
1309 /// may be less that the amount of memory suppllied and may be zero if
1310 /// the UNDI and network device do not use external memory buffers.
1311 ///
1312 /// Memory used by the UNDI and network device is allocated from the
1313 /// lowest memory buffer address.
1314 ///
1315 PXE_UINT32 MemoryUsed;
1316
1317 ///
1318 /// Actual number and size of receive and transmit buffers that were
1319 /// allocated.
1320 ///
1321 PXE_UINT16 TxBufCnt;
1322 PXE_UINT16 TxBufSize;
1323 PXE_UINT16 RxBufCnt;
1324 PXE_UINT16 RxBufSize;
1325 } PXE_DB_INITIALIZE;
1326
1327 typedef struct s_pxe_cpb_receive_filters {
1328 ///
1329 /// List of multicast MAC addresses. This list, if present, will
1330 /// replace the existing multicast MAC address filter list.
1331 ///
1332 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1333 } PXE_CPB_RECEIVE_FILTERS;
1334
1335 typedef struct s_pxe_db_receive_filters {
1336 ///
1337 /// Filtered multicast MAC address list.
1338 ///
1339 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1340 } PXE_DB_RECEIVE_FILTERS;
1341
1342 typedef struct s_pxe_cpb_station_address {
1343 ///
1344 /// If supplied and supported, the current station MAC address
1345 /// will be changed.
1346 ///
1347 PXE_MAC_ADDR StationAddr;
1348 } PXE_CPB_STATION_ADDRESS;
1349
1350 typedef struct s_pxe_dpb_station_address {
1351 ///
1352 /// Current station MAC address.
1353 ///
1354 PXE_MAC_ADDR StationAddr;
1355
1356 ///
1357 /// Station broadcast MAC address.
1358 ///
1359 PXE_MAC_ADDR BroadcastAddr;
1360
1361 ///
1362 /// Permanent station MAC address.
1363 ///
1364 PXE_MAC_ADDR PermanentAddr;
1365 } PXE_DB_STATION_ADDRESS;
1366
1367 typedef struct s_pxe_db_statistics {
1368 ///
1369 /// Bit field identifying what statistic data is collected by the
1370 /// UNDI/NIC.
1371 /// If bit 0x00 is set, Data[0x00] is collected.
1372 /// If bit 0x01 is set, Data[0x01] is collected.
1373 /// If bit 0x20 is set, Data[0x20] is collected.
1374 /// If bit 0x21 is set, Data[0x21] is collected.
1375 /// Etc.
1376 ///
1377 PXE_UINT64 Supported;
1378
1379 ///
1380 /// Statistic data.
1381 ///
1382 PXE_UINT64 Data[64];
1383 } PXE_DB_STATISTICS;
1384
1385 ///
1386 /// Total number of frames received. Includes frames with errors and
1387 /// dropped frames.
1388 ///
1389 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1390
1391 ///
1392 /// Number of valid frames received and copied into receive buffers.
1393 ///
1394 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1395
1396 ///
1397 /// Number of frames below the minimum length for the media.
1398 /// This would be <64 for ethernet.
1399 ///
1400 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1401
1402 ///
1403 /// Number of frames longer than the maxminum length for the
1404 /// media. This would be >1500 for ethernet.
1405 ///
1406 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1407
1408 ///
1409 /// Valid frames that were dropped because receive buffers were full.
1410 ///
1411 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1412
1413 ///
1414 /// Number of valid unicast frames received and not dropped.
1415 ///
1416 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1417
1418 ///
1419 /// Number of valid broadcast frames received and not dropped.
1420 ///
1421 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1422
1423 ///
1424 /// Number of valid mutlicast frames received and not dropped.
1425 ///
1426 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1427
1428 ///
1429 /// Number of frames w/ CRC or alignment errors.
1430 ///
1431 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1432
1433 ///
1434 /// Total number of bytes received. Includes frames with errors
1435 /// and dropped frames.
1436 ///
1437 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1438
1439 ///
1440 /// Transmit statistics.
1441 ///
1442 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1443 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1444 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1445 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1446 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1447 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1448 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1449 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1450 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1451 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1452
1453 ///
1454 /// Number of collisions detection on this subnet.
1455 ///
1456 #define PXE_STATISTICS_COLLISIONS 0x14
1457
1458 ///
1459 /// Number of frames destined for unsupported protocol.
1460 ///
1461 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1462
1463 typedef struct s_pxe_cpb_mcast_ip_to_mac {
1464 ///
1465 /// Multicast IP address to be converted to multicast MAC address.
1466 ///
1467 PXE_IP_ADDR IP;
1468 } PXE_CPB_MCAST_IP_TO_MAC;
1469
1470 typedef struct s_pxe_db_mcast_ip_to_mac {
1471 ///
1472 /// Multicast MAC address.
1473 ///
1474 PXE_MAC_ADDR MAC;
1475 } PXE_DB_MCAST_IP_TO_MAC;
1476
1477 typedef struct s_pxe_cpb_nvdata_sparse {
1478 ///
1479 /// NvData item list. Only items in this list will be updated.
1480 ///
1481 struct {
1482 ///
1483 /// Non-volatile storage address to be changed.
1484 ///
1485 PXE_UINT32 Addr;
1486
1487 ///
1488 /// Data item to write into above storage address.
1489 ///
1490 union {
1491 PXE_UINT8 Byte;
1492 PXE_UINT16 Word;
1493 PXE_UINT32 Dword;
1494 } Data;
1495 } Item[MAX_EEPROM_LEN];
1496 } PXE_CPB_NVDATA_SPARSE;
1497
1498 ///
1499 /// When using bulk update, the size of the CPB structure must be
1500 /// the same size as the non-volatile NIC storage.
1501 ///
1502 typedef union u_pxe_cpb_nvdata_bulk {
1503 ///
1504 /// Array of byte-wide data items.
1505 ///
1506 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1507
1508 ///
1509 /// Array of word-wide data items.
1510 ///
1511 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1512
1513 ///
1514 /// Array of dword-wide data items.
1515 ///
1516 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1517 } PXE_CPB_NVDATA_BULK;
1518
1519 typedef struct s_pxe_db_nvdata {
1520 ///
1521 /// Arrays of data items from non-volatile storage.
1522 ///
1523 union {
1524 ///
1525 /// Array of byte-wide data items.
1526 ///
1527 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1528
1529 ///
1530 /// Array of word-wide data items.
1531 ///
1532 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1533
1534 ///
1535 /// Array of dword-wide data items.
1536 ///
1537 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1538 } Data;
1539 } PXE_DB_NVDATA;
1540
1541 typedef struct s_pxe_db_get_status {
1542 ///
1543 /// Length of next receive frame (header + data). If this is zero,
1544 /// there is no next receive frame available.
1545 ///
1546 PXE_UINT32 RxFrameLen;
1547
1548 ///
1549 /// Reserved, set to zero.
1550 ///
1551 PXE_UINT32 reserved;
1552
1553 ///
1554 /// Addresses of transmitted buffers that need to be recycled.
1555 ///
1556 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];
1557 } PXE_DB_GET_STATUS;
1558
1559 typedef struct s_pxe_cpb_fill_header {
1560 ///
1561 /// Source and destination MAC addresses. These will be copied into
1562 /// the media header without doing byte swapping.
1563 ///
1564 PXE_MAC_ADDR SrcAddr;
1565 PXE_MAC_ADDR DestAddr;
1566
1567 ///
1568 /// Address of first byte of media header. The first byte of packet data
1569 /// follows the last byte of the media header.
1570 ///
1571 PXE_UINT64 MediaHeader;
1572
1573 ///
1574 /// Length of packet data in bytes (not including the media header).
1575 ///
1576 PXE_UINT32 PacketLen;
1577
1578 ///
1579 /// Protocol type. This will be copied into the media header without
1580 /// doing byte swapping. Protocol type numbers can be obtained from
1581 /// the Assigned Numbers RFC 1700.
1582 ///
1583 PXE_UINT16 Protocol;
1584
1585 ///
1586 /// Length of the media header in bytes.
1587 ///
1588 PXE_UINT16 MediaHeaderLen;
1589 } PXE_CPB_FILL_HEADER;
1590
1591 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
1592 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1593 #define MAX_XMIT_FRAGMENTS 16
1594
1595 typedef struct s_pxe_cpb_fill_header_fragmented {
1596 ///
1597 /// Source and destination MAC addresses. These will be copied into
1598 /// the media header without doing byte swapping.
1599 ///
1600 PXE_MAC_ADDR SrcAddr;
1601 PXE_MAC_ADDR DestAddr;
1602
1603 ///
1604 /// Length of packet data in bytes (not including the media header).
1605 ///
1606 PXE_UINT32 PacketLen;
1607
1608 ///
1609 /// Protocol type. This will be copied into the media header without
1610 /// doing byte swapping. Protocol type numbers can be obtained from
1611 /// the Assigned Numbers RFC 1700.
1612 ///
1613 PXE_MEDIA_PROTOCOL Protocol;
1614
1615 ///
1616 /// Length of the media header in bytes.
1617 ///
1618 PXE_UINT16 MediaHeaderLen;
1619
1620 ///
1621 /// Number of packet fragment descriptors.
1622 ///
1623 PXE_UINT16 FragCnt;
1624
1625 ///
1626 /// Reserved, must be set to zero.
1627 ///
1628 PXE_UINT16 reserved;
1629
1630 ///
1631 /// Array of packet fragment descriptors. The first byte of the media
1632 /// header is the first byte of the first fragment.
1633 ///
1634 struct {
1635 ///
1636 /// Address of this packet fragment.
1637 ///
1638 PXE_UINT64 FragAddr;
1639
1640 ///
1641 /// Length of this packet fragment.
1642 ///
1643 PXE_UINT32 FragLen;
1644
1645 ///
1646 /// Reserved, must be set to zero.
1647 ///
1648 PXE_UINT32 reserved;
1649 } FragDesc[MAX_XMIT_FRAGMENTS];
1650 }
1651 PXE_CPB_FILL_HEADER_FRAGMENTED;
1652
1653 typedef struct s_pxe_cpb_transmit {
1654 ///
1655 /// Address of first byte of frame buffer. This is also the first byte
1656 /// of the media header.
1657 ///
1658 PXE_UINT64 FrameAddr;
1659
1660 ///
1661 /// Length of the data portion of the frame buffer in bytes. Do not
1662 /// include the length of the media header.
1663 ///
1664 PXE_UINT32 DataLen;
1665
1666 ///
1667 /// Length of the media header in bytes.
1668 ///
1669 PXE_UINT16 MediaheaderLen;
1670
1671 ///
1672 /// Reserved, must be zero.
1673 ///
1674 PXE_UINT16 reserved;
1675 } PXE_CPB_TRANSMIT;
1676
1677 typedef struct s_pxe_cpb_transmit_fragments {
1678 ///
1679 /// Length of packet data in bytes (not including the media header).
1680 ///
1681 PXE_UINT32 FrameLen;
1682
1683 ///
1684 /// Length of the media header in bytes.
1685 ///
1686 PXE_UINT16 MediaheaderLen;
1687
1688 ///
1689 /// Number of packet fragment descriptors.
1690 ///
1691 PXE_UINT16 FragCnt;
1692
1693 ///
1694 /// Array of frame fragment descriptors. The first byte of the first
1695 /// fragment is also the first byte of the media header.
1696 ///
1697 struct {
1698 ///
1699 /// Address of this frame fragment.
1700 ///
1701 PXE_UINT64 FragAddr;
1702
1703 ///
1704 /// Length of this frame fragment.
1705 ///
1706 PXE_UINT32 FragLen;
1707
1708 ///
1709 /// Reserved, must be set to zero.
1710 ///
1711 PXE_UINT32 reserved;
1712 } FragDesc[MAX_XMIT_FRAGMENTS];
1713 }
1714 PXE_CPB_TRANSMIT_FRAGMENTS;
1715
1716 typedef struct s_pxe_cpb_receive {
1717 ///
1718 /// Address of first byte of receive buffer. This is also the first byte
1719 /// of the frame header.
1720 ///
1721 PXE_UINT64 BufferAddr;
1722
1723 ///
1724 /// Length of receive buffer. This must be large enough to hold the
1725 /// received frame (media header + data). If the length of smaller than
1726 /// the received frame, data will be lost.
1727 ///
1728 PXE_UINT32 BufferLen;
1729
1730 ///
1731 /// Reserved, must be set to zero.
1732 ///
1733 PXE_UINT32 reserved;
1734 } PXE_CPB_RECEIVE;
1735
1736 typedef struct s_pxe_db_receive {
1737 ///
1738 /// Source and destination MAC addresses from media header.
1739 ///
1740 PXE_MAC_ADDR SrcAddr;
1741 PXE_MAC_ADDR DestAddr;
1742
1743 ///
1744 /// Length of received frame. May be larger than receive buffer size.
1745 /// The receive buffer will not be overwritten. This is how to tell
1746 /// if data was lost because the receive buffer was too small.
1747 ///
1748 PXE_UINT32 FrameLen;
1749
1750 ///
1751 /// Protocol type from media header.
1752 ///
1753 PXE_MEDIA_PROTOCOL Protocol;
1754
1755 ///
1756 /// Length of media header in received frame.
1757 ///
1758 PXE_UINT16 MediaHeaderLen;
1759
1760 ///
1761 /// Type of receive frame.
1762 ///
1763 PXE_FRAME_TYPE Type;
1764
1765 ///
1766 /// Reserved, must be zero.
1767 ///
1768 PXE_UINT8 reserved[7];
1769
1770 } PXE_DB_RECEIVE;
1771
1772 #pragma pack()
1773
1774 #endif