MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 //
  16 // Include common header file for this module.
  17 //
  18 #include <Base.h>
  19 #include <Library/DebugLib.h>
  20
  21 /**
  22   Invalidates the entire instruction cache in cache coherency domain of the
  23   calling CPU.
  24
  25   Invalidates the entire instruction cache in cache coherency domain of the
  26   calling CPU.
  27
  28 **/
  29 VOID
  30 EFIAPI
  31 InvalidateInstructionCache (
  32   VOID
  33   )
  34 {
  35 }
  36
  37 /**
  38   Invalidates a range of instruction cache lines in the cache coherency domain
  39   of the calling CPU.
  40
  41   Invalidates the instruction cache lines specified by Address and Length. If
  42   Address is not aligned on a cache line boundary, then entire instruction
  43   cache line containing Address is invalidated. If Address + Length is not
  44   aligned on a cache line boundary, then the entire instruction cache line
  45   containing Address + Length -1 is invalidated. This function may choose to
  46   invalidate the entire instruction cache if that is more efficient than
  47   invalidating the specified range. If Length is 0, the no instruction cache
  48   lines are invalidated. Address is returned.
  49
  50   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  51
  52   @param  Address The base address of the instruction cache lines to
  53                   invalidate. If the CPU is in a physical addressing mode, then
  54                   Address is a physical address. If the CPU is in a virtual
  55                   addressing mode, then Address is a virtual address.
  56
  57   @param  Length  The number of bytes to invalidate from the instruction cache.
  58
  59   @return Address of cache invalidation.
  60
  61 **/
  62 VOID *
  63 EFIAPI
  64 InvalidateInstructionCacheRange (
  65   IN      VOID                      *Address,
  66   IN      UINTN                     Length
  67   )
  68 {
  69   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  70   return Address;
  71 }
  72
  73 /**
  74   Writes Back and Invalidates the entire data cache in cache coherency domain
  75   of the calling CPU.
  76
  77   Writes Back and Invalidates the entire data cache in cache coherency domain
  78   of the calling CPU. This function guarantees that all dirty cache lines are
  79   written back to system memory, and also invalidates all the data cache lines
  80   in the cache coherency domain of the calling CPU.
  81
  82 **/
  83 VOID
  84 EFIAPI
  85 WriteBackInvalidateDataCache (
  86   VOID
  87   )
  88 {
  89 }
  90
  91 /**
  92   Writes Back and Invalidates a range of data cache lines in the cache
  93   coherency domain of the calling CPU.
  94
  95   Writes Back and Invalidate the data cache lines specified by Address and
  96   Length. If Address is not aligned on a cache line boundary, then entire data
  97   cache line containing Address is written back and invalidated. If Address +
  98   Length is not aligned on a cache line boundary, then the entire data cache
  99   line containing Address + Length -1 is written back and invalidated. This
 100   function may choose to write back and invalidate the entire data cache if
 101   that is more efficient than writing back and invalidating the specified
 102   range. If Length is 0, the no data cache lines are written back and
 103   invalidated. Address is returned.
 104
 105   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 106
 107   @param  Address The base address of the data cache lines to write back and
 108                   invalidate. If the CPU is in a physical addressing mode, then
 109                   Address is a physical address. If the CPU is in a virtual
 110                   addressing mode, then Address is a virtual address.
 111   @param  Length  The number of bytes to write back and invalidate from the
 112                   data cache.
 113
 114   @return Address of cache invalidation.
 115
 116 **/
 117 VOID *
 118 EFIAPI
 119 WriteBackInvalidateDataCacheRange (
 120   IN      VOID                      *Address,
 121   IN      UINTN                     Length
 122   )
 123 {
 124   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 125   return Address;
 126 }
 127
 128 /**
 129   Writes Back the entire data cache in cache coherency domain of the calling
 130   CPU.
 131
 132   Writes Back the entire data cache in cache coherency domain of the calling
 133   CPU. This function guarantees that all dirty cache lines are written back to
 134   system memory. This function may also invalidate all the data cache lines in
 135   the cache coherency domain of the calling CPU.
 136
 137 **/
 138 VOID
 139 EFIAPI
 140 WriteBackDataCache (
 141   VOID
 142   )
 143 {
 144 }
 145
 146 /**
 147   Writes Back a range of data cache lines in the cache coherency domain of the
 148   calling CPU.
 149
 150   Writes Back the data cache lines specified by Address and Length. If Address
 151   is not aligned on a cache line boundary, then entire data cache line
 152   containing Address is written back. If Address + Length is not aligned on a
 153   cache line boundary, then the entire data cache line containing Address +
 154   Length -1 is written back. This function may choose to write back the entire
 155   data cache if that is more efficient than writing back the specified range.
 156   If Length is 0, the no data cache lines are written back. This function may
 157   also invalidate all the data cache lines in the specified range of the cache
 158   coherency domain of the calling CPU. Address is returned.
 159
 160   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 161
 162   @param  Address The base address of the data cache lines to write back. If
 163                   the CPU is in a physical addressing mode, then Address is a
 164                   physical address. If the CPU is in a virtual addressing
 165                   mode, then Address is a virtual address.
 166   @param  Length  The number of bytes to write back from the data cache.
 167
 168   @return Address of cache wrote in main memory.
 169
 170 **/
 171 VOID *
 172 EFIAPI
 173 WriteBackDataCacheRange (
 174   IN      VOID                      *Address,
 175   IN      UINTN                     Length
 176   )
 177 {
 178   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 179   return Address;
 180 }
 181
 182 /**
 183   Invalidates the entire data cache in cache coherency domain of the calling
 184   CPU.
 185
 186   Invalidates the entire data cache in cache coherency domain of the calling
 187   CPU. This function must be used with care because dirty cache lines are not
 188   written back to system memory. It is typically used for cache diagnostics. If
 189   the CPU does not support invalidation of the entire data cache, then a write
 190   back and invalidate operation should be performed on the entire data cache.
 191
 192 **/
 193 VOID
 194 EFIAPI
 195 InvalidateDataCache (
 196   VOID
 197   )
 198 {
 199 }
 200
 201 /**
 202   Invalidates a range of data cache lines in the cache coherency domain of the
 203   calling CPU.
 204
 205   Invalidates the data cache lines specified by Address and Length. If Address
 206   is not aligned on a cache line boundary, then entire data cache line
 207   containing Address is invalidated. If Address + Length is not aligned on a
 208   cache line boundary, then the entire data cache line containing Address +
 209   Length -1 is invalidated. This function must never invalidate any cache lines
 210   outside the specified range. If Length is 0, the no data cache lines are
 211   invalidated. Address is returned. This function must be used with care
 212   because dirty cache lines are not written back to system memory. It is
 213   typically used for cache diagnostics. If the CPU does not support
 214   invalidation of a data cache range, then a write back and invalidate
 215   operation should be performed on the data cache range.
 216
 217   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 218
 219   @param  Address The base address of the data cache lines to invalidate. If
 220                   the CPU is in a physical addressing mode, then Address is a
 221                   physical address. If the CPU is in a virtual addressing mode,
 222                   then Address is a virtual address.
 223   @param  Length  The number of bytes to invalidate from the data cache.
 224
 225   @return Address of cache invalidation.
 226
 227 **/
 228 VOID *
 229 EFIAPI
 230 InvalidateDataCacheRange (
 231   IN      VOID                      *Address,
 232   IN      UINTN                     Length
 233   )
 234 {
 235   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 236   return Address;
 237 }