MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation<BR>
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Base.h>
  16 #include <Library/DebugLib.h>
  17
  18 /**
  19   Invalidates the entire instruction cache in cache coherency domain of the
  20   calling CPU.
  21
  22   Invalidates the entire instruction cache in cache coherency domain of the
  23   calling CPU.
  24
  25 **/
  26 VOID
  27 EFIAPI
  28 InvalidateInstructionCache (
  29   VOID
  30   )
  31 {
  32 }
  33
  34 /**
  35   Invalidates a range of instruction cache lines in the cache coherency domain
  36   of the calling CPU.
  37
  38   Invalidates the instruction cache lines specified by Address and Length. If
  39   Address is not aligned on a cache line boundary, then entire instruction
  40   cache line containing Address is invalidated. If Address + Length is not
  41   aligned on a cache line boundary, then the entire instruction cache line
  42   containing Address + Length -1 is invalidated. This function may choose to
  43   invalidate the entire instruction cache if that is more efficient than
  44   invalidating the specified range. If Length is 0, the no instruction cache
  45   lines are invalidated. Address is returned.
  46
  47   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  48
  49   @param  Address The base address of the instruction cache lines to
  50                   invalidate. If the CPU is in a physical addressing mode, then
  51                   Address is a physical address. If the CPU is in a virtual
  52                   addressing mode, then Address is a virtual address.
  53
  54   @param  Length  The number of bytes to invalidate from the instruction cache.
  55
  56   @return Address.
  57
  58 **/
  59 VOID *
  60 EFIAPI
  61 InvalidateInstructionCacheRange (
  62   IN      VOID                      *Address,
  63   IN      UINTN                     Length
  64   )
  65 {
  66   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  67   return Address;
  68 }
  69
  70 /**
  71   Writes Back and Invalidates the entire data cache in cache coherency domain
  72   of the calling CPU.
  73
  74   Writes Back and Invalidates the entire data cache in cache coherency domain
  75   of the calling CPU. This function guarantees that all dirty cache lines are
  76   written back to system memory, and also invalidates all the data cache lines
  77   in the cache coherency domain of the calling CPU.
  78
  79 **/
  80 VOID
  81 EFIAPI
  82 WriteBackInvalidateDataCache (
  83   VOID
  84   )
  85 {
  86 }
  87
  88 /**
  89   Writes Back and Invalidates a range of data cache lines in the cache
  90   coherency domain of the calling CPU.
  91
  92   Writes Back and Invalidate the data cache lines specified by Address and
  93   Length. If Address is not aligned on a cache line boundary, then entire data
  94   cache line containing Address is written back and invalidated. If Address +
  95   Length is not aligned on a cache line boundary, then the entire data cache
  96   line containing Address + Length -1 is written back and invalidated. This
  97   function may choose to write back and invalidate the entire data cache if
  98   that is more efficient than writing back and invalidating the specified
  99   range. If Length is 0, the no data cache lines are written back and
 100   invalidated. Address is returned.
 101
 102   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 103
 104   @param  Address The base address of the data cache lines to write back and
 105                   invalidate. If the CPU is in a physical addressing mode, then
 106                   Address is a physical address. If the CPU is in a virtual
 107                   addressing mode, then Address is a virtual address.
 108   @param  Length  The number of bytes to write back and invalidate from the
 109                   data cache.
 110
 111   @return Address of cache invalidation.
 112
 113 **/
 114 VOID *
 115 EFIAPI
 116 WriteBackInvalidateDataCacheRange (
 117   IN      VOID                      *Address,
 118   IN      UINTN                     Length
 119   )
 120 {
 121   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 122   return Address;
 123 }
 124
 125 /**
 126   Writes Back the entire data cache in cache coherency domain of the calling
 127   CPU.
 128
 129   Writes Back the entire data cache in cache coherency domain of the calling
 130   CPU. This function guarantees that all dirty cache lines are written back to
 131   system memory. This function may also invalidate all the data cache lines in
 132   the cache coherency domain of the calling CPU.
 133
 134 **/
 135 VOID
 136 EFIAPI
 137 WriteBackDataCache (
 138   VOID
 139   )
 140 {
 141 }
 142
 143 /**
 144   Writes Back a range of data cache lines in the cache coherency domain of the
 145   calling CPU.
 146
 147   Writes Back the data cache lines specified by Address and Length. If Address
 148   is not aligned on a cache line boundary, then entire data cache line
 149   containing Address is written back. If Address + Length is not aligned on a
 150   cache line boundary, then the entire data cache line containing Address +
 151   Length -1 is written back. This function may choose to write back the entire
 152   data cache if that is more efficient than writing back the specified range.
 153   If Length is 0, the no data cache lines are written back. This function may
 154   also invalidate all the data cache lines in the specified range of the cache
 155   coherency domain of the calling CPU. Address is returned.
 156
 157   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 158
 159   @param  Address The base address of the data cache lines to write back. If
 160                   the CPU is in a physical addressing mode, then Address is a
 161                   physical address. If the CPU is in a virtual addressing
 162                   mode, then Address is a virtual address.
 163   @param  Length  The number of bytes to write back from the data cache.
 164
 165   @return Address of cache written in main memory.
 166
 167 **/
 168 VOID *
 169 EFIAPI
 170 WriteBackDataCacheRange (
 171   IN      VOID                      *Address,
 172   IN      UINTN                     Length
 173   )
 174 {
 175   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 176   return Address;
 177 }
 178
 179 /**
 180   Invalidates the entire data cache in cache coherency domain of the calling
 181   CPU.
 182
 183   Invalidates the entire data cache in cache coherency domain of the calling
 184   CPU. This function must be used with care because dirty cache lines are not
 185   written back to system memory. It is typically used for cache diagnostics. If
 186   the CPU does not support invalidation of the entire data cache, then a write
 187   back and invalidate operation should be performed on the entire data cache.
 188
 189 **/
 190 VOID
 191 EFIAPI
 192 InvalidateDataCache (
 193   VOID
 194   )
 195 {
 196 }
 197
 198 /**
 199   Invalidates a range of data cache lines in the cache coherency domain of the
 200   calling CPU.
 201
 202   Invalidates the data cache lines specified by Address and Length. If Address
 203   is not aligned on a cache line boundary, then entire data cache line
 204   containing Address is invalidated. If Address + Length is not aligned on a
 205   cache line boundary, then the entire data cache line containing Address +
 206   Length -1 is invalidated. This function must never invalidate any cache lines
 207   outside the specified range. If Length is 0, the no data cache lines are
 208   invalidated. Address is returned. This function must be used with care
 209   because dirty cache lines are not written back to system memory. It is
 210   typically used for cache diagnostics. If the CPU does not support
 211   invalidation of a data cache range, then a write back and invalidate
 212   operation should be performed on the data cache range.
 213
 214   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 215
 216   @param  Address The base address of the data cache lines to invalidate. If
 217                   the CPU is in a physical addressing mode, then Address is a
 218                   physical address. If the CPU is in a virtual addressing mode,
 219                   then Address is a virtual address.
 220   @param  Length  The number of bytes to invalidate from the data cache.
 221
 222   @return Address.
 223
 224 **/
 225 VOID *
 226 EFIAPI
 227 InvalidateDataCacheRange (
 228   IN      VOID                      *Address,
 229   IN      UINTN                     Length
 230   )
 231 {
 232   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 233   return Address;
 234 }