2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2008, Intel Corporation All rights
5 reserved. This program and the accompanying materials are
6 licensed and made available under the terms and conditions of
7 the BSD License which accompanies this distribution. The full
8 text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Protocol/PciRootBridgeIo.h>
20 #include <Library/PciLib.h>
21 #include <Library/BaseLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/DebugLib.h>
26 Assert the validity of a PCI address. A valid PCI address should contain 1's
27 only in the low 28 bits.
29 @param A The address to validate.
30 @param M Additional bits to assert to be zero.
33 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
34 ASSERT (((A) & (~0xfffffff | (M))) == 0)
37 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
39 @param A Address that encodes the PCI Bus, Device, Function and
43 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
44 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
47 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
49 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
52 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
54 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
55 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
57 @param ImageHandle The firmware allocated handle for the EFI image.
58 @param SystemTable A pointer to the EFI System Table.
60 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
66 IN EFI_HANDLE ImageHandle
,
67 IN EFI_SYSTEM_TABLE
*SystemTable
72 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
73 ASSERT_EFI_ERROR (Status
);
74 ASSERT (mPciRootBridgeIo
!= NULL
);
80 Internal worker function to read a PCI configuration register.
82 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
83 It reads and returns the PCI configuration register specified by Address,
84 the width of data is specified by Width.
86 @param Address Address that encodes the PCI Bus, Device, Function and
88 @param Width Width of data to read
90 @return The value read from the PCI configuration register.
94 DxePciLibPciRootBridgeIoReadWorker (
96 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
101 mPciRootBridgeIo
->Pci
.Read (
104 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
113 Internal worker function to writes a PCI configuration register.
115 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
116 It writes the PCI configuration register specified by Address with the
117 value specified by Data. The width of data is specifed by Width.
120 @param Address Address that encodes the PCI Bus, Device, Function and
122 @param Width Width of data to write
123 @param Data The value to write.
125 @return The value written to the PCI configuration register.
129 DxePciLibPciRootBridgeIoWriteWorker (
131 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
135 mPciRootBridgeIo
->Pci
.Write (
138 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
146 Registers a PCI device so PCI configuration registers may be accessed after
147 SetVirtualAddressMap().
149 Registers the PCI device specified by Address so all the PCI configuration registers
150 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
152 If Address > 0x0FFFFFFF, then ASSERT().
154 @param Address Address that encodes the PCI Bus, Device, Function and
157 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
158 @retval RETURN_UNSUPPORTED An attempt was made to call this function
159 after ExitBootServices().
160 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
161 at runtime could not be mapped.
162 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
163 complete the registration.
168 PciRegisterForRuntimeAccess (
172 return RETURN_UNSUPPORTED
;
176 Reads an 8-bit PCI configuration register.
178 Reads and returns the 8-bit PCI configuration register specified by Address.
179 This function must guarantee that all PCI read and write operations are
182 If Address > 0x0FFFFFFF, then ASSERT().
184 @param Address Address that encodes the PCI Bus, Device, Function and
187 @return The read value from the PCI configuration register.
196 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
198 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
202 Writes an 8-bit PCI configuration register.
204 Writes the 8-bit PCI configuration register specified by Address with the
205 value specified by Value. Value is returned. This function must guarantee
206 that all PCI read and write operations are serialized.
208 If Address > 0x0FFFFFFF, then ASSERT().
210 @param Address Address that encodes the PCI Bus, Device, Function and
212 @param Value The value to write.
214 @return The value written to the PCI configuration register.
224 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
226 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Value
);
230 Performs a bitwise OR of an 8-bit PCI configuration register with
233 Reads the 8-bit PCI configuration register specified by Address, performs a
234 bitwise OR between the read result and the value specified by
235 OrData, and writes the result to the 8-bit PCI configuration register
236 specified by Address. The value written to the PCI configuration register is
237 returned. This function must guarantee that all PCI read and write operations
240 If Address > 0x0FFFFFFF, then ASSERT().
242 @param Address Address that encodes the PCI Bus, Device, Function and
244 @param OrData The value to OR with the PCI configuration register.
246 @return The value written back to the PCI configuration register.
256 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
260 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
263 Reads the 8-bit PCI configuration register specified by Address, performs a
264 bitwise AND between the read result and the value specified by AndData, and
265 writes the result to the 8-bit PCI configuration register specified by
266 Address. The value written to the PCI configuration register is returned.
267 This function must guarantee that all PCI read and write operations are
270 If Address > 0x0FFFFFFF, then ASSERT().
272 @param Address Address that encodes the PCI Bus, Device, Function and
274 @param AndData The value to AND with the PCI configuration register.
276 @return The value written back to the PCI configuration register.
286 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
290 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
291 value, followed a bitwise OR with another 8-bit value.
293 Reads the 8-bit PCI configuration register specified by Address, performs a
294 bitwise AND between the read result and the value specified by AndData,
295 performs a bitwise OR between the result of the AND operation and
296 the value specified by OrData, and writes the result to the 8-bit PCI
297 configuration register specified by Address. The value written to the PCI
298 configuration register is returned. This function must guarantee that all PCI
299 read and write operations are serialized.
301 If Address > 0x0FFFFFFF, then ASSERT().
303 @param Address Address that encodes the PCI Bus, Device, Function and
305 @param AndData The value to AND with the PCI configuration register.
306 @param OrData The value to OR with the result of the AND operation.
308 @return The value written back to the PCI configuration register.
319 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
323 Reads a bit field of a PCI configuration register.
325 Reads the bit field in an 8-bit PCI configuration register. The bit field is
326 specified by the StartBit and the EndBit. The value of the bit field is
329 If Address > 0x0FFFFFFF, then ASSERT().
330 If StartBit is greater than 7, then ASSERT().
331 If EndBit is greater than 7, then ASSERT().
332 If EndBit is less than StartBit, then ASSERT().
334 @param Address PCI configuration register to read.
335 @param StartBit The ordinal of the least significant bit in the bit field.
337 @param EndBit The ordinal of the most significant bit in the bit field.
340 @return The value of the bit field read from the PCI configuration register.
351 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
355 Writes a bit field to a PCI configuration register.
357 Writes Value to the bit field of the PCI configuration register. The bit
358 field is specified by the StartBit and the EndBit. All other bits in the
359 destination PCI configuration register are preserved. The new value of the
360 8-bit register is returned.
362 If Address > 0x0FFFFFFF, then ASSERT().
363 If StartBit is greater than 7, then ASSERT().
364 If EndBit is greater than 7, then ASSERT().
365 If EndBit is less than StartBit, then ASSERT().
367 @param Address PCI configuration register to write.
368 @param StartBit The ordinal of the least significant bit in the bit field.
370 @param EndBit The ordinal of the most significant bit in the bit field.
372 @param Value New value of the bit field.
374 @return The value written back to the PCI configuration register.
388 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
393 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
394 writes the result back to the bit field in the 8-bit port.
396 Reads the 8-bit PCI configuration register specified by Address, performs a
397 bitwise OR between the read result and the value specified by
398 OrData, and writes the result to the 8-bit PCI configuration register
399 specified by Address. The value written to the PCI configuration register is
400 returned. This function must guarantee that all PCI read and write operations
401 are serialized. Extra left bits in OrData are stripped.
403 If Address > 0x0FFFFFFF, then ASSERT().
404 If StartBit is greater than 7, then ASSERT().
405 If EndBit is greater than 7, then ASSERT().
406 If EndBit is less than StartBit, then ASSERT().
408 @param Address PCI configuration register to write.
409 @param StartBit The ordinal of the least significant bit in the bit field.
411 @param EndBit The ordinal of the most significant bit in the bit field.
413 @param OrData The value to OR with the PCI configuration register.
415 @return The value written back to the PCI configuration register.
429 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
434 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
435 AND, and writes the result back to the bit field in the 8-bit register.
437 Reads the 8-bit PCI configuration register specified by Address, performs a
438 bitwise AND between the read result and the value specified by AndData, and
439 writes the result to the 8-bit PCI configuration register specified by
440 Address. The value written to the PCI configuration register is returned.
441 This function must guarantee that all PCI read and write operations are
442 serialized. Extra left bits in AndData are stripped.
444 If Address > 0x0FFFFFFF, then ASSERT().
445 If StartBit is greater than 7, then ASSERT().
446 If EndBit is greater than 7, then ASSERT().
447 If EndBit is less than StartBit, then ASSERT().
449 @param Address PCI configuration register to write.
450 @param StartBit The ordinal of the least significant bit in the bit field.
452 @param EndBit The ordinal of the most significant bit in the bit field.
454 @param AndData The value to AND with the PCI configuration register.
456 @return The value written back to the PCI configuration register.
470 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
475 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
476 bitwise OR, and writes the result back to the bit field in the
479 Reads the 8-bit PCI configuration register specified by Address, performs a
480 bitwise AND followed by a bitwise OR between the read result and
481 the value specified by AndData, and writes the result to the 8-bit PCI
482 configuration register specified by Address. The value written to the PCI
483 configuration register is returned. This function must guarantee that all PCI
484 read and write operations are serialized. Extra left bits in both AndData and
487 If Address > 0x0FFFFFFF, then ASSERT().
488 If StartBit is greater than 7, then ASSERT().
489 If EndBit is greater than 7, then ASSERT().
490 If EndBit is less than StartBit, then ASSERT().
492 @param Address PCI configuration register to write.
493 @param StartBit The ordinal of the least significant bit in the bit field.
495 @param EndBit The ordinal of the most significant bit in the bit field.
497 @param AndData The value to AND with the PCI configuration register.
498 @param OrData The value to OR with the result of the AND operation.
500 @return The value written back to the PCI configuration register.
505 PciBitFieldAndThenOr8 (
515 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
520 Reads a 16-bit PCI configuration register.
522 Reads and returns the 16-bit PCI configuration register specified by Address.
523 This function must guarantee that all PCI read and write operations are
526 If Address > 0x0FFFFFFF, then ASSERT().
527 If Address is not aligned on a 16-bit boundary, then ASSERT().
529 @param Address Address that encodes the PCI Bus, Device, Function and
532 @return The read value from the PCI configuration register.
541 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
543 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
547 Writes a 16-bit PCI configuration register.
549 Writes the 16-bit PCI configuration register specified by Address with the
550 value specified by Value. Value is returned. This function must guarantee
551 that all PCI read and write operations are serialized.
553 If Address > 0x0FFFFFFF, then ASSERT().
554 If Address is not aligned on a 16-bit boundary, then ASSERT().
556 @param Address Address that encodes the PCI Bus, Device, Function and
558 @param Value The value to write.
560 @return The value written to the PCI configuration register.
570 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
572 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Value
);
576 Performs a bitwise OR of a 16-bit PCI configuration register with
579 Reads the 16-bit PCI configuration register specified by Address, performs a
580 bitwise OR between the read result and the value specified by
581 OrData, and writes the result to the 16-bit PCI configuration register
582 specified by Address. The value written to the PCI configuration register is
583 returned. This function must guarantee that all PCI read and write operations
586 If Address > 0x0FFFFFFF, then ASSERT().
587 If Address is not aligned on a 16-bit boundary, then ASSERT().
589 @param Address Address that encodes the PCI Bus, Device, Function and
591 @param OrData The value to OR with the PCI configuration register.
593 @return The value written back to the PCI configuration register.
603 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
607 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
610 Reads the 16-bit PCI configuration register specified by Address, performs a
611 bitwise AND between the read result and the value specified by AndData, and
612 writes the result to the 16-bit PCI configuration register specified by
613 Address. The value written to the PCI configuration register is returned.
614 This function must guarantee that all PCI read and write operations are
617 If Address > 0x0FFFFFFF, then ASSERT().
618 If Address is not aligned on a 16-bit boundary, then ASSERT().
620 @param Address Address that encodes the PCI Bus, Device, Function and
622 @param AndData The value to AND with the PCI configuration register.
624 @return The value written back to the PCI configuration register.
634 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
638 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
639 value, followed a bitwise OR with another 16-bit value.
641 Reads the 16-bit PCI configuration register specified by Address, performs a
642 bitwise AND between the read result and the value specified by AndData,
643 performs a bitwise OR between the result of the AND operation and
644 the value specified by OrData, and writes the result to the 16-bit PCI
645 configuration register specified by Address. The value written to the PCI
646 configuration register is returned. This function must guarantee that all PCI
647 read and write operations are serialized.
649 If Address > 0x0FFFFFFF, then ASSERT().
650 If Address is not aligned on a 16-bit boundary, then ASSERT().
652 @param Address Address that encodes the PCI Bus, Device, Function and
654 @param AndData The value to AND with the PCI configuration register.
655 @param OrData The value to OR with the result of the AND operation.
657 @return The value written back to the PCI configuration register.
668 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
672 Reads a bit field of a PCI configuration register.
674 Reads the bit field in a 16-bit PCI configuration register. The bit field is
675 specified by the StartBit and the EndBit. The value of the bit field is
678 If Address > 0x0FFFFFFF, then ASSERT().
679 If Address is not aligned on a 16-bit boundary, then ASSERT().
680 If StartBit is greater than 15, then ASSERT().
681 If EndBit is greater than 15, then ASSERT().
682 If EndBit is less than StartBit, then ASSERT().
684 @param Address PCI configuration register to read.
685 @param StartBit The ordinal of the least significant bit in the bit field.
687 @param EndBit The ordinal of the most significant bit in the bit field.
690 @return The value of the bit field read from the PCI configuration register.
701 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
705 Writes a bit field to a PCI configuration register.
707 Writes Value to the bit field of the PCI configuration register. The bit
708 field is specified by the StartBit and the EndBit. All other bits in the
709 destination PCI configuration register are preserved. The new value of the
710 16-bit register is returned.
712 If Address > 0x0FFFFFFF, then ASSERT().
713 If Address is not aligned on a 16-bit boundary, then ASSERT().
714 If StartBit is greater than 15, then ASSERT().
715 If EndBit is greater than 15, then ASSERT().
716 If EndBit is less than StartBit, then ASSERT().
718 @param Address PCI configuration register to write.
719 @param StartBit The ordinal of the least significant bit in the bit field.
721 @param EndBit The ordinal of the most significant bit in the bit field.
723 @param Value New value of the bit field.
725 @return The value written back to the PCI configuration register.
739 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
744 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
745 writes the result back to the bit field in the 16-bit port.
747 Reads the 16-bit PCI configuration register specified by Address, performs a
748 bitwise OR between the read result and the value specified by
749 OrData, and writes the result to the 16-bit PCI configuration register
750 specified by Address. The value written to the PCI configuration register is
751 returned. This function must guarantee that all PCI read and write operations
752 are serialized. Extra left bits in OrData are stripped.
754 If Address > 0x0FFFFFFF, then ASSERT().
755 If Address is not aligned on a 16-bit boundary, then ASSERT().
756 If StartBit is greater than 15, then ASSERT().
757 If EndBit is greater than 15, then ASSERT().
758 If EndBit is less than StartBit, then ASSERT().
760 @param Address PCI configuration register to write.
761 @param StartBit The ordinal of the least significant bit in the bit field.
763 @param EndBit The ordinal of the most significant bit in the bit field.
765 @param OrData The value to OR with the PCI configuration register.
767 @return The value written back to the PCI configuration register.
781 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
786 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
787 AND, and writes the result back to the bit field in the 16-bit register.
789 Reads the 16-bit PCI configuration register specified by Address, performs a
790 bitwise AND between the read result and the value specified by AndData, and
791 writes the result to the 16-bit PCI configuration register specified by
792 Address. The value written to the PCI configuration register is returned.
793 This function must guarantee that all PCI read and write operations are
794 serialized. Extra left bits in AndData are stripped.
796 If Address > 0x0FFFFFFF, then ASSERT().
797 If Address is not aligned on a 16-bit boundary, then ASSERT().
798 If StartBit is greater than 15, then ASSERT().
799 If EndBit is greater than 15, then ASSERT().
800 If EndBit is less than StartBit, then ASSERT().
802 @param Address PCI configuration register to write.
803 @param StartBit The ordinal of the least significant bit in the bit field.
805 @param EndBit The ordinal of the most significant bit in the bit field.
807 @param AndData The value to AND with the PCI configuration register.
809 @return The value written back to the PCI configuration register.
823 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
828 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
829 bitwise OR, and writes the result back to the bit field in the
832 Reads the 16-bit PCI configuration register specified by Address, performs a
833 bitwise AND followed by a bitwise OR between the read result and
834 the value specified by AndData, and writes the result to the 16-bit PCI
835 configuration register specified by Address. The value written to the PCI
836 configuration register is returned. This function must guarantee that all PCI
837 read and write operations are serialized. Extra left bits in both AndData and
840 If Address > 0x0FFFFFFF, then ASSERT().
841 If Address is not aligned on a 16-bit boundary, then ASSERT().
842 If StartBit is greater than 15, then ASSERT().
843 If EndBit is greater than 15, then ASSERT().
844 If EndBit is less than StartBit, then ASSERT().
846 @param Address PCI configuration register to write.
847 @param StartBit The ordinal of the least significant bit in the bit field.
849 @param EndBit The ordinal of the most significant bit in the bit field.
851 @param AndData The value to AND with the PCI configuration register.
852 @param OrData The value to OR with the result of the AND operation.
854 @return The value written back to the PCI configuration register.
859 PciBitFieldAndThenOr16 (
869 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
874 Reads a 32-bit PCI configuration register.
876 Reads and returns the 32-bit PCI configuration register specified by Address.
877 This function must guarantee that all PCI read and write operations are
880 If Address > 0x0FFFFFFF, then ASSERT().
881 If Address is not aligned on a 32-bit boundary, then ASSERT().
883 @param Address Address that encodes the PCI Bus, Device, Function and
886 @return The read value from the PCI configuration register.
895 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
897 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
901 Writes a 32-bit PCI configuration register.
903 Writes the 32-bit PCI configuration register specified by Address with the
904 value specified by Value. Value is returned. This function must guarantee
905 that all PCI read and write operations are serialized.
907 If Address > 0x0FFFFFFF, then ASSERT().
908 If Address is not aligned on a 32-bit boundary, then ASSERT().
910 @param Address Address that encodes the PCI Bus, Device, Function and
912 @param Value The value to write.
914 @return The value written to the PCI configuration register.
924 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
926 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Value
);
930 Performs a bitwise OR of a 32-bit PCI configuration register with
933 Reads the 32-bit PCI configuration register specified by Address, performs a
934 bitwise OR between the read result and the value specified by
935 OrData, and writes the result to the 32-bit PCI configuration register
936 specified by Address. The value written to the PCI configuration register is
937 returned. This function must guarantee that all PCI read and write operations
940 If Address > 0x0FFFFFFF, then ASSERT().
941 If Address is not aligned on a 32-bit boundary, then ASSERT().
943 @param Address Address that encodes the PCI Bus, Device, Function and
945 @param OrData The value to OR with the PCI configuration register.
947 @return The value written back to the PCI configuration register.
957 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
961 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
964 Reads the 32-bit PCI configuration register specified by Address, performs a
965 bitwise AND between the read result and the value specified by AndData, and
966 writes the result to the 32-bit PCI configuration register specified by
967 Address. The value written to the PCI configuration register is returned.
968 This function must guarantee that all PCI read and write operations are
971 If Address > 0x0FFFFFFF, then ASSERT().
972 If Address is not aligned on a 32-bit boundary, then ASSERT().
974 @param Address Address that encodes the PCI Bus, Device, Function and
976 @param AndData The value to AND with the PCI configuration register.
978 @return The value written back to the PCI configuration register.
988 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
992 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
993 value, followed a bitwise OR with another 32-bit value.
995 Reads the 32-bit PCI configuration register specified by Address, performs a
996 bitwise AND between the read result and the value specified by AndData,
997 performs a bitwise OR between the result of the AND operation and
998 the value specified by OrData, and writes the result to the 32-bit PCI
999 configuration register specified by Address. The value written to the PCI
1000 configuration register is returned. This function must guarantee that all PCI
1001 read and write operations are serialized.
1003 If Address > 0x0FFFFFFF, then ASSERT().
1004 If Address is not aligned on a 32-bit boundary, then ASSERT().
1006 @param Address Address that encodes the PCI Bus, Device, Function and
1008 @param AndData The value to AND with the PCI configuration register.
1009 @param OrData The value to OR with the result of the AND operation.
1011 @return The value written back to the PCI configuration register.
1022 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1026 Reads a bit field of a PCI configuration register.
1028 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1029 specified by the StartBit and the EndBit. The value of the bit field is
1032 If Address > 0x0FFFFFFF, then ASSERT().
1033 If Address is not aligned on a 32-bit boundary, then ASSERT().
1034 If StartBit is greater than 31, then ASSERT().
1035 If EndBit is greater than 31, then ASSERT().
1036 If EndBit is less than StartBit, then ASSERT().
1038 @param Address PCI configuration register to read.
1039 @param StartBit The ordinal of the least significant bit in the bit field.
1041 @param EndBit The ordinal of the most significant bit in the bit field.
1044 @return The value of the bit field read from the PCI configuration register.
1055 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1059 Writes a bit field to a PCI configuration register.
1061 Writes Value to the bit field of the PCI configuration register. The bit
1062 field is specified by the StartBit and the EndBit. All other bits in the
1063 destination PCI configuration register are preserved. The new value of the
1064 32-bit register is returned.
1066 If Address > 0x0FFFFFFF, then ASSERT().
1067 If Address is not aligned on a 32-bit boundary, then ASSERT().
1068 If StartBit is greater than 31, then ASSERT().
1069 If EndBit is greater than 31, then ASSERT().
1070 If EndBit is less than StartBit, then ASSERT().
1072 @param Address PCI configuration register to write.
1073 @param StartBit The ordinal of the least significant bit in the bit field.
1075 @param EndBit The ordinal of the most significant bit in the bit field.
1077 @param Value New value of the bit field.
1079 @return The value written back to the PCI configuration register.
1084 PciBitFieldWrite32 (
1093 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1098 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1099 writes the result back to the bit field in the 32-bit port.
1101 Reads the 32-bit PCI configuration register specified by Address, performs a
1102 bitwise OR between the read result and the value specified by
1103 OrData, and writes the result to the 32-bit PCI configuration register
1104 specified by Address. The value written to the PCI configuration register is
1105 returned. This function must guarantee that all PCI read and write operations
1106 are serialized. Extra left bits in OrData are stripped.
1108 If Address > 0x0FFFFFFF, then ASSERT().
1109 If Address is not aligned on a 32-bit boundary, then ASSERT().
1110 If StartBit is greater than 31, then ASSERT().
1111 If EndBit is greater than 31, then ASSERT().
1112 If EndBit is less than StartBit, then ASSERT().
1114 @param Address PCI configuration register to write.
1115 @param StartBit The ordinal of the least significant bit in the bit field.
1117 @param EndBit The ordinal of the most significant bit in the bit field.
1119 @param OrData The value to OR with the PCI configuration register.
1121 @return The value written back to the PCI configuration register.
1135 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1140 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1141 AND, and writes the result back to the bit field in the 32-bit register.
1143 Reads the 32-bit PCI configuration register specified by Address, performs a
1144 bitwise AND between the read result and the value specified by AndData, and
1145 writes the result to the 32-bit PCI configuration register specified by
1146 Address. The value written to the PCI configuration register is returned.
1147 This function must guarantee that all PCI read and write operations are
1148 serialized. Extra left bits in AndData are stripped.
1150 If Address > 0x0FFFFFFF, then ASSERT().
1151 If Address is not aligned on a 32-bit boundary, then ASSERT().
1152 If StartBit is greater than 31, then ASSERT().
1153 If EndBit is greater than 31, then ASSERT().
1154 If EndBit is less than StartBit, then ASSERT().
1156 @param Address PCI configuration register to write.
1157 @param StartBit The ordinal of the least significant bit in the bit field.
1159 @param EndBit The ordinal of the most significant bit in the bit field.
1161 @param AndData The value to AND with the PCI configuration register.
1163 @return The value written back to the PCI configuration register.
1177 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1182 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1183 bitwise OR, and writes the result back to the bit field in the
1186 Reads the 32-bit PCI configuration register specified by Address, performs a
1187 bitwise AND followed by a bitwise OR between the read result and
1188 the value specified by AndData, and writes the result to the 32-bit PCI
1189 configuration register specified by Address. The value written to the PCI
1190 configuration register is returned. This function must guarantee that all PCI
1191 read and write operations are serialized. Extra left bits in both AndData and
1192 OrData are stripped.
1194 If Address > 0x0FFFFFFF, then ASSERT().
1195 If Address is not aligned on a 32-bit boundary, then ASSERT().
1196 If StartBit is greater than 31, then ASSERT().
1197 If EndBit is greater than 31, then ASSERT().
1198 If EndBit is less than StartBit, then ASSERT().
1200 @param Address PCI configuration register to write.
1201 @param StartBit The ordinal of the least significant bit in the bit field.
1203 @param EndBit The ordinal of the most significant bit in the bit field.
1205 @param AndData The value to AND with the PCI configuration register.
1206 @param OrData The value to OR with the result of the AND operation.
1208 @return The value written back to the PCI configuration register.
1213 PciBitFieldAndThenOr32 (
1223 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1228 Reads a range of PCI configuration registers into a caller supplied buffer.
1230 Reads the range of PCI configuration registers specified by StartAddress and
1231 Size into the buffer specified by Buffer. This function only allows the PCI
1232 configuration registers from a single PCI function to be read. Size is
1233 returned. When possible 32-bit PCI configuration read cycles are used to read
1234 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1235 and 16-bit PCI configuration read cycles may be used at the beginning and the
1238 If StartAddress > 0x0FFFFFFF, then ASSERT().
1239 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1240 If Size > 0 and Buffer is NULL, then ASSERT().
1242 @param StartAddress Starting address that encodes the PCI Bus, Device,
1243 Function and Register.
1244 @param Size Size in bytes of the transfer.
1245 @param Buffer Pointer to a buffer receiving the data read.
1253 IN UINTN StartAddress
,
1260 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1261 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1267 ASSERT (Buffer
!= NULL
);
1270 // Save Size for return
1274 if ((StartAddress
& BIT0
) != 0) {
1276 // Read a byte if StartAddress is byte aligned
1278 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1279 StartAddress
+= sizeof (UINT8
);
1280 Size
-= sizeof (UINT8
);
1281 Buffer
= (UINT8
*)Buffer
+ 1;
1284 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1286 // Read a word if StartAddress is word aligned
1288 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1289 StartAddress
+= sizeof (UINT16
);
1290 Size
-= sizeof (UINT16
);
1291 Buffer
= (UINT16
*)Buffer
+ 1;
1294 while (Size
>= sizeof (UINT32
)) {
1296 // Read as many double words as possible
1298 *(volatile UINT32
*)Buffer
= PciRead32 (StartAddress
);
1299 StartAddress
+= sizeof (UINT32
);
1300 Size
-= sizeof (UINT32
);
1301 Buffer
= (UINT32
*)Buffer
+ 1;
1304 if (Size
>= sizeof (UINT16
)) {
1306 // Read the last remaining word if exist
1308 *(volatile UINT16
*)Buffer
= PciRead16 (StartAddress
);
1309 StartAddress
+= sizeof (UINT16
);
1310 Size
-= sizeof (UINT16
);
1311 Buffer
= (UINT16
*)Buffer
+ 1;
1314 if (Size
>= sizeof (UINT8
)) {
1316 // Read the last remaining byte if exist
1318 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1325 Copies the data in a caller supplied buffer to a specified range of PCI
1326 configuration space.
1328 Writes the range of PCI configuration registers specified by StartAddress and
1329 Size from the buffer specified by Buffer. This function only allows the PCI
1330 configuration registers from a single PCI function to be written. Size is
1331 returned. When possible 32-bit PCI configuration write cycles are used to
1332 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1333 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1334 and the end of the range.
1336 If StartAddress > 0x0FFFFFFF, then ASSERT().
1337 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1338 If Size > 0 and Buffer is NULL, then ASSERT().
1340 @param StartAddress Starting address that encodes the PCI Bus, Device,
1341 Function and Register.
1342 @param Size Size in bytes of the transfer.
1343 @param Buffer Pointer to a buffer containing the data to write.
1345 @return Size written to StartAddress.
1351 IN UINTN StartAddress
,
1358 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1359 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1365 ASSERT (Buffer
!= NULL
);
1368 // Save Size for return
1372 if ((StartAddress
& BIT0
) != 0) {
1374 // Write a byte if StartAddress is byte aligned
1376 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1377 StartAddress
+= sizeof (UINT8
);
1378 Size
-= sizeof (UINT8
);
1379 Buffer
= (UINT8
*)Buffer
+ 1;
1382 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1384 // Write a word if StartAddress is word aligned
1386 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1387 StartAddress
+= sizeof (UINT16
);
1388 Size
-= sizeof (UINT16
);
1389 Buffer
= (UINT16
*)Buffer
+ 1;
1392 while (Size
>= sizeof (UINT32
)) {
1394 // Write as many double words as possible
1396 PciWrite32 (StartAddress
, *(UINT32
*)Buffer
);
1397 StartAddress
+= sizeof (UINT32
);
1398 Size
-= sizeof (UINT32
);
1399 Buffer
= (UINT32
*)Buffer
+ 1;
1402 if (Size
>= sizeof (UINT16
)) {
1404 // Write the last remaining word if exist
1406 PciWrite16 (StartAddress
, *(UINT16
*)Buffer
);
1407 StartAddress
+= sizeof (UINT16
);
1408 Size
-= sizeof (UINT16
);
1409 Buffer
= (UINT16
*)Buffer
+ 1;
1412 if (Size
>= sizeof (UINT8
)) {
1414 // Write the last remaining byte if exist
1416 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);