3 Virtual Memory Management Services to set or clear the memory encryption bit
5 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
8 This program and the accompanying materials are licensed and made available
9 under the terms and conditions of the BSD License which accompanies this
10 distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
14 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
20 #ifndef __VIRTUAL_MEMORY__
21 #define __VIRTUAL_MEMORY__
24 #include <Library/BaseLib.h>
25 #include <Library/BaseMemoryLib.h>
26 #include <Library/DebugLib.h>
27 #include <Library/MemoryAllocationLib.h>
29 #include <Library/CacheMaintenanceLib.h>
30 #define SYS_CODE64_SEL 0x38
35 // Page-Map Level-4 Offset (PML4) and
36 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
41 UINT64 Present
:1; // 0 = Not present in memory,
42 // 1 = Present in memory
43 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
44 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
45 UINT64 WriteThrough
:1; // 0 = Write-Back caching,
46 // 1 = Write-Through caching
47 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
48 UINT64 Accessed
:1; // 0 = Not accessed,
49 // 1 = Accessed (set by CPU)
50 UINT64 Reserved
:1; // Reserved
51 UINT64 MustBeZero
:2; // Must Be Zero
52 UINT64 Available
:3; // Available for use by system software
53 UINT64 PageTableBaseAddress
:40; // Page Table Base Address
54 UINT64 AvabilableHigh
:11; // Available for use by system software
55 UINT64 Nx
:1; // No Execute bit
58 } PAGE_MAP_AND_DIRECTORY_POINTER
;
61 // Page Table Entry 4KB
65 UINT64 Present
:1; // 0 = Not present in memory,
66 // 1 = Present in memory
67 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
68 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
69 UINT64 WriteThrough
:1; // 0 = Write-Back caching,
70 // 1 = Write-Through caching
71 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
72 UINT64 Accessed
:1; // 0 = Not accessed,
73 // 1 = Accessed (set by CPU)
74 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by
75 // processor on access to page
77 UINT64 Global
:1; // 0 = Not global page, 1 = global page
78 // TLB not cleared on CR3 write
79 UINT64 Available
:3; // Available for use by system software
80 UINT64 PageTableBaseAddress
:40; // Page Table Base Address
81 UINT64 AvabilableHigh
:11; // Available for use by system software
82 UINT64 Nx
:1; // 0 = Execute Code,
83 // 1 = No Code Execution
86 } PAGE_TABLE_4K_ENTRY
;
89 // Page Table Entry 2MB
93 UINT64 Present
:1; // 0 = Not present in memory,
94 // 1 = Present in memory
95 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
96 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
97 UINT64 WriteThrough
:1; // 0 = Write-Back caching,
98 // 1=Write-Through caching
99 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
100 UINT64 Accessed
:1; // 0 = Not accessed,
101 // 1 = Accessed (set by CPU)
102 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by
103 // processor on access to page
104 UINT64 MustBe1
:1; // Must be 1
105 UINT64 Global
:1; // 0 = Not global page, 1 = global page
106 // TLB not cleared on CR3 write
107 UINT64 Available
:3; // Available for use by system software
109 UINT64 MustBeZero
:8; // Must be zero;
110 UINT64 PageTableBaseAddress
:31; // Page Table Base Address
111 UINT64 AvabilableHigh
:11; // Available for use by system software
112 UINT64 Nx
:1; // 0 = Execute Code,
113 // 1 = No Code Execution
119 // Page Table Entry 1GB
123 UINT64 Present
:1; // 0 = Not present in memory,
124 // 1 = Present in memory
125 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
126 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
127 UINT64 WriteThrough
:1; // 0 = Write-Back caching,
128 // 1 = Write-Through caching
129 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
130 UINT64 Accessed
:1; // 0 = Not accessed,
131 // 1 = Accessed (set by CPU)
132 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by
133 // processor on access to page
134 UINT64 MustBe1
:1; // Must be 1
135 UINT64 Global
:1; // 0 = Not global page, 1 = global page
136 // TLB not cleared on CR3 write
137 UINT64 Available
:3; // Available for use by system software
139 UINT64 MustBeZero
:17; // Must be zero;
140 UINT64 PageTableBaseAddress
:22; // Page Table Base Address
141 UINT64 AvabilableHigh
:11; // Available for use by system software
142 UINT64 Nx
:1; // 0 = Execute Code,
143 // 1 = No Code Execution
146 } PAGE_TABLE_1G_ENTRY
;
150 #define IA32_PG_P BIT0
151 #define IA32_PG_RW BIT1
152 #define IA32_PG_PS BIT7
154 #define PAGING_PAE_INDEX_MASK 0x1FF
156 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
157 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
158 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
160 #define PAGING_L1_ADDRESS_SHIFT 12
161 #define PAGING_L2_ADDRESS_SHIFT 21
162 #define PAGING_L3_ADDRESS_SHIFT 30
163 #define PAGING_L4_ADDRESS_SHIFT 39
165 #define PAGING_PML4E_NUMBER 4
167 #define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)
168 #define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)
169 #define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)
170 #define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)
171 #define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)
172 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
174 #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
175 #define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB
176 #define PAGE_TABLE_POOL_UNIT_PAGES \
177 EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
178 #define PAGE_TABLE_POOL_ALIGN_MASK \
179 (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
190 This function clears memory encryption bit for the memory region specified by
191 PhysicalAddress and Length from the current page table context.
193 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
195 @param[in] PhysicalAddress The physical address that is the start
196 address of a memory region.
197 @param[in] Length The length of memory region
198 @param[in] Flush Flush the caches before applying the
201 @retval RETURN_SUCCESS The attributes were cleared for the
203 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
204 @retval RETURN_UNSUPPORTED Clearing the memory encyrption attribute
209 InternalMemEncryptSevSetMemoryDecrypted (
210 IN PHYSICAL_ADDRESS Cr3BaseAddress
,
211 IN PHYSICAL_ADDRESS PhysicalAddress
,
217 This function sets memory encryption bit for the memory region specified by
218 PhysicalAddress and Length from the current page table context.
220 @param[in] Cr3BaseAddress Cr3 Base Address (if zero then use
222 @param[in] PhysicalAddress The physical address that is the start
223 address of a memory region.
224 @param[in] Length The length of memory region
225 @param[in] Flush Flush the caches before applying the
228 @retval RETURN_SUCCESS The attributes were set for the memory
230 @retval RETURN_INVALID_PARAMETER Number of pages is zero.
231 @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute
236 InternalMemEncryptSevSetMemoryEncrypted (
237 IN PHYSICAL_ADDRESS Cr3BaseAddress
,
238 IN PHYSICAL_ADDRESS PhysicalAddress
,