2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // The package level header files this module uses
25 // The Library classes this module consumes
27 #include <Library/DebugLib.h>
28 #include <Library/HobLib.h>
29 #include <Library/IoLib.h>
30 #include <Library/PcdLib.h>
31 #include <Library/PeimEntryPoint.h>
32 #include <Library/ResourcePublicationLib.h>
33 #include <Library/MtrrLib.h>
39 GetSystemMemorySizeBelow4gb (
47 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
48 // * CMOS(0x35) is the high byte
49 // * CMOS(0x34) is the low byte
50 // * The size is specified in 64kb chunks
51 // * Since this is memory above 16MB, the 16MB must be added
52 // into the calculation to get the total memory size.
55 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
56 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
58 return (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
64 GetSystemMemorySizeAbove4gb (
71 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
72 // * CMOS(0x5d) is the most significant size byte
73 // * CMOS(0x5c) is the middle size byte
74 // * CMOS(0x5b) is the least significant size byte
75 // * The size is specified in 64kb chunks
79 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
80 Size
= (UINT32
) (Size
<< 8) + (UINT32
) CmosRead8 (CmosIndex
);
83 return LShiftU64 (Size
, 16);
87 Publish PEI core memory
89 @return EFI_SUCCESS The PEIM initialized successfully.
98 EFI_PHYSICAL_ADDRESS MemoryBase
;
100 UINT64 LowerMemorySize
;
102 if (mBootMode
== BOOT_ON_S3_RESUME
) {
103 MemoryBase
= PcdGet32 (PcdS3AcpiReservedMemoryBase
);
104 MemorySize
= PcdGet32 (PcdS3AcpiReservedMemorySize
);
106 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
109 // Determine the range of memory to use during PEI
111 MemoryBase
= PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
112 MemorySize
= LowerMemorySize
- MemoryBase
;
113 if (MemorySize
> SIZE_64MB
) {
114 MemoryBase
= LowerMemorySize
- SIZE_64MB
;
115 MemorySize
= SIZE_64MB
;
120 // Publish this memory to the PEI Core
122 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
123 ASSERT_EFI_ERROR (Status
);
130 Peform Memory Detection for QEMU / KVM
139 UINT64 LowerMemorySize
;
140 UINT64 UpperMemorySize
;
142 DEBUG ((EFI_D_INFO
, "%a called\n", __FUNCTION__
));
145 // Determine total memory size available
147 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
148 UpperMemorySize
= GetSystemMemorySizeAbove4gb ();
150 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
152 // Create memory HOBs
154 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
155 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
158 MtrrSetMemoryAttribute (BASE_1MB
, LowerMemorySize
- BASE_1MB
, CacheWriteBack
);
160 MtrrSetMemoryAttribute (0, BASE_512KB
+ BASE_128KB
, CacheWriteBack
);
162 if (UpperMemorySize
!= 0) {
163 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
164 AddUntestedMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
167 MtrrSetMemoryAttribute (BASE_4GB
, UpperMemorySize
, CacheWriteBack
);
172 Publish system RAM and reserve memory regions
176 InitializeRamRegions (
181 QemuInitializeRam ();
183 XenPublishRamRegions ();
186 if (mS3Supported
&& mBootMode
!= BOOT_ON_S3_RESUME
) {
188 // This is the memory range that will be used for PEI on S3 resume
190 BuildMemoryAllocationHob (
191 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdS3AcpiReservedMemoryBase
),
192 (UINT64
)(UINTN
) PcdGet32 (PcdS3AcpiReservedMemorySize
),
197 // Cover the initial RAM area used as stack and temporary PEI heap.
199 // This is reserved as ACPI NVS so it can be used on S3 resume.
201 BuildMemoryAllocationHob (
202 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
203 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
209 // Reserve the initial page tables built by the reset vector code.
211 // Since this memory range will be used by the Reset Vector on S3
212 // resume, it must be reserved as ACPI NVS.
214 BuildMemoryAllocationHob (
215 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesBase
),
216 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesSize
),