OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 MemMapInitialization (
 156   VOID
 157   )
 158 {
 159   UINT64 PciIoBase;
 160   UINT64 PciIoSize;
 161
 162   PciIoBase = 0xC000;
 163   PciIoSize = 0x4000;
 164
 165   //
 166   // Create Memory Type Information HOB
 167   //
 168   BuildGuidDataHob (
 169     &gEfiMemoryTypeInformationGuid,
 170     mDefaultMemoryTypeInformation,
 171     sizeof(mDefaultMemoryTypeInformation)
 172     );
 173
 174   //
 175   // Video memory + Legacy BIOS region
 176   //
 177   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 178
 179   if (!mXen) {
 180     UINT32  TopOfLowRam;
 181     UINT64  PciExBarBase;
 182     UINT32  PciBase;
 183     UINT32  PciSize;
 184
 185     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 186     PciExBarBase = 0;
 187     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 188       //
 189       // The MMCONFIG area is expected to fall between the top of low RAM and
 190       // the base of the 32-bit PCI host aperture.
 191       //
 192       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 193       ASSERT (TopOfLowRam <= PciExBarBase);
 194       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 195       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 196     } else {
 197       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 198     }
 199
 200     //
 201     // address       purpose   size
 202     // ------------  --------  -------------------------
 203     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 204     // 0xFC000000    gap                           44 MB
 205     // 0xFEC00000    IO-APIC                        4 KB
 206     // 0xFEC01000    gap                         1020 KB
 207     // 0xFED00000    HPET                           1 KB
 208     // 0xFED00400    gap                          111 KB
 209     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 210     // 0xFED20000    gap                          896 KB
 211     // 0xFEE00000    LAPIC                          1 MB
 212     //
 213     PciSize = 0xFC000000 - PciBase;
 214     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 215     PcdSet64 (PcdPciMmio32Base, PciBase);
 216     PcdSet64 (PcdPciMmio32Size, PciSize);
 217     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 218     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 219     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 220       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 221       //
 222       // Note: there should be an
 223       //
 224       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 225       //
 226       // call below, just like the one above for RCBA. However, Linux insists
 227       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 228       // "reserved memory" -- Linux does not content itself with a simple gap
 229       // in the memory map wherever the MCFG ACPI table points to.
 230       //
 231       // This appears to be a safety measure. The PCI Firmware Specification
 232       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 233       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 234       // [...]". (Emphasis added here.)
 235       //
 236       // Normally we add memory resource descriptor HOBs in
 237       // QemuInitializeRam(), and pre-allocate from those with memory
 238       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 239       // is most definitely not RAM; so, as an exception, cover it with
 240       // uncacheable reserved memory right here.
 241       //
 242       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 243       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 244         EfiReservedMemoryType);
 245     }
 246     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 247   }
 248
 249   //
 250   // Add PCI IO Port space available for PCI resource allocations.
 251   //
 252   BuildResourceDescriptorHob (
 253     EFI_RESOURCE_IO,
 254     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 255     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 256     PciIoBase,
 257     PciIoSize
 258     );
 259   PcdSet64 (PcdPciIoBase, PciIoBase);
 260   PcdSet64 (PcdPciIoSize, PciIoSize);
 261 }
 262
 263 EFI_STATUS
 264 GetNamedFwCfgBoolean (
 265   IN  CHAR8   *FwCfgFileName,
 266   OUT BOOLEAN *Setting
 267   )
 268 {
 269   EFI_STATUS           Status;
 270   FIRMWARE_CONFIG_ITEM FwCfgItem;
 271   UINTN                FwCfgSize;
 272   UINT8                Value[3];
 273
 274   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 275   if (EFI_ERROR (Status)) {
 276     return Status;
 277   }
 278   if (FwCfgSize > sizeof Value) {
 279     return EFI_BAD_BUFFER_SIZE;
 280   }
 281   QemuFwCfgSelectItem (FwCfgItem);
 282   QemuFwCfgReadBytes (FwCfgSize, Value);
 283
 284   if ((FwCfgSize == 1) ||
 285       (FwCfgSize == 2 && Value[1] == '\n') ||
 286       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 287     switch (Value[0]) {
 288       case '0':
 289       case 'n':
 290       case 'N':
 291         *Setting = FALSE;
 292         return EFI_SUCCESS;
 293
 294       case '1':
 295       case 'y':
 296       case 'Y':
 297         *Setting = TRUE;
 298         return EFI_SUCCESS;
 299
 300       default:
 301         break;
 302     }
 303   }
 304   return EFI_PROTOCOL_ERROR;
 305 }
 306
 307 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 308           do {                                                      \
 309             BOOLEAN Setting;                                        \
 310                                                                     \
 311             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 312                               "opt/ovmf/" #TokenName, &Setting))) { \
 313               PcdSetBool (TokenName, Setting);                      \
 314             }                                                       \
 315           } while (0)
 316
 317 VOID
 318 NoexecDxeInitialization (
 319   VOID
 320   )
 321 {
 322   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 323   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 324 }
 325
 326 VOID
 327 PciExBarInitialization (
 328   VOID
 329   )
 330 {
 331   union {
 332     UINT64 Uint64;
 333     UINT32 Uint32[2];
 334   } PciExBarBase;
 335
 336   //
 337   // We only support the 256MB size for the MMCONFIG area:
 338   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 339   //
 340   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 341   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 342   //
 343   // Note that (b) also ensures that the minimum address width we have
 344   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 345   // for DXE's page tables to cover the MMCONFIG area.
 346   //
 347   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 348   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 349   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 350
 351   //
 352   // Clear the PCIEXBAREN bit first, before programming the high register.
 353   //
 354   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 355
 356   //
 357   // Program the high register. Then program the low register, setting the
 358   // MMCONFIG area size and enabling decoding at once.
 359   //
 360   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 361   PciWrite32 (
 362     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 363     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 364     );
 365 }
 366
 367 VOID
 368 MiscInitialization (
 369   VOID
 370   )
 371 {
 372   UINTN  PmCmd;
 373   UINTN  Pmba;
 374   UINT32 PmbaAndVal;
 375   UINT32 PmbaOrVal;
 376   UINTN  AcpiCtlReg;
 377   UINT8  AcpiEnBit;
 378
 379   //
 380   // Disable A20 Mask
 381   //
 382   IoOr8 (0x92, BIT1);
 383
 384   //
 385   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 386   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 387   // S3 resume as well, so we build it unconditionally.)
 388   //
 389   BuildCpuHob (mPhysMemAddressWidth, 16);
 390
 391   //
 392   // Determine platform type and save Host Bridge DID to PCD
 393   //
 394   switch (mHostBridgeDevId) {
 395     case INTEL_82441_DEVICE_ID:
 396       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 397       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 398       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 399       PmbaOrVal  = PIIX4_PMBA_VALUE;
 400       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 401       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 402       break;
 403     case INTEL_Q35_MCH_DEVICE_ID:
 404       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 405       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 406       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 407       PmbaOrVal  = ICH9_PMBASE_VALUE;
 408       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 409       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 410       break;
 411     default:
 412       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 413         __FUNCTION__, mHostBridgeDevId));
 414       ASSERT (FALSE);
 415       return;
 416   }
 417   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 418
 419   //
 420   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 421   // has been configured (e.g., by Xen) and skip the setup here.
 422   // This matches the logic in AcpiTimerLibConstructor ().
 423   //
 424   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 425     //
 426     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 427     // 1. set PMBA
 428     //
 429     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 430
 431     //
 432     // 2. set PCICMD/IOSE
 433     //
 434     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 435
 436     //
 437     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 438     //
 439     PciOr8 (AcpiCtlReg, AcpiEnBit);
 440   }
 441
 442   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 443     //
 444     // Set Root Complex Register Block BAR
 445     //
 446     PciWrite32 (
 447       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 448       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 449       );
 450
 451     //
 452     // Set PCI Express Register Range Base Address
 453     //
 454     PciExBarInitialization ();
 455   }
 456 }
 457
 458
 459 VOID
 460 BootModeInitialization (
 461   VOID
 462   )
 463 {
 464   EFI_STATUS    Status;
 465
 466   if (CmosRead8 (0xF) == 0xFE) {
 467     mBootMode = BOOT_ON_S3_RESUME;
 468   }
 469   CmosWrite8 (0xF, 0x00);
 470
 471   Status = PeiServicesSetBootMode (mBootMode);
 472   ASSERT_EFI_ERROR (Status);
 473
 474   Status = PeiServicesInstallPpi (mPpiBootMode);
 475   ASSERT_EFI_ERROR (Status);
 476 }
 477
 478
 479 VOID
 480 ReserveEmuVariableNvStore (
 481   )
 482 {
 483   EFI_PHYSICAL_ADDRESS VariableStore;
 484
 485   //
 486   // Allocate storage for NV variables early on so it will be
 487   // at a consistent address.  Since VM memory is preserved
 488   // across reboots, this allows the NV variable storage to survive
 489   // a VM reboot.
 490   //
 491   VariableStore =
 492     (EFI_PHYSICAL_ADDRESS)(UINTN)
 493       AllocateAlignedRuntimePages (
 494         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 495         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 496         );
 497   DEBUG ((EFI_D_INFO,
 498           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 499           VariableStore,
 500           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 501         ));
 502   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 503 }
 504
 505
 506 VOID
 507 DebugDumpCmos (
 508   VOID
 509   )
 510 {
 511   UINT32 Loop;
 512
 513   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 514
 515   for (Loop = 0; Loop < 0x80; Loop++) {
 516     if ((Loop % 0x10) == 0) {
 517       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 518     }
 519     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 520     if ((Loop % 0x10) == 0xf) {
 521       DEBUG ((EFI_D_INFO, "\n"));
 522     }
 523   }
 524 }
 525
 526
 527 VOID
 528 S3Verification (
 529   VOID
 530   )
 531 {
 532 #if defined (MDE_CPU_X64)
 533   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 534     DEBUG ((EFI_D_ERROR,
 535       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 536     DEBUG ((EFI_D_ERROR,
 537       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 538       __FUNCTION__));
 539     DEBUG ((EFI_D_ERROR,
 540       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 541     ASSERT (FALSE);
 542     CpuDeadLoop ();
 543   }
 544 #endif
 545 }
 546
 547
 548 /**
 549   Perform Platform PEI initialization.
 550
 551   @param  FileHandle      Handle of the file being invoked.
 552   @param  PeiServices     Describes the list of possible PEI Services.
 553
 554   @return EFI_SUCCESS     The PEIM initialized successfully.
 555
 556 **/
 557 EFI_STATUS
 558 EFIAPI
 559 InitializePlatform (
 560   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 561   IN CONST EFI_PEI_SERVICES     **PeiServices
 562   )
 563 {
 564   EFI_STATUS    Status;
 565
 566   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 567
 568   DebugDumpCmos ();
 569
 570   XenDetect ();
 571
 572   if (QemuFwCfgS3Enabled ()) {
 573     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 574     mS3Supported = TRUE;
 575     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 576     ASSERT_EFI_ERROR (Status);
 577   }
 578
 579   S3Verification ();
 580   BootModeInitialization ();
 581   AddressWidthInitialization ();
 582
 583   PublishPeiMemory ();
 584
 585   InitializeRamRegions ();
 586
 587   if (mXen) {
 588     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 589     InitializeXen ();
 590   }
 591
 592   //
 593   // Query Host Bridge DID
 594   //
 595   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 596
 597   if (mBootMode != BOOT_ON_S3_RESUME) {
 598     ReserveEmuVariableNvStore ();
 599     PeiFvInitialization ();
 600     MemMapInitialization ();
 601     NoexecDxeInitialization ();
 602   }
 603
 604   MiscInitialization ();
 605
 606   return EFI_SUCCESS;
 607 }