OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 //
  12 // The package level header files this module uses
  13 //
  14 #include <PiPei.h>
  15
  16 //
  17 // The Library classes this module consumes
  18 //
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/HobLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/MemoryAllocationLib.h>
  24 #include <Library/PcdLib.h>
  25 #include <Library/PciLib.h>
  26 #include <Library/PeimEntryPoint.h>
  27 #include <Library/PeiServicesLib.h>
  28 #include <Library/QemuFwCfgLib.h>
  29 #include <Library/QemuFwCfgS3Lib.h>
  30 #include <Library/ResourcePublicationLib.h>
  31 #include <Guid/MemoryTypeInformation.h>
  32 #include <Ppi/MasterBootMode.h>
  33 #include <IndustryStandard/Pci22.h>
  34 #include <OvmfPlatforms.h>
  35
  36 #include "Platform.h"
  37 #include "Cmos.h"
  38
  39 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  40   { EfiACPIMemoryNVS,       0x004 },
  41   { EfiACPIReclaimMemory,   0x008 },
  42   { EfiReservedMemoryType,  0x004 },
  43   { EfiRuntimeServicesData, 0x024 },
  44   { EfiRuntimeServicesCode, 0x030 },
  45   { EfiBootServicesCode,    0x180 },
  46   { EfiBootServicesData,    0xF00 },
  47   { EfiMaxMemoryType,       0x000 }
  48 };
  49
  50
  51 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  52   {
  53     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  54     &gEfiPeiMasterBootModePpiGuid,
  55     NULL
  56   }
  57 };
  58
  59
  60 UINT16 mHostBridgeDevId;
  61
  62 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  63
  64 BOOLEAN mS3Supported = FALSE;
  65
  66 UINT32 mMaxCpuCount;
  67
  68 VOID
  69 AddIoMemoryBaseSizeHob (
  70   EFI_PHYSICAL_ADDRESS        MemoryBase,
  71   UINT64                      MemorySize
  72   )
  73 {
  74   BuildResourceDescriptorHob (
  75     EFI_RESOURCE_MEMORY_MAPPED_IO,
  76       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  77       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  78       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  79       EFI_RESOURCE_ATTRIBUTE_TESTED,
  80     MemoryBase,
  81     MemorySize
  82     );
  83 }
  84
  85 VOID
  86 AddReservedMemoryBaseSizeHob (
  87   EFI_PHYSICAL_ADDRESS        MemoryBase,
  88   UINT64                      MemorySize,
  89   BOOLEAN                     Cacheable
  90   )
  91 {
  92   BuildResourceDescriptorHob (
  93     EFI_RESOURCE_MEMORY_RESERVED,
  94       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  95       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  96       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  97       (Cacheable ?
  98        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  99        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 100        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 101        0
 102        ) |
 103       EFI_RESOURCE_ATTRIBUTE_TESTED,
 104     MemoryBase,
 105     MemorySize
 106     );
 107 }
 108
 109 VOID
 110 AddIoMemoryRangeHob (
 111   EFI_PHYSICAL_ADDRESS        MemoryBase,
 112   EFI_PHYSICAL_ADDRESS        MemoryLimit
 113   )
 114 {
 115   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 116 }
 117
 118
 119 VOID
 120 AddMemoryBaseSizeHob (
 121   EFI_PHYSICAL_ADDRESS        MemoryBase,
 122   UINT64                      MemorySize
 123   )
 124 {
 125   BuildResourceDescriptorHob (
 126     EFI_RESOURCE_SYSTEM_MEMORY,
 127       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 128       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 129       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 130       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 131       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 132       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 133       EFI_RESOURCE_ATTRIBUTE_TESTED,
 134     MemoryBase,
 135     MemorySize
 136     );
 137 }
 138
 139
 140 VOID
 141 AddMemoryRangeHob (
 142   EFI_PHYSICAL_ADDRESS        MemoryBase,
 143   EFI_PHYSICAL_ADDRESS        MemoryLimit
 144   )
 145 {
 146   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 147 }
 148
 149
 150 VOID
 151 MemMapInitialization (
 152   VOID
 153   )
 154 {
 155   UINT64        PciIoBase;
 156   UINT64        PciIoSize;
 157   RETURN_STATUS PcdStatus;
 158
 159   PciIoBase = 0xC000;
 160   PciIoSize = 0x4000;
 161
 162   //
 163   // Create Memory Type Information HOB
 164   //
 165   BuildGuidDataHob (
 166     &gEfiMemoryTypeInformationGuid,
 167     mDefaultMemoryTypeInformation,
 168     sizeof(mDefaultMemoryTypeInformation)
 169     );
 170
 171   //
 172   // Video memory + Legacy BIOS region
 173   //
 174   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 175
 176   if (!mXen) {
 177     UINT64  PciExBarBase;
 178     UINT32  PciBase;
 179     UINT32  PciSize;
 180
 181     PciExBarBase = 0;
 182     PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base;
 183     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 184       //
 185       // The 32-bit PCI host aperture is expected to fall between the top of
 186       // low RAM and the base of the MMCONFIG area.
 187       //
 188       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 189       ASSERT (PciBase < PciExBarBase);
 190       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 191       PciSize = (UINT32)(PciExBarBase - PciBase);
 192     } else {
 193       PciSize = 0xFC000000 - PciBase;
 194     }
 195
 196     //
 197     // address       purpose   size
 198     // ------------  --------  -------------------------
 199     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 200     // 0xFC000000    gap                           44 MB
 201     // 0xFEC00000    IO-APIC                        4 KB
 202     // 0xFEC01000    gap                         1020 KB
 203     // 0xFED00000    HPET                           1 KB
 204     // 0xFED00400    gap                          111 KB
 205     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 206     // 0xFED20000    gap                          896 KB
 207     // 0xFEE00000    LAPIC                          1 MB
 208     //
 209     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 210     PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
 211     ASSERT_RETURN_ERROR (PcdStatus);
 212     PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize);
 213     ASSERT_RETURN_ERROR (PcdStatus);
 214
 215     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 216     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 217     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 218       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 219       //
 220       // Note: there should be an
 221       //
 222       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 223       //
 224       // call below, just like the one above for RCBA. However, Linux insists
 225       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 226       // "reserved memory" -- Linux does not content itself with a simple gap
 227       // in the memory map wherever the MCFG ACPI table points to.
 228       //
 229       // This appears to be a safety measure. The PCI Firmware Specification
 230       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 231       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 232       // [...]". (Emphasis added here.)
 233       //
 234       // Normally we add memory resource descriptor HOBs in
 235       // QemuInitializeRam(), and pre-allocate from those with memory
 236       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 237       // is most definitely not RAM; so, as an exception, cover it with
 238       // uncacheable reserved memory right here.
 239       //
 240       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 241       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 242         EfiReservedMemoryType);
 243     }
 244     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 245
 246     //
 247     // On Q35, the IO Port space is available for PCI resource allocations from
 248     // 0x6000 up.
 249     //
 250     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 251       PciIoBase = 0x6000;
 252       PciIoSize = 0xA000;
 253       ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);
 254     }
 255   }
 256
 257   //
 258   // Add PCI IO Port space available for PCI resource allocations.
 259   //
 260   BuildResourceDescriptorHob (
 261     EFI_RESOURCE_IO,
 262     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 263     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 264     PciIoBase,
 265     PciIoSize
 266     );
 267   PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);
 268   ASSERT_RETURN_ERROR (PcdStatus);
 269   PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);
 270   ASSERT_RETURN_ERROR (PcdStatus);
 271 }
 272
 273 EFI_STATUS
 274 GetNamedFwCfgBoolean (
 275   IN  CHAR8   *FwCfgFileName,
 276   OUT BOOLEAN *Setting
 277   )
 278 {
 279   EFI_STATUS           Status;
 280   FIRMWARE_CONFIG_ITEM FwCfgItem;
 281   UINTN                FwCfgSize;
 282   UINT8                Value[3];
 283
 284   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 285   if (EFI_ERROR (Status)) {
 286     return Status;
 287   }
 288   if (FwCfgSize > sizeof Value) {
 289     return EFI_BAD_BUFFER_SIZE;
 290   }
 291   QemuFwCfgSelectItem (FwCfgItem);
 292   QemuFwCfgReadBytes (FwCfgSize, Value);
 293
 294   if ((FwCfgSize == 1) ||
 295       (FwCfgSize == 2 && Value[1] == '\n') ||
 296       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 297     switch (Value[0]) {
 298       case '0':
 299       case 'n':
 300       case 'N':
 301         *Setting = FALSE;
 302         return EFI_SUCCESS;
 303
 304       case '1':
 305       case 'y':
 306       case 'Y':
 307         *Setting = TRUE;
 308         return EFI_SUCCESS;
 309
 310       default:
 311         break;
 312     }
 313   }
 314   return EFI_PROTOCOL_ERROR;
 315 }
 316
 317 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 318           do {                                                      \
 319             BOOLEAN       Setting;                                  \
 320             RETURN_STATUS PcdStatus;                                \
 321                                                                     \
 322             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 323                               "opt/ovmf/" #TokenName, &Setting))) { \
 324               PcdStatus = PcdSetBoolS (TokenName, Setting);         \
 325               ASSERT_RETURN_ERROR (PcdStatus);                      \
 326             }                                                       \
 327           } while (0)
 328
 329 VOID
 330 NoexecDxeInitialization (
 331   VOID
 332   )
 333 {
 334   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 335   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 336 }
 337
 338 VOID
 339 PciExBarInitialization (
 340   VOID
 341   )
 342 {
 343   union {
 344     UINT64 Uint64;
 345     UINT32 Uint32[2];
 346   } PciExBarBase;
 347
 348   //
 349   // We only support the 256MB size for the MMCONFIG area:
 350   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 351   //
 352   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 353   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 354   //
 355   // Note that (b) also ensures that the minimum address width we have
 356   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 357   // for DXE's page tables to cover the MMCONFIG area.
 358   //
 359   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 360   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 361   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 362
 363   //
 364   // Clear the PCIEXBAREN bit first, before programming the high register.
 365   //
 366   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 367
 368   //
 369   // Program the high register. Then program the low register, setting the
 370   // MMCONFIG area size and enabling decoding at once.
 371   //
 372   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 373   PciWrite32 (
 374     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 375     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 376     );
 377 }
 378
 379 VOID
 380 MiscInitialization (
 381   VOID
 382   )
 383 {
 384   UINTN         PmCmd;
 385   UINTN         Pmba;
 386   UINT32        PmbaAndVal;
 387   UINT32        PmbaOrVal;
 388   UINTN         AcpiCtlReg;
 389   UINT8         AcpiEnBit;
 390   RETURN_STATUS PcdStatus;
 391
 392   //
 393   // Disable A20 Mask
 394   //
 395   IoOr8 (0x92, BIT1);
 396
 397   //
 398   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 399   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 400   // S3 resume as well, so we build it unconditionally.)
 401   //
 402   BuildCpuHob (mPhysMemAddressWidth, 16);
 403
 404   //
 405   // Determine platform type and save Host Bridge DID to PCD
 406   //
 407   switch (mHostBridgeDevId) {
 408     case INTEL_82441_DEVICE_ID:
 409       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 410       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 411       PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
 412       PmbaOrVal  = PIIX4_PMBA_VALUE;
 413       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 414       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 415       break;
 416     case INTEL_Q35_MCH_DEVICE_ID:
 417       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 418       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 419       PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
 420       PmbaOrVal  = ICH9_PMBASE_VALUE;
 421       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 422       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 423       break;
 424     default:
 425       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 426         __FUNCTION__, mHostBridgeDevId));
 427       ASSERT (FALSE);
 428       return;
 429   }
 430   PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 431   ASSERT_RETURN_ERROR (PcdStatus);
 432
 433   //
 434   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 435   // has been configured (e.g., by Xen) and skip the setup here.
 436   // This matches the logic in AcpiTimerLibConstructor ().
 437   //
 438   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 439     //
 440     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 441     // 1. set PMBA
 442     //
 443     PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
 444
 445     //
 446     // 2. set PCICMD/IOSE
 447     //
 448     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 449
 450     //
 451     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 452     //
 453     PciOr8 (AcpiCtlReg, AcpiEnBit);
 454   }
 455
 456   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 457     //
 458     // Set Root Complex Register Block BAR
 459     //
 460     PciWrite32 (
 461       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 462       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 463       );
 464
 465     //
 466     // Set PCI Express Register Range Base Address
 467     //
 468     PciExBarInitialization ();
 469   }
 470 }
 471
 472
 473 VOID
 474 BootModeInitialization (
 475   VOID
 476   )
 477 {
 478   EFI_STATUS    Status;
 479
 480   if (CmosRead8 (0xF) == 0xFE) {
 481     mBootMode = BOOT_ON_S3_RESUME;
 482   }
 483   CmosWrite8 (0xF, 0x00);
 484
 485   Status = PeiServicesSetBootMode (mBootMode);
 486   ASSERT_EFI_ERROR (Status);
 487
 488   Status = PeiServicesInstallPpi (mPpiBootMode);
 489   ASSERT_EFI_ERROR (Status);
 490 }
 491
 492
 493 VOID
 494 ReserveEmuVariableNvStore (
 495   )
 496 {
 497   EFI_PHYSICAL_ADDRESS VariableStore;
 498   RETURN_STATUS        PcdStatus;
 499
 500   //
 501   // Allocate storage for NV variables early on so it will be
 502   // at a consistent address.  Since VM memory is preserved
 503   // across reboots, this allows the NV variable storage to survive
 504   // a VM reboot.
 505   //
 506   VariableStore =
 507     (EFI_PHYSICAL_ADDRESS)(UINTN)
 508       AllocateRuntimePages (
 509         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))
 510         );
 511   DEBUG ((EFI_D_INFO,
 512           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 513           VariableStore,
 514           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 515         ));
 516   PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);
 517   ASSERT_RETURN_ERROR (PcdStatus);
 518 }
 519
 520
 521 VOID
 522 DebugDumpCmos (
 523   VOID
 524   )
 525 {
 526   UINT32 Loop;
 527
 528   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 529
 530   for (Loop = 0; Loop < 0x80; Loop++) {
 531     if ((Loop % 0x10) == 0) {
 532       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 533     }
 534     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 535     if ((Loop % 0x10) == 0xf) {
 536       DEBUG ((EFI_D_INFO, "\n"));
 537     }
 538   }
 539 }
 540
 541
 542 VOID
 543 S3Verification (
 544   VOID
 545   )
 546 {
 547 #if defined (MDE_CPU_X64)
 548   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 549     DEBUG ((EFI_D_ERROR,
 550       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 551     DEBUG ((EFI_D_ERROR,
 552       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 553       __FUNCTION__));
 554     DEBUG ((EFI_D_ERROR,
 555       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 556     ASSERT (FALSE);
 557     CpuDeadLoop ();
 558   }
 559 #endif
 560 }
 561
 562
 563 /**
 564   Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.
 565   Set the mMaxCpuCount variable.
 566 **/
 567 VOID
 568 MaxCpuCountInitialization (
 569   VOID
 570   )
 571 {
 572   UINT16        ProcessorCount;
 573   RETURN_STATUS PcdStatus;
 574
 575   QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
 576   ProcessorCount = QemuFwCfgRead16 ();
 577   //
 578   // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount
 579   // from the PCD default. No change to PCDs.
 580   //
 581   if (ProcessorCount == 0) {
 582     mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
 583     return;
 584   }
 585   //
 586   // Otherwise, set mMaxCpuCount to the value reported by QEMU.
 587   //
 588   mMaxCpuCount = ProcessorCount;
 589   //
 590   // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)
 591   // to wait, in the initial AP bringup, exactly as long as it takes for all of
 592   // the APs to report in. For this, we set the longest representable timeout
 593   // (approx. 71 minutes).
 594   //
 595   PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);
 596   ASSERT_RETURN_ERROR (PcdStatus);
 597   PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);
 598   ASSERT_RETURN_ERROR (PcdStatus);
 599   DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,
 600     ProcessorCount));
 601 }
 602
 603
 604 /**
 605   Perform Platform PEI initialization.
 606
 607   @param  FileHandle      Handle of the file being invoked.
 608   @param  PeiServices     Describes the list of possible PEI Services.
 609
 610   @return EFI_SUCCESS     The PEIM initialized successfully.
 611
 612 **/
 613 EFI_STATUS
 614 EFIAPI
 615 InitializePlatform (
 616   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 617   IN CONST EFI_PEI_SERVICES     **PeiServices
 618   )
 619 {
 620   EFI_STATUS    Status;
 621
 622   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
 623
 624   DebugDumpCmos ();
 625
 626   XenDetect ();
 627
 628   if (QemuFwCfgS3Enabled ()) {
 629     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 630     mS3Supported = TRUE;
 631     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 632     ASSERT_EFI_ERROR (Status);
 633   }
 634
 635   S3Verification ();
 636   BootModeInitialization ();
 637   AddressWidthInitialization ();
 638   MaxCpuCountInitialization ();
 639
 640   //
 641   // Query Host Bridge DID
 642   //
 643   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 644
 645   if (FeaturePcdGet (PcdSmmSmramRequire)) {
 646     Q35TsegMbytesInitialization ();
 647   }
 648
 649   PublishPeiMemory ();
 650
 651   InitializeRamRegions ();
 652
 653   if (mXen) {
 654     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 655     InitializeXen ();
 656   }
 657
 658   if (mBootMode != BOOT_ON_S3_RESUME) {
 659     if (!FeaturePcdGet (PcdSmmSmramRequire)) {
 660       ReserveEmuVariableNvStore ();
 661     }
 662     PeiFvInitialization ();
 663     MemMapInitialization ();
 664     NoexecDxeInitialization ();
 665   }
 666
 667   InstallClearCacheCallback ();
 668   AmdSevInitialize ();
 669   MiscInitialization ();
 670   InstallFeatureControlCallback ();
 671
 672   return EFI_SUCCESS;
 673 }