OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 AddUntestedMemoryBaseSizeHob (
 156   EFI_PHYSICAL_ADDRESS        MemoryBase,
 157   UINT64                      MemorySize
 158   )
 159 {
 160   BuildResourceDescriptorHob (
 161     EFI_RESOURCE_SYSTEM_MEMORY,
 162       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 163       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 164       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 165       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 166       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 167       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 168     MemoryBase,
 169     MemorySize
 170     );
 171 }
 172
 173
 174 VOID
 175 AddUntestedMemoryRangeHob (
 176   EFI_PHYSICAL_ADDRESS        MemoryBase,
 177   EFI_PHYSICAL_ADDRESS        MemoryLimit
 178   )
 179 {
 180   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 181 }
 182
 183 VOID
 184 MemMapInitialization (
 185   VOID
 186   )
 187 {
 188   //
 189   // Create Memory Type Information HOB
 190   //
 191   BuildGuidDataHob (
 192     &gEfiMemoryTypeInformationGuid,
 193     mDefaultMemoryTypeInformation,
 194     sizeof(mDefaultMemoryTypeInformation)
 195     );
 196
 197   //
 198   // Add PCI IO Port space available for PCI resource allocations.
 199   //
 200   BuildResourceDescriptorHob (
 201     EFI_RESOURCE_IO,
 202     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 203     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 204     PcdGet64 (PcdPciIoBase),
 205     PcdGet64 (PcdPciIoSize)
 206     );
 207
 208   //
 209   // Video memory + Legacy BIOS region
 210   //
 211   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 212
 213   if (!mXen) {
 214     UINT32  TopOfLowRam;
 215     UINT32  PciBase;
 216     UINT32  PciSize;
 217
 218     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 219     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 220       //
 221       // A 3GB base will always fall into Q35's 32-bit PCI host aperture,
 222       // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets
 223       // the RAM below 4 GB exceed it.
 224       //
 225       PciBase = BASE_2GB + BASE_1GB;
 226       ASSERT (TopOfLowRam <= PciBase);
 227     } else {
 228       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 229     }
 230
 231     //
 232     // address       purpose   size
 233     // ------------  --------  -------------------------
 234     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 235     // 0xFC000000    gap                           44 MB
 236     // 0xFEC00000    IO-APIC                        4 KB
 237     // 0xFEC01000    gap                         1020 KB
 238     // 0xFED00000    HPET                           1 KB
 239     // 0xFED00400    gap                          111 KB
 240     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 241     // 0xFED20000    gap                          896 KB
 242     // 0xFEE00000    LAPIC                          1 MB
 243     //
 244     PciSize = 0xFC000000 - PciBase;
 245     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 246     PcdSet64 (PcdPciMmio32Base, PciBase);
 247     PcdSet64 (PcdPciMmio32Size, PciSize);
 248     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 249     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 250     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 251       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 252     }
 253     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 254   }
 255 }
 256
 257 EFI_STATUS
 258 GetNamedFwCfgBoolean (
 259   IN  CHAR8   *FwCfgFileName,
 260   OUT BOOLEAN *Setting
 261   )
 262 {
 263   EFI_STATUS           Status;
 264   FIRMWARE_CONFIG_ITEM FwCfgItem;
 265   UINTN                FwCfgSize;
 266   UINT8                Value[3];
 267
 268   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 269   if (EFI_ERROR (Status)) {
 270     return Status;
 271   }
 272   if (FwCfgSize > sizeof Value) {
 273     return EFI_BAD_BUFFER_SIZE;
 274   }
 275   QemuFwCfgSelectItem (FwCfgItem);
 276   QemuFwCfgReadBytes (FwCfgSize, Value);
 277
 278   if ((FwCfgSize == 1) ||
 279       (FwCfgSize == 2 && Value[1] == '\n') ||
 280       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 281     switch (Value[0]) {
 282       case '0':
 283       case 'n':
 284       case 'N':
 285         *Setting = FALSE;
 286         return EFI_SUCCESS;
 287
 288       case '1':
 289       case 'y':
 290       case 'Y':
 291         *Setting = TRUE;
 292         return EFI_SUCCESS;
 293
 294       default:
 295         break;
 296     }
 297   }
 298   return EFI_PROTOCOL_ERROR;
 299 }
 300
 301 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 302           do {                                                      \
 303             BOOLEAN Setting;                                        \
 304                                                                     \
 305             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 306                               "opt/ovmf/" #TokenName, &Setting))) { \
 307               PcdSetBool (TokenName, Setting);                      \
 308             }                                                       \
 309           } while (0)
 310
 311 VOID
 312 NoexecDxeInitialization (
 313   VOID
 314   )
 315 {
 316   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 317   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 318 }
 319
 320 VOID
 321 MiscInitialization (
 322   VOID
 323   )
 324 {
 325   UINTN  PmCmd;
 326   UINTN  Pmba;
 327   UINTN  AcpiCtlReg;
 328   UINT8  AcpiEnBit;
 329
 330   //
 331   // Disable A20 Mask
 332   //
 333   IoOr8 (0x92, BIT1);
 334
 335   //
 336   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 337   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 338   // S3 resume as well, so we build it unconditionally.)
 339   //
 340   BuildCpuHob (mPhysMemAddressWidth, 16);
 341
 342   //
 343   // Determine platform type and save Host Bridge DID to PCD
 344   //
 345   switch (mHostBridgeDevId) {
 346     case INTEL_82441_DEVICE_ID:
 347       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 348       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 349       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 350       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 351       break;
 352     case INTEL_Q35_MCH_DEVICE_ID:
 353       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 354       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 355       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 356       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 357       break;
 358     default:
 359       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 360         __FUNCTION__, mHostBridgeDevId));
 361       ASSERT (FALSE);
 362       return;
 363   }
 364   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 365
 366   //
 367   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 368   // has been configured (e.g., by Xen) and skip the setup here.
 369   // This matches the logic in AcpiTimerLibConstructor ().
 370   //
 371   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 372     //
 373     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 374     // 1. set PMBA
 375     //
 376     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 377
 378     //
 379     // 2. set PCICMD/IOSE
 380     //
 381     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 382
 383     //
 384     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 385     //
 386     PciOr8 (AcpiCtlReg, AcpiEnBit);
 387   }
 388
 389   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 390     //
 391     // Set Root Complex Register Block BAR
 392     //
 393     PciWrite32 (
 394       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 395       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 396       );
 397   }
 398 }
 399
 400
 401 VOID
 402 BootModeInitialization (
 403   VOID
 404   )
 405 {
 406   EFI_STATUS    Status;
 407
 408   if (CmosRead8 (0xF) == 0xFE) {
 409     mBootMode = BOOT_ON_S3_RESUME;
 410   }
 411   CmosWrite8 (0xF, 0x00);
 412
 413   Status = PeiServicesSetBootMode (mBootMode);
 414   ASSERT_EFI_ERROR (Status);
 415
 416   Status = PeiServicesInstallPpi (mPpiBootMode);
 417   ASSERT_EFI_ERROR (Status);
 418 }
 419
 420
 421 VOID
 422 ReserveEmuVariableNvStore (
 423   )
 424 {
 425   EFI_PHYSICAL_ADDRESS VariableStore;
 426
 427   //
 428   // Allocate storage for NV variables early on so it will be
 429   // at a consistent address.  Since VM memory is preserved
 430   // across reboots, this allows the NV variable storage to survive
 431   // a VM reboot.
 432   //
 433   VariableStore =
 434     (EFI_PHYSICAL_ADDRESS)(UINTN)
 435       AllocateAlignedRuntimePages (
 436         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 437         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 438         );
 439   DEBUG ((EFI_D_INFO,
 440           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 441           VariableStore,
 442           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 443         ));
 444   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 445 }
 446
 447
 448 VOID
 449 DebugDumpCmos (
 450   VOID
 451   )
 452 {
 453   UINT32 Loop;
 454
 455   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 456
 457   for (Loop = 0; Loop < 0x80; Loop++) {
 458     if ((Loop % 0x10) == 0) {
 459       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 460     }
 461     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 462     if ((Loop % 0x10) == 0xf) {
 463       DEBUG ((EFI_D_INFO, "\n"));
 464     }
 465   }
 466 }
 467
 468
 469 VOID
 470 S3Verification (
 471   VOID
 472   )
 473 {
 474 #if defined (MDE_CPU_X64)
 475   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 476     DEBUG ((EFI_D_ERROR,
 477       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 478     DEBUG ((EFI_D_ERROR,
 479       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 480       __FUNCTION__));
 481     DEBUG ((EFI_D_ERROR,
 482       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 483     ASSERT (FALSE);
 484     CpuDeadLoop ();
 485   }
 486 #endif
 487 }
 488
 489
 490 /**
 491   Perform Platform PEI initialization.
 492
 493   @param  FileHandle      Handle of the file being invoked.
 494   @param  PeiServices     Describes the list of possible PEI Services.
 495
 496   @return EFI_SUCCESS     The PEIM initialized successfully.
 497
 498 **/
 499 EFI_STATUS
 500 EFIAPI
 501 InitializePlatform (
 502   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 503   IN CONST EFI_PEI_SERVICES     **PeiServices
 504   )
 505 {
 506   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 507
 508   DebugDumpCmos ();
 509
 510   XenDetect ();
 511
 512   if (QemuFwCfgS3Enabled ()) {
 513     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 514     mS3Supported = TRUE;
 515   }
 516
 517   S3Verification ();
 518   BootModeInitialization ();
 519   AddressWidthInitialization ();
 520
 521   PublishPeiMemory ();
 522
 523   InitializeRamRegions ();
 524
 525   if (mXen) {
 526     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 527     InitializeXen ();
 528   }
 529
 530   //
 531   // Query Host Bridge DID
 532   //
 533   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 534
 535   if (mBootMode != BOOT_ON_S3_RESUME) {
 536     ReserveEmuVariableNvStore ();
 537     PeiFvInitialization ();
 538     MemMapInitialization ();
 539     NoexecDxeInitialization ();
 540   }
 541
 542   MiscInitialization ();
 543
 544   return EFI_SUCCESS;
 545 }