OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 MemMapInitialization (
 156   VOID
 157   )
 158 {
 159   //
 160   // Create Memory Type Information HOB
 161   //
 162   BuildGuidDataHob (
 163     &gEfiMemoryTypeInformationGuid,
 164     mDefaultMemoryTypeInformation,
 165     sizeof(mDefaultMemoryTypeInformation)
 166     );
 167
 168   //
 169   // Add PCI IO Port space available for PCI resource allocations.
 170   //
 171   BuildResourceDescriptorHob (
 172     EFI_RESOURCE_IO,
 173     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 174     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 175     PcdGet64 (PcdPciIoBase),
 176     PcdGet64 (PcdPciIoSize)
 177     );
 178
 179   //
 180   // Video memory + Legacy BIOS region
 181   //
 182   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 183
 184   if (!mXen) {
 185     UINT32  TopOfLowRam;
 186     UINT64  PciExBarBase;
 187     UINT32  PciBase;
 188     UINT32  PciSize;
 189
 190     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 191     PciExBarBase = 0;
 192     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 193       //
 194       // The MMCONFIG area is expected to fall between the top of low RAM and
 195       // the base of the 32-bit PCI host aperture.
 196       //
 197       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 198       ASSERT (TopOfLowRam <= PciExBarBase);
 199       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 200       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 201     } else {
 202       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 203     }
 204
 205     //
 206     // address       purpose   size
 207     // ------------  --------  -------------------------
 208     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 209     // 0xFC000000    gap                           44 MB
 210     // 0xFEC00000    IO-APIC                        4 KB
 211     // 0xFEC01000    gap                         1020 KB
 212     // 0xFED00000    HPET                           1 KB
 213     // 0xFED00400    gap                          111 KB
 214     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 215     // 0xFED20000    gap                          896 KB
 216     // 0xFEE00000    LAPIC                          1 MB
 217     //
 218     PciSize = 0xFC000000 - PciBase;
 219     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 220     PcdSet64 (PcdPciMmio32Base, PciBase);
 221     PcdSet64 (PcdPciMmio32Size, PciSize);
 222     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 223     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 224     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 225       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 226       //
 227       // Note: there should be an
 228       //
 229       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 230       //
 231       // call below, just like the one above for RCBA. However, Linux insists
 232       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 233       // "reserved memory" -- Linux does not content itself with a simple gap
 234       // in the memory map wherever the MCFG ACPI table points to.
 235       //
 236       // This appears to be a safety measure. The PCI Firmware Specification
 237       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 238       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 239       // [...]". (Emphasis added here.)
 240       //
 241       // Normally we add memory resource descriptor HOBs in
 242       // QemuInitializeRam(), and pre-allocate from those with memory
 243       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 244       // is most definitely not RAM; so, as an exception, cover it with
 245       // uncacheable reserved memory right here.
 246       //
 247       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 248       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 249         EfiReservedMemoryType);
 250     }
 251     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 252   }
 253 }
 254
 255 EFI_STATUS
 256 GetNamedFwCfgBoolean (
 257   IN  CHAR8   *FwCfgFileName,
 258   OUT BOOLEAN *Setting
 259   )
 260 {
 261   EFI_STATUS           Status;
 262   FIRMWARE_CONFIG_ITEM FwCfgItem;
 263   UINTN                FwCfgSize;
 264   UINT8                Value[3];
 265
 266   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 267   if (EFI_ERROR (Status)) {
 268     return Status;
 269   }
 270   if (FwCfgSize > sizeof Value) {
 271     return EFI_BAD_BUFFER_SIZE;
 272   }
 273   QemuFwCfgSelectItem (FwCfgItem);
 274   QemuFwCfgReadBytes (FwCfgSize, Value);
 275
 276   if ((FwCfgSize == 1) ||
 277       (FwCfgSize == 2 && Value[1] == '\n') ||
 278       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 279     switch (Value[0]) {
 280       case '0':
 281       case 'n':
 282       case 'N':
 283         *Setting = FALSE;
 284         return EFI_SUCCESS;
 285
 286       case '1':
 287       case 'y':
 288       case 'Y':
 289         *Setting = TRUE;
 290         return EFI_SUCCESS;
 291
 292       default:
 293         break;
 294     }
 295   }
 296   return EFI_PROTOCOL_ERROR;
 297 }
 298
 299 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 300           do {                                                      \
 301             BOOLEAN Setting;                                        \
 302                                                                     \
 303             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 304                               "opt/ovmf/" #TokenName, &Setting))) { \
 305               PcdSetBool (TokenName, Setting);                      \
 306             }                                                       \
 307           } while (0)
 308
 309 VOID
 310 NoexecDxeInitialization (
 311   VOID
 312   )
 313 {
 314   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 315   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 316 }
 317
 318 VOID
 319 PciExBarInitialization (
 320   VOID
 321   )
 322 {
 323   union {
 324     UINT64 Uint64;
 325     UINT32 Uint32[2];
 326   } PciExBarBase;
 327
 328   //
 329   // We only support the 256MB size for the MMCONFIG area:
 330   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 331   //
 332   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 333   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 334   //
 335   // Note that (b) also ensures that the minimum address width we have
 336   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 337   // for DXE's page tables to cover the MMCONFIG area.
 338   //
 339   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 340   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 341   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 342
 343   //
 344   // Clear the PCIEXBAREN bit first, before programming the high register.
 345   //
 346   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 347
 348   //
 349   // Program the high register. Then program the low register, setting the
 350   // MMCONFIG area size and enabling decoding at once.
 351   //
 352   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 353   PciWrite32 (
 354     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 355     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 356     );
 357 }
 358
 359 VOID
 360 MiscInitialization (
 361   VOID
 362   )
 363 {
 364   UINTN  PmCmd;
 365   UINTN  Pmba;
 366   UINTN  AcpiCtlReg;
 367   UINT8  AcpiEnBit;
 368
 369   //
 370   // Disable A20 Mask
 371   //
 372   IoOr8 (0x92, BIT1);
 373
 374   //
 375   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 376   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 377   // S3 resume as well, so we build it unconditionally.)
 378   //
 379   BuildCpuHob (mPhysMemAddressWidth, 16);
 380
 381   //
 382   // Determine platform type and save Host Bridge DID to PCD
 383   //
 384   switch (mHostBridgeDevId) {
 385     case INTEL_82441_DEVICE_ID:
 386       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 387       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 388       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 389       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 390       break;
 391     case INTEL_Q35_MCH_DEVICE_ID:
 392       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 393       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 394       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 395       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 396       break;
 397     default:
 398       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 399         __FUNCTION__, mHostBridgeDevId));
 400       ASSERT (FALSE);
 401       return;
 402   }
 403   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 404
 405   //
 406   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 407   // has been configured (e.g., by Xen) and skip the setup here.
 408   // This matches the logic in AcpiTimerLibConstructor ().
 409   //
 410   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 411     //
 412     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 413     // 1. set PMBA
 414     //
 415     PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
 416
 417     //
 418     // 2. set PCICMD/IOSE
 419     //
 420     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 421
 422     //
 423     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 424     //
 425     PciOr8 (AcpiCtlReg, AcpiEnBit);
 426   }
 427
 428   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 429     //
 430     // Set Root Complex Register Block BAR
 431     //
 432     PciWrite32 (
 433       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 434       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 435       );
 436
 437     //
 438     // Set PCI Express Register Range Base Address
 439     //
 440     PciExBarInitialization ();
 441   }
 442 }
 443
 444
 445 VOID
 446 BootModeInitialization (
 447   VOID
 448   )
 449 {
 450   EFI_STATUS    Status;
 451
 452   if (CmosRead8 (0xF) == 0xFE) {
 453     mBootMode = BOOT_ON_S3_RESUME;
 454   }
 455   CmosWrite8 (0xF, 0x00);
 456
 457   Status = PeiServicesSetBootMode (mBootMode);
 458   ASSERT_EFI_ERROR (Status);
 459
 460   Status = PeiServicesInstallPpi (mPpiBootMode);
 461   ASSERT_EFI_ERROR (Status);
 462 }
 463
 464
 465 VOID
 466 ReserveEmuVariableNvStore (
 467   )
 468 {
 469   EFI_PHYSICAL_ADDRESS VariableStore;
 470
 471   //
 472   // Allocate storage for NV variables early on so it will be
 473   // at a consistent address.  Since VM memory is preserved
 474   // across reboots, this allows the NV variable storage to survive
 475   // a VM reboot.
 476   //
 477   VariableStore =
 478     (EFI_PHYSICAL_ADDRESS)(UINTN)
 479       AllocateAlignedRuntimePages (
 480         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 481         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 482         );
 483   DEBUG ((EFI_D_INFO,
 484           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 485           VariableStore,
 486           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 487         ));
 488   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 489 }
 490
 491
 492 VOID
 493 DebugDumpCmos (
 494   VOID
 495   )
 496 {
 497   UINT32 Loop;
 498
 499   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 500
 501   for (Loop = 0; Loop < 0x80; Loop++) {
 502     if ((Loop % 0x10) == 0) {
 503       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 504     }
 505     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 506     if ((Loop % 0x10) == 0xf) {
 507       DEBUG ((EFI_D_INFO, "\n"));
 508     }
 509   }
 510 }
 511
 512
 513 VOID
 514 S3Verification (
 515   VOID
 516   )
 517 {
 518 #if defined (MDE_CPU_X64)
 519   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 520     DEBUG ((EFI_D_ERROR,
 521       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 522     DEBUG ((EFI_D_ERROR,
 523       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 524       __FUNCTION__));
 525     DEBUG ((EFI_D_ERROR,
 526       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 527     ASSERT (FALSE);
 528     CpuDeadLoop ();
 529   }
 530 #endif
 531 }
 532
 533
 534 /**
 535   Perform Platform PEI initialization.
 536
 537   @param  FileHandle      Handle of the file being invoked.
 538   @param  PeiServices     Describes the list of possible PEI Services.
 539
 540   @return EFI_SUCCESS     The PEIM initialized successfully.
 541
 542 **/
 543 EFI_STATUS
 544 EFIAPI
 545 InitializePlatform (
 546   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 547   IN CONST EFI_PEI_SERVICES     **PeiServices
 548   )
 549 {
 550   EFI_STATUS    Status;
 551
 552   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 553
 554   DebugDumpCmos ();
 555
 556   XenDetect ();
 557
 558   if (QemuFwCfgS3Enabled ()) {
 559     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 560     mS3Supported = TRUE;
 561     Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
 562     ASSERT_EFI_ERROR (Status);
 563   }
 564
 565   S3Verification ();
 566   BootModeInitialization ();
 567   AddressWidthInitialization ();
 568
 569   PublishPeiMemory ();
 570
 571   InitializeRamRegions ();
 572
 573   if (mXen) {
 574     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 575     InitializeXen ();
 576   }
 577
 578   //
 579   // Query Host Bridge DID
 580   //
 581   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 582
 583   if (mBootMode != BOOT_ON_S3_RESUME) {
 584     ReserveEmuVariableNvStore ();
 585     PeiFvInitialization ();
 586     MemMapInitialization ();
 587     NoexecDxeInitialization ();
 588   }
 589
 590   MiscInitialization ();
 591
 592   return EFI_SUCCESS;
 593 }