OvmfPkg/PlatformPei/Platform.c

   1 /**@file
   2   Platform PEI driver
   3
   4   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
   6
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 //
  18 // The package level header files this module uses
  19 //
  20 #include <PiPei.h>
  21
  22 //
  23 // The Library classes this module consumes
  24 //
  25 #include <Library/BaseLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/MemoryAllocationLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/PciLib.h>
  32 #include <Library/PeimEntryPoint.h>
  33 #include <Library/PeiServicesLib.h>
  34 #include <Library/QemuFwCfgLib.h>
  35 #include <Library/ResourcePublicationLib.h>
  36 #include <Guid/MemoryTypeInformation.h>
  37 #include <Ppi/MasterBootMode.h>
  38 #include <IndustryStandard/Pci22.h>
  39 #include <OvmfPlatforms.h>
  40
  41 #include "Platform.h"
  42 #include "Cmos.h"
  43
  44 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
  45   { EfiACPIMemoryNVS,       0x004 },
  46   { EfiACPIReclaimMemory,   0x008 },
  47   { EfiReservedMemoryType,  0x004 },
  48   { EfiRuntimeServicesData, 0x024 },
  49   { EfiRuntimeServicesCode, 0x030 },
  50   { EfiBootServicesCode,    0x180 },
  51   { EfiBootServicesData,    0xF00 },
  52   { EfiMaxMemoryType,       0x000 }
  53 };
  54
  55
  56 EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
  57   {
  58     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  59     &gEfiPeiMasterBootModePpiGuid,
  60     NULL
  61   }
  62 };
  63
  64
  65 UINT16 mHostBridgeDevId;
  66
  67 EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
  68
  69 BOOLEAN mS3Supported = FALSE;
  70
  71
  72 VOID
  73 AddIoMemoryBaseSizeHob (
  74   EFI_PHYSICAL_ADDRESS        MemoryBase,
  75   UINT64                      MemorySize
  76   )
  77 {
  78   BuildResourceDescriptorHob (
  79     EFI_RESOURCE_MEMORY_MAPPED_IO,
  80       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  81       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  82       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  83       EFI_RESOURCE_ATTRIBUTE_TESTED,
  84     MemoryBase,
  85     MemorySize
  86     );
  87 }
  88
  89 VOID
  90 AddReservedMemoryBaseSizeHob (
  91   EFI_PHYSICAL_ADDRESS        MemoryBase,
  92   UINT64                      MemorySize,
  93   BOOLEAN                     Cacheable
  94   )
  95 {
  96   BuildResourceDescriptorHob (
  97     EFI_RESOURCE_MEMORY_RESERVED,
  98       EFI_RESOURCE_ATTRIBUTE_PRESENT     |
  99       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 100       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 101       (Cacheable ?
 102        EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 103        EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 104        EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :
 105        0
 106        ) |
 107       EFI_RESOURCE_ATTRIBUTE_TESTED,
 108     MemoryBase,
 109     MemorySize
 110     );
 111 }
 112
 113 VOID
 114 AddIoMemoryRangeHob (
 115   EFI_PHYSICAL_ADDRESS        MemoryBase,
 116   EFI_PHYSICAL_ADDRESS        MemoryLimit
 117   )
 118 {
 119   AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 120 }
 121
 122
 123 VOID
 124 AddMemoryBaseSizeHob (
 125   EFI_PHYSICAL_ADDRESS        MemoryBase,
 126   UINT64                      MemorySize
 127   )
 128 {
 129   BuildResourceDescriptorHob (
 130     EFI_RESOURCE_SYSTEM_MEMORY,
 131       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 132       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 133       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 134       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 135       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 136       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
 137       EFI_RESOURCE_ATTRIBUTE_TESTED,
 138     MemoryBase,
 139     MemorySize
 140     );
 141 }
 142
 143
 144 VOID
 145 AddMemoryRangeHob (
 146   EFI_PHYSICAL_ADDRESS        MemoryBase,
 147   EFI_PHYSICAL_ADDRESS        MemoryLimit
 148   )
 149 {
 150   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 151 }
 152
 153
 154 VOID
 155 AddUntestedMemoryBaseSizeHob (
 156   EFI_PHYSICAL_ADDRESS        MemoryBase,
 157   UINT64                      MemorySize
 158   )
 159 {
 160   BuildResourceDescriptorHob (
 161     EFI_RESOURCE_SYSTEM_MEMORY,
 162       EFI_RESOURCE_ATTRIBUTE_PRESENT |
 163       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
 164       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
 165       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
 166       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
 167       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
 168     MemoryBase,
 169     MemorySize
 170     );
 171 }
 172
 173
 174 VOID
 175 AddUntestedMemoryRangeHob (
 176   EFI_PHYSICAL_ADDRESS        MemoryBase,
 177   EFI_PHYSICAL_ADDRESS        MemoryLimit
 178   )
 179 {
 180   AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 181 }
 182
 183 VOID
 184 MemMapInitialization (
 185   VOID
 186   )
 187 {
 188   //
 189   // Create Memory Type Information HOB
 190   //
 191   BuildGuidDataHob (
 192     &gEfiMemoryTypeInformationGuid,
 193     mDefaultMemoryTypeInformation,
 194     sizeof(mDefaultMemoryTypeInformation)
 195     );
 196
 197   //
 198   // Add PCI IO Port space available for PCI resource allocations.
 199   //
 200   BuildResourceDescriptorHob (
 201     EFI_RESOURCE_IO,
 202     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
 203     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
 204     PcdGet64 (PcdPciIoBase),
 205     PcdGet64 (PcdPciIoSize)
 206     );
 207
 208   //
 209   // Video memory + Legacy BIOS region
 210   //
 211   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 212
 213   if (!mXen) {
 214     UINT32  TopOfLowRam;
 215     UINT64  PciExBarBase;
 216     UINT32  PciBase;
 217     UINT32  PciSize;
 218
 219     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
 220     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 221       //
 222       // The MMCONFIG area is expected to fall between the top of low RAM and
 223       // the base of the 32-bit PCI host aperture.
 224       //
 225       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
 226       ASSERT (TopOfLowRam <= PciExBarBase);
 227       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
 228       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
 229     } else {
 230       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
 231     }
 232
 233     //
 234     // address       purpose   size
 235     // ------------  --------  -------------------------
 236     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
 237     // 0xFC000000    gap                           44 MB
 238     // 0xFEC00000    IO-APIC                        4 KB
 239     // 0xFEC01000    gap                         1020 KB
 240     // 0xFED00000    HPET                           1 KB
 241     // 0xFED00400    gap                          111 KB
 242     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
 243     // 0xFED20000    gap                          896 KB
 244     // 0xFEE00000    LAPIC                          1 MB
 245     //
 246     PciSize = 0xFC000000 - PciBase;
 247     AddIoMemoryBaseSizeHob (PciBase, PciSize);
 248     PcdSet64 (PcdPciMmio32Base, PciBase);
 249     PcdSet64 (PcdPciMmio32Size, PciSize);
 250     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
 251     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
 252     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 253       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
 254       //
 255       // Note: there should be an
 256       //
 257       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
 258       //
 259       // call below, just like the one above for RCBA. However, Linux insists
 260       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
 261       // "reserved memory" -- Linux does not content itself with a simple gap
 262       // in the memory map wherever the MCFG ACPI table points to.
 263       //
 264       // This appears to be a safety measure. The PCI Firmware Specification
 265       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
 266       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
 267       // [...]". (Emphasis added here.)
 268       //
 269       // Normally we add memory resource descriptor HOBs in
 270       // QemuInitializeRam(), and pre-allocate from those with memory
 271       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
 272       // is most definitely not RAM; so, as an exception, cover it with
 273       // uncacheable reserved memory right here.
 274       //
 275       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
 276       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
 277         EfiReservedMemoryType);
 278     }
 279     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
 280   }
 281 }
 282
 283 EFI_STATUS
 284 GetNamedFwCfgBoolean (
 285   IN  CHAR8   *FwCfgFileName,
 286   OUT BOOLEAN *Setting
 287   )
 288 {
 289   EFI_STATUS           Status;
 290   FIRMWARE_CONFIG_ITEM FwCfgItem;
 291   UINTN                FwCfgSize;
 292   UINT8                Value[3];
 293
 294   Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);
 295   if (EFI_ERROR (Status)) {
 296     return Status;
 297   }
 298   if (FwCfgSize > sizeof Value) {
 299     return EFI_BAD_BUFFER_SIZE;
 300   }
 301   QemuFwCfgSelectItem (FwCfgItem);
 302   QemuFwCfgReadBytes (FwCfgSize, Value);
 303
 304   if ((FwCfgSize == 1) ||
 305       (FwCfgSize == 2 && Value[1] == '\n') ||
 306       (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {
 307     switch (Value[0]) {
 308       case '0':
 309       case 'n':
 310       case 'N':
 311         *Setting = FALSE;
 312         return EFI_SUCCESS;
 313
 314       case '1':
 315       case 'y':
 316       case 'Y':
 317         *Setting = TRUE;
 318         return EFI_SUCCESS;
 319
 320       default:
 321         break;
 322     }
 323   }
 324   return EFI_PROTOCOL_ERROR;
 325 }
 326
 327 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName)                   \
 328           do {                                                      \
 329             BOOLEAN Setting;                                        \
 330                                                                     \
 331             if (!EFI_ERROR (GetNamedFwCfgBoolean (                  \
 332                               "opt/ovmf/" #TokenName, &Setting))) { \
 333               PcdSetBool (TokenName, Setting);                      \
 334             }                                                       \
 335           } while (0)
 336
 337 VOID
 338 NoexecDxeInitialization (
 339   VOID
 340   )
 341 {
 342   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);
 343   UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);
 344 }
 345
 346 VOID
 347 PciExBarInitialization (
 348   VOID
 349   )
 350 {
 351   union {
 352     UINT64 Uint64;
 353     UINT32 Uint32[2];
 354   } PciExBarBase;
 355
 356   //
 357   // We only support the 256MB size for the MMCONFIG area:
 358   // 256 buses * 32 devices * 8 functions * 4096 bytes config space.
 359   //
 360   // The masks used below enforce the Q35 requirements that the MMCONFIG area
 361   // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.
 362   //
 363   // Note that (b) also ensures that the minimum address width we have
 364   // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice
 365   // for DXE's page tables to cover the MMCONFIG area.
 366   //
 367   PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);
 368   ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);
 369   ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);
 370
 371   //
 372   // Clear the PCIEXBAREN bit first, before programming the high register.
 373   //
 374   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
 375
 376   //
 377   // Program the high register. Then program the low register, setting the
 378   // MMCONFIG area size and enabling decoding at once.
 379   //
 380   PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);
 381   PciWrite32 (
 382     DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
 383     PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN
 384     );
 385 }
 386
 387 VOID
 388 MiscInitialization (
 389   VOID
 390   )
 391 {
 392   UINTN  PmCmd;
 393   UINTN  Pmba;
 394   UINTN  AcpiCtlReg;
 395   UINT8  AcpiEnBit;
 396
 397   //
 398   // Disable A20 Mask
 399   //
 400   IoOr8 (0x92, BIT1);
 401
 402   //
 403   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
 404   // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
 405   // S3 resume as well, so we build it unconditionally.)
 406   //
 407   BuildCpuHob (mPhysMemAddressWidth, 16);
 408
 409   //
 410   // Determine platform type and save Host Bridge DID to PCD
 411   //
 412   switch (mHostBridgeDevId) {
 413     case INTEL_82441_DEVICE_ID:
 414       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
 415       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
 416       AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
 417       AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
 418       break;
 419     case INTEL_Q35_MCH_DEVICE_ID:
 420       PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
 421       Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
 422       AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
 423       AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
 424       break;
 425     default:
 426       DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
 427         __FUNCTION__, mHostBridgeDevId));
 428       ASSERT (FALSE);
 429       return;
 430   }
 431   PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
 432
 433   //
 434   // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
 435   // has been configured (e.g., by Xen) and skip the setup here.
 436   // This matches the logic in AcpiTimerLibConstructor ().
 437   //
 438   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
 439     //
 440     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
 441     // 1. set PMBA
 442     //
 443     PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 444
 445     //
 446     // 2. set PCICMD/IOSE
 447     //
 448     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 449
 450     //
 451     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
 452     //
 453     PciOr8 (AcpiCtlReg, AcpiEnBit);
 454   }
 455
 456   if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
 457     //
 458     // Set Root Complex Register Block BAR
 459     //
 460     PciWrite32 (
 461       POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
 462       ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
 463       );
 464
 465     //
 466     // Set PCI Express Register Range Base Address
 467     //
 468     PciExBarInitialization ();
 469   }
 470 }
 471
 472
 473 VOID
 474 BootModeInitialization (
 475   VOID
 476   )
 477 {
 478   EFI_STATUS    Status;
 479
 480   if (CmosRead8 (0xF) == 0xFE) {
 481     mBootMode = BOOT_ON_S3_RESUME;
 482   }
 483   CmosWrite8 (0xF, 0x00);
 484
 485   Status = PeiServicesSetBootMode (mBootMode);
 486   ASSERT_EFI_ERROR (Status);
 487
 488   Status = PeiServicesInstallPpi (mPpiBootMode);
 489   ASSERT_EFI_ERROR (Status);
 490 }
 491
 492
 493 VOID
 494 ReserveEmuVariableNvStore (
 495   )
 496 {
 497   EFI_PHYSICAL_ADDRESS VariableStore;
 498
 499   //
 500   // Allocate storage for NV variables early on so it will be
 501   // at a consistent address.  Since VM memory is preserved
 502   // across reboots, this allows the NV variable storage to survive
 503   // a VM reboot.
 504   //
 505   VariableStore =
 506     (EFI_PHYSICAL_ADDRESS)(UINTN)
 507       AllocateAlignedRuntimePages (
 508         EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
 509         PcdGet32 (PcdFlashNvStorageFtwSpareSize)
 510         );
 511   DEBUG ((EFI_D_INFO,
 512           "Reserved variable store memory: 0x%lX; size: %dkb\n",
 513           VariableStore,
 514           (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024
 515         ));
 516   PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);
 517 }
 518
 519
 520 VOID
 521 DebugDumpCmos (
 522   VOID
 523   )
 524 {
 525   UINT32 Loop;
 526
 527   DEBUG ((EFI_D_INFO, "CMOS:\n"));
 528
 529   for (Loop = 0; Loop < 0x80; Loop++) {
 530     if ((Loop % 0x10) == 0) {
 531       DEBUG ((EFI_D_INFO, "%02x:", Loop));
 532     }
 533     DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));
 534     if ((Loop % 0x10) == 0xf) {
 535       DEBUG ((EFI_D_INFO, "\n"));
 536     }
 537   }
 538 }
 539
 540
 541 VOID
 542 S3Verification (
 543   VOID
 544   )
 545 {
 546 #if defined (MDE_CPU_X64)
 547   if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {
 548     DEBUG ((EFI_D_ERROR,
 549       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));
 550     DEBUG ((EFI_D_ERROR,
 551       "%a: Please disable S3 on the QEMU command line (see the README),\n",
 552       __FUNCTION__));
 553     DEBUG ((EFI_D_ERROR,
 554       "%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));
 555     ASSERT (FALSE);
 556     CpuDeadLoop ();
 557   }
 558 #endif
 559 }
 560
 561
 562 /**
 563   Perform Platform PEI initialization.
 564
 565   @param  FileHandle      Handle of the file being invoked.
 566   @param  PeiServices     Describes the list of possible PEI Services.
 567
 568   @return EFI_SUCCESS     The PEIM initialized successfully.
 569
 570 **/
 571 EFI_STATUS
 572 EFIAPI
 573 InitializePlatform (
 574   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 575   IN CONST EFI_PEI_SERVICES     **PeiServices
 576   )
 577 {
 578   DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
 579
 580   DebugDumpCmos ();
 581
 582   XenDetect ();
 583
 584   if (QemuFwCfgS3Enabled ()) {
 585     DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
 586     mS3Supported = TRUE;
 587   }
 588
 589   S3Verification ();
 590   BootModeInitialization ();
 591   AddressWidthInitialization ();
 592
 593   PublishPeiMemory ();
 594
 595   InitializeRamRegions ();
 596
 597   if (mXen) {
 598     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
 599     InitializeXen ();
 600   }
 601
 602   //
 603   // Query Host Bridge DID
 604   //
 605   mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
 606
 607   if (mBootMode != BOOT_ON_S3_RESUME) {
 608     ReserveEmuVariableNvStore ();
 609     PeiFvInitialization ();
 610     MemMapInitialization ();
 611     NoexecDxeInitialization ();
 612   }
 613
 614   MiscInitialization ();
 615
 616   return EFI_SUCCESS;
 617 }