PcAtChipsetPkg: Clean up source files
[mirror_edk2.git] / PcAtChipsetPkg / Include / Register / Hpet.h
1 /** @file
2 HPET register definitions from the IA-PC HPET (High Precision Event Timers)
3 Specification, Revision 1.0a, October 2004.
4
5 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef __HPET_REGISTER_H__
17 #define __HPET_REGISTER_H__
18
19 ///
20 /// HPET General Register Offsets
21 ///
22 #define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
23 #define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
24 #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
25
26 ///
27 /// HPET Timer Register Offsets
28 ///
29 #define HPET_MAIN_COUNTER_OFFSET 0x0F0
30 #define HPET_TIMER_CONFIGURATION_OFFSET 0x100
31 #define HPET_TIMER_COMPARATOR_OFFSET 0x108
32 #define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
33
34 ///
35 /// Stride between sets of HPET Timer Registers
36 ///
37 #define HPET_TIMER_STRIDE 0x20
38
39 #pragma pack(1)
40
41 ///
42 /// HPET General Capabilities and ID Register
43 ///
44 typedef union {
45 struct {
46 UINT32 Revision:8;
47 UINT32 NumberOfTimers:5;
48 UINT32 CounterSize:1;
49 UINT32 Reserved0:1;
50 UINT32 LegacyRoute:1;
51 UINT32 VendorId:16;
52 UINT32 CounterClockPeriod:32;
53 } Bits;
54 UINT64 Uint64;
55 } HPET_GENERAL_CAPABILITIES_ID_REGISTER;
56
57 ///
58 /// HPET General Configuration Register
59 ///
60 typedef union {
61 struct {
62 UINT32 MainCounterEnable:1;
63 UINT32 LegacyRouteEnable:1;
64 UINT32 Reserved0:30;
65 UINT32 Reserved1:32;
66 } Bits;
67 UINT64 Uint64;
68 } HPET_GENERAL_CONFIGURATION_REGISTER;
69
70 ///
71 /// HPET Timer Configuration Register
72 ///
73 typedef union {
74 struct {
75 UINT32 Reserved0:1;
76 UINT32 LevelTriggeredInterrupt:1;
77 UINT32 InterruptEnable:1;
78 UINT32 PeriodicInterruptEnable:1;
79 UINT32 PeriodicInterruptCapablity:1;
80 UINT32 CounterSizeCapablity:1;
81 UINT32 ValueSetEnable:1;
82 UINT32 Reserved1:1;
83 UINT32 CounterSizeEnable:1;
84 UINT32 InterruptRoute:5;
85 UINT32 MsiInterruptEnable:1;
86 UINT32 MsiInterruptCapablity:1;
87 UINT32 Reserved2:16;
88 UINT32 InterruptRouteCapability;
89 } Bits;
90 UINT64 Uint64;
91 } HPET_TIMER_CONFIGURATION_REGISTER;
92
93 ///
94 /// HPET Timer MSI Route Register
95 ///
96 typedef union {
97 struct {
98 UINT32 Value:32;
99 UINT32 Address:32;
100 } Bits;
101 UINT64 Uint64;
102 } HPET_TIMER_MSI_ROUTE_REGISTER;
103
104 #pragma pack()
105
106 #endif