2 Main file for Pci shell Debug1 function.
4 (C) Copyright 2013-2014 Hewlett-Packard Development Company, L.P.
5 Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "UefiShellDebug1CommandsLib.h"
17 #include <Protocol/PciRootBridgeIo.h>
18 #include <Library/ShellLib.h>
19 #include <IndustryStandard/Pci.h>
20 #include <IndustryStandard/Acpi.h>
24 // Printable strings for Pci class code
27 CHAR16
*BaseClass
; // Pointer to the PCI base class string
28 CHAR16
*SubClass
; // Pointer to the PCI sub class string
29 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
33 // a structure holding a single entry, which also points to its lower level
36 typedef struct PCI_CLASS_ENTRY_TAG
{
37 UINT8 Code
; // Class, subclass or I/F code
38 CHAR16
*DescText
; // Description string
39 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
43 // Declarations of entries which contain printable strings for class codes
44 // in PCI configuration space
46 PCI_CLASS_ENTRY PCIBlankEntry
[];
47 PCI_CLASS_ENTRY PCISubClass_00
[];
48 PCI_CLASS_ENTRY PCISubClass_01
[];
49 PCI_CLASS_ENTRY PCISubClass_02
[];
50 PCI_CLASS_ENTRY PCISubClass_03
[];
51 PCI_CLASS_ENTRY PCISubClass_04
[];
52 PCI_CLASS_ENTRY PCISubClass_05
[];
53 PCI_CLASS_ENTRY PCISubClass_06
[];
54 PCI_CLASS_ENTRY PCISubClass_07
[];
55 PCI_CLASS_ENTRY PCISubClass_08
[];
56 PCI_CLASS_ENTRY PCISubClass_09
[];
57 PCI_CLASS_ENTRY PCISubClass_0a
[];
58 PCI_CLASS_ENTRY PCISubClass_0b
[];
59 PCI_CLASS_ENTRY PCISubClass_0c
[];
60 PCI_CLASS_ENTRY PCISubClass_0d
[];
61 PCI_CLASS_ENTRY PCISubClass_0e
[];
62 PCI_CLASS_ENTRY PCISubClass_0f
[];
63 PCI_CLASS_ENTRY PCISubClass_10
[];
64 PCI_CLASS_ENTRY PCISubClass_11
[];
65 PCI_CLASS_ENTRY PCISubClass_12
[];
66 PCI_CLASS_ENTRY PCISubClass_13
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0100
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0105
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0106
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0107
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0108
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0109
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0609
[];
77 PCI_CLASS_ENTRY PCIPIFClass_060b
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
80 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
81 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
82 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
83 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
84 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
85 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
86 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
87 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
88 PCI_CLASS_ENTRY PCIPIFClass_0c07
[];
89 PCI_CLASS_ENTRY PCIPIFClass_0d01
[];
90 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
93 // Base class strings entries
95 PCI_CLASS_ENTRY gClassStringList
[] = {
103 L
"Mass Storage Controller",
108 L
"Network Controller",
113 L
"Display Controller",
118 L
"Multimedia Device",
123 L
"Memory Controller",
133 L
"Simple Communications Controllers",
138 L
"Base System Peripherals",
158 L
"Serial Bus Controllers",
163 L
"Wireless Controllers",
168 L
"Intelligent IO Controllers",
173 L
"Satellite Communications Controllers",
178 L
"Encryption/Decryption Controllers",
183 L
"Data Acquisition & Signal Processing Controllers",
188 L
"Processing Accelerators",
193 L
"Non-Essential Instrumentation",
198 L
"Device does not fit in any defined classes",
204 /* null string ends the list */NULL
209 // Subclass strings entries
211 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
220 /* null string ends the list */NULL
224 PCI_CLASS_ENTRY PCISubClass_00
[] = {
227 L
"All devices other than VGA",
232 L
"VGA-compatible devices",
238 /* null string ends the list */NULL
242 PCI_CLASS_ENTRY PCISubClass_01
[] = {
255 L
"Floppy disk controller",
270 L
"ATA controller with ADMA interface",
275 L
"Serial ATA controller",
280 L
"Serial Attached SCSI (SAS) controller ",
285 L
"Non-volatile memory subsystem",
290 L
"Universal Flash Storage (UFS) controller ",
295 L
"Other mass storage controller",
301 /* null string ends the list */NULL
305 PCI_CLASS_ENTRY PCISubClass_02
[] = {
308 L
"Ethernet controller",
313 L
"Token ring controller",
333 L
"WorldFip controller",
338 L
"PICMG 2.14 Multi Computing",
343 L
"InfiniBand controller",
348 L
"Other network controller",
354 /* null string ends the list */NULL
358 PCI_CLASS_ENTRY PCISubClass_03
[] = {
361 L
"VGA/8514 controller",
376 L
"Other display controller",
382 /* null string ends the list */PCIBlankEntry
386 PCI_CLASS_ENTRY PCISubClass_04
[] = {
399 L
"Computer Telephony device",
404 L
"Mixed mode device",
409 L
"Other multimedia device",
415 /* null string ends the list */NULL
419 PCI_CLASS_ENTRY PCISubClass_05
[] = {
422 L
"RAM memory controller",
427 L
"Flash memory controller",
432 L
"Other memory controller",
438 /* null string ends the list */NULL
442 PCI_CLASS_ENTRY PCISubClass_06
[] = {
460 L
"PCI/Micro Channel bridge",
470 L
"PCI/PCMCIA bridge",
490 L
"Semi-transparent PCI-to-PCI bridge",
495 L
"InfiniBand-to-PCI host bridge",
500 L
"Advanced Switching to PCI host bridge",
505 L
"Other bridge type",
511 /* null string ends the list */NULL
515 PCI_CLASS_ENTRY PCISubClass_07
[] = {
518 L
"Serial controller",
528 L
"Multiport serial controller",
538 L
"GPIB (IEEE 488.1/2) controller",
548 L
"Other communication device",
554 /* null string ends the list */NULL
558 PCI_CLASS_ENTRY PCISubClass_08
[] = {
581 L
"Generic PCI Hot-Plug controller",
586 L
"SD Host controller",
596 L
"Root Complex Event Collector",
601 L
"Other system peripheral",
607 /* null string ends the list */NULL
611 PCI_CLASS_ENTRY PCISubClass_09
[] = {
614 L
"Keyboard controller",
629 L
"Scanner controller",
634 L
"Gameport controller",
639 L
"Other input controller",
645 /* null string ends the list */NULL
649 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
652 L
"Generic docking station",
657 L
"Other type of docking station",
663 /* null string ends the list */NULL
667 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
711 /* null string ends the list */NULL
715 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
743 L
"System Management Bus",
758 L
"SERCOS Interface Standard (IEC 61491)",
774 /* null string ends the list */NULL
778 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
781 L
"iRDA compatible controller",
806 L
"Ethernet (802.11a - 5 GHz)",
811 L
"Ethernet (802.11b - 2.4 GHz)",
816 L
"Other type of wireless controller",
822 /* null string ends the list */NULL
826 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
835 /* null string ends the list */NULL
839 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
862 L
"Other satellite communication controller",
868 /* null string ends the list */NULL
872 PCI_CLASS_ENTRY PCISubClass_10
[] = {
875 L
"Network & computing Encrypt/Decrypt",
880 L
"Entertainment Encrypt/Decrypt",
885 L
"Other Encrypt/Decrypt",
891 /* null string ends the list */NULL
895 PCI_CLASS_ENTRY PCISubClass_11
[] = {
903 L
"Performance Counters",
908 L
"Communications synchronization plus time and frequency test/measurement ",
918 L
"Other DAQ & SP controllers",
924 /* null string ends the list */NULL
928 PCI_CLASS_ENTRY PCISubClass_12
[] = {
931 L
"Processing Accelerator",
937 /* null string ends the list */NULL
941 PCI_CLASS_ENTRY PCISubClass_13
[] = {
944 L
"Non-Essential Instrumentation Function",
950 /* null string ends the list */NULL
955 // Programming Interface entries
957 PCI_CLASS_ENTRY PCIPIFClass_0100
[] = {
965 L
"SCSI storage device SOP using PQI",
970 L
"SCSI controller SOP using PQI",
975 L
"SCSI storage device and controller SOP using PQI",
980 L
"SCSI storage device SOP using NVMe",
986 /* null string ends the list */NULL
990 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
1018 L
"OM-primary, OM-secondary",
1023 L
"PI-primary, OM-secondary",
1028 L
"OM/PI-primary, OM-secondary",
1038 L
"OM-primary, PI-secondary",
1043 L
"PI-primary, PI-secondary",
1048 L
"OM/PI-primary, PI-secondary",
1058 L
"OM-primary, OM/PI-secondary",
1063 L
"PI-primary, OM/PI-secondary",
1068 L
"OM/PI-primary, OM/PI-secondary",
1078 L
"Master, OM-primary",
1083 L
"Master, PI-primary",
1088 L
"Master, OM/PI-primary",
1093 L
"Master, OM-secondary",
1098 L
"Master, OM-primary, OM-secondary",
1103 L
"Master, PI-primary, OM-secondary",
1108 L
"Master, OM/PI-primary, OM-secondary",
1113 L
"Master, OM-secondary",
1118 L
"Master, OM-primary, PI-secondary",
1123 L
"Master, PI-primary, PI-secondary",
1128 L
"Master, OM/PI-primary, PI-secondary",
1133 L
"Master, OM-secondary",
1138 L
"Master, OM-primary, OM/PI-secondary",
1143 L
"Master, PI-primary, OM/PI-secondary",
1148 L
"Master, OM/PI-primary, OM/PI-secondary",
1154 /* null string ends the list */NULL
1158 PCI_CLASS_ENTRY PCIPIFClass_0105
[] = {
1166 L
"Continuous operation",
1172 /* null string ends the list */NULL
1176 PCI_CLASS_ENTRY PCIPIFClass_0106
[] = {
1189 L
"Serial Storage Bus",
1195 /* null string ends the list */NULL
1199 PCI_CLASS_ENTRY PCIPIFClass_0107
[] = {
1213 /* null string ends the list */NULL
1217 PCI_CLASS_ENTRY PCIPIFClass_0108
[] = {
1236 /* null string ends the list */NULL
1240 PCI_CLASS_ENTRY PCIPIFClass_0109
[] = {
1254 /* null string ends the list */NULL
1258 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
1272 /* null string ends the list */NULL
1276 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
1284 L
"Subtractive decode",
1290 /* null string ends the list */NULL
1294 PCI_CLASS_ENTRY PCIPIFClass_0609
[] = {
1297 L
"Primary PCI bus side facing the system host processor",
1302 L
"Secondary PCI bus side facing the system host processor",
1308 /* null string ends the list */NULL
1312 PCI_CLASS_ENTRY PCIPIFClass_060b
[] = {
1320 L
"ASI-SIG Defined Portal",
1326 /* null string ends the list */NULL
1330 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
1333 L
"Generic XT-compatible",
1338 L
"16450-compatible",
1343 L
"16550-compatible",
1348 L
"16650-compatible",
1353 L
"16750-compatible",
1358 L
"16850-compatible",
1363 L
"16950-compatible",
1369 /* null string ends the list */NULL
1373 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1386 L
"ECP 1.X-compliant",
1396 L
"IEEE 1284 target (not a controller)",
1402 /* null string ends the list */NULL
1406 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1414 L
"Hayes-compatible 16450",
1419 L
"Hayes-compatible 16550",
1424 L
"Hayes-compatible 16650",
1429 L
"Hayes-compatible 16750",
1435 /* null string ends the list */NULL
1439 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1462 L
"IO(x) APIC interrupt controller",
1468 /* null string ends the list */NULL
1472 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1491 /* null string ends the list */NULL
1495 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1514 /* null string ends the list */NULL
1518 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1537 /* null string ends the list */NULL
1541 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1555 /* null string ends the list */NULL
1559 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1567 L
"Using 1394 OpenHCI spec",
1573 /* null string ends the list */NULL
1577 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1600 L
"No specific programming interface",
1605 L
"(Not Host Controller)",
1611 /* null string ends the list */NULL
1615 PCI_CLASS_ENTRY PCIPIFClass_0c07
[] = {
1623 L
"Keyboard Controller Style",
1634 /* null string ends the list */NULL
1638 PCI_CLASS_ENTRY PCIPIFClass_0d01
[] = {
1641 L
"Consumer IR controller",
1646 L
"UWB Radio controller",
1652 /* null string ends the list */NULL
1656 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1659 L
"Message FIFO at offset 40h",
1670 /* null string ends the list */NULL
1676 Generates printable Unicode strings that represent PCI device class,
1677 subclass and programmed I/F based on a value passed to the function.
1679 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1680 PCI device. The encodings are:
1681 bits 23:16 - Base Class Code
1682 bits 15:8 - Sub-Class Code
1683 bits 7:0 - Programming Interface
1684 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1685 printable class strings corresponding to ClassCode. The
1686 caller must not modify the strings that are pointed by
1687 the fields in ClassStrings.
1690 PciGetClassStrings (
1691 IN UINT32 ClassCode
,
1692 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1697 PCI_CLASS_ENTRY
*CurrentClass
;
1700 // Assume no strings found
1702 ClassStrings
->BaseClass
= L
"UNDEFINED";
1703 ClassStrings
->SubClass
= L
"UNDEFINED";
1704 ClassStrings
->PIFClass
= L
"UNDEFINED";
1706 CurrentClass
= gClassStringList
;
1707 Code
= (UINT8
) (ClassCode
>> 16);
1711 // Go through all entries of the base class, until the entry with a matching
1712 // base class code is found. If reaches an entry with a null description
1713 // text, the last entry is met, which means no text for the base class was
1714 // found, so no more action is needed.
1716 while (Code
!= CurrentClass
[Index
].Code
) {
1717 if (NULL
== CurrentClass
[Index
].DescText
) {
1724 // A base class was found. Assign description, and check if this class has
1725 // sub-class defined. If sub-class defined, no more action is needed,
1726 // otherwise, continue to find description for the sub-class code.
1728 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1729 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1733 // find Subclass entry
1735 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1736 Code
= (UINT8
) (ClassCode
>> 8);
1740 // Go through all entries of the sub-class, until the entry with a matching
1741 // sub-class code is found. If reaches an entry with a null description
1742 // text, the last entry is met, which means no text for the sub-class was
1743 // found, so no more action is needed.
1745 while (Code
!= CurrentClass
[Index
].Code
) {
1746 if (NULL
== CurrentClass
[Index
].DescText
) {
1753 // A class was found for the sub-class code. Assign description, and check if
1754 // this sub-class has programming interface defined. If no, no more action is
1755 // needed, otherwise, continue to find description for the programming
1758 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1759 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1763 // Find programming interface entry
1765 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1766 Code
= (UINT8
) ClassCode
;
1770 // Go through all entries of the I/F entries, until the entry with a
1771 // matching I/F code is found. If reaches an entry with a null description
1772 // text, the last entry is met, which means no text was found, so no more
1773 // action is needed.
1775 while (Code
!= CurrentClass
[Index
].Code
) {
1776 if (NULL
== CurrentClass
[Index
].DescText
) {
1783 // A class was found for the I/F code. Assign description, done!
1785 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1790 Print strings that represent PCI device class, subclass and programmed I/F.
1792 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1793 configuration space.
1794 @param[in] IncludePIF If the printed string should include the programming I/F part
1798 IN UINT8
*ClassCodePtr
,
1799 IN BOOLEAN IncludePIF
1803 PCI_CLASS_STRINGS ClassStrings
;
1806 ClassCode
|= (UINT32
)ClassCodePtr
[0];
1807 ClassCode
|= (UINT32
)(ClassCodePtr
[1] << 8);
1808 ClassCode
|= (UINT32
)(ClassCodePtr
[2] << 16);
1811 // Get name from class code
1813 PciGetClassStrings (ClassCode
, &ClassStrings
);
1817 // Print base class, sub class, and programming inferface name
1819 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1820 ClassStrings
.BaseClass
,
1821 ClassStrings
.SubClass
,
1822 ClassStrings
.PIFClass
1827 // Only print base class and sub class name
1829 ShellPrintEx (-1, -1, L
"%s - %s",
1830 ClassStrings
.BaseClass
,
1831 ClassStrings
.SubClass
1837 This function finds out the protocol which is in charge of the given
1838 segment, and its bus range covers the current bus number. It lookes
1839 each instances of RootBridgeIoProtocol handle, until the one meets the
1842 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1843 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1844 @param[in] Segment Segment number of device we are dealing with.
1845 @param[in] Bus Bus number of device we are dealing with.
1846 @param[out] IoDev Handle used to access configuration space of PCI device.
1848 @retval EFI_SUCCESS The command completed successfully.
1849 @retval EFI_INVALID_PARAMETER Invalid parameter.
1853 PciFindProtocolInterface (
1854 IN EFI_HANDLE
*HandleBuf
,
1855 IN UINTN HandleCount
,
1858 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1862 This function gets the protocol interface from the given handle, and
1863 obtains its address space descriptors.
1865 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1866 @param[out] IoDev Handle used to access configuration space of PCI device.
1867 @param[out] Descriptors Points to the address space descriptors.
1869 @retval EFI_SUCCESS The command completed successfully
1872 PciGetProtocolAndResource (
1873 IN EFI_HANDLE Handle
,
1874 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1875 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1879 This function get the next bus range of given address space descriptors.
1880 It also moves the pointer backward a node, to get prepared to be called
1883 @param[in, out] Descriptors Points to current position of a serial of address space
1885 @param[out] MinBus The lower range of bus number.
1886 @param[out] MaxBus The upper range of bus number.
1887 @param[out] IsEnd Meet end of the serial of descriptors.
1889 @retval EFI_SUCCESS The command completed successfully.
1892 PciGetNextBusRange (
1893 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1900 Explain the data in PCI configuration space. The part which is common for
1901 PCI device and bridge is interpreted in this function. It calls other
1902 functions to interpret data unique for device or bridge.
1904 @param[in] ConfigSpace Data in PCI configuration space.
1905 @param[in] Address Address used to access configuration space of this PCI device.
1906 @param[in] IoDev Handle used to access configuration space of PCI device.
1907 @param[in] EnhancedDump The print format for the dump data.
1909 @retval EFI_SUCCESS The command completed successfully.
1913 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1915 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1916 IN CONST UINT16 EnhancedDump
1920 Explain the device specific part of data in PCI configuration space.
1922 @param[in] Device Data in PCI configuration space.
1923 @param[in] Address Address used to access configuration space of this PCI device.
1924 @param[in] IoDev Handle used to access configuration space of PCI device.
1926 @retval EFI_SUCCESS The command completed successfully.
1929 PciExplainDeviceData (
1930 IN PCI_DEVICE_HEADER
*Device
,
1932 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1936 Explain the bridge specific part of data in PCI configuration space.
1938 @param[in] Bridge Bridge specific data region in PCI configuration space.
1939 @param[in] Address Address used to access configuration space of this PCI device.
1940 @param[in] IoDev Handle used to access configuration space of PCI device.
1942 @retval EFI_SUCCESS The command completed successfully.
1945 PciExplainBridgeData (
1946 IN PCI_BRIDGE_HEADER
*Bridge
,
1948 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1952 Explain the Base Address Register(Bar) in PCI configuration space.
1954 @param[in] Bar Points to the Base Address Register intended to interpret.
1955 @param[in] Command Points to the register Command.
1956 @param[in] Address Address used to access configuration space of this PCI device.
1957 @param[in] IoDev Handle used to access configuration space of PCI device.
1958 @param[in, out] Index The Index.
1960 @retval EFI_SUCCESS The command completed successfully.
1967 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1972 Explain the cardbus specific part of data in PCI configuration space.
1974 @param[in] CardBus CardBus specific region of PCI configuration space.
1975 @param[in] Address Address used to access configuration space of this PCI device.
1976 @param[in] IoDev Handle used to access configuration space of PCI device.
1978 @retval EFI_SUCCESS The command completed successfully.
1981 PciExplainCardBusData (
1982 IN PCI_CARDBUS_HEADER
*CardBus
,
1984 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1988 Explain each meaningful bit of register Status. The definition of Status is
1989 slightly different depending on the PCI header type.
1991 @param[in] Status Points to the content of register Status.
1992 @param[in] MainStatus Indicates if this register is main status(not secondary
1994 @param[in] HeaderType Header type of this PCI device.
1996 @retval EFI_SUCCESS The command completed successfully.
2001 IN BOOLEAN MainStatus
,
2002 IN PCI_HEADER_TYPE HeaderType
2006 Explain each meaningful bit of register Command.
2008 @param[in] Command Points to the content of register Command.
2010 @retval EFI_SUCCESS The command completed successfully.
2018 Explain each meaningful bit of register Bridge Control.
2020 @param[in] BridgeControl Points to the content of register Bridge Control.
2021 @param[in] HeaderType The headertype.
2023 @retval EFI_SUCCESS The command completed successfully.
2026 PciExplainBridgeControl (
2027 IN UINT16
*BridgeControl
,
2028 IN PCI_HEADER_TYPE HeaderType
2032 Print each capability structure.
2034 @param[in] IoDev The pointer to the deivce.
2035 @param[in] Address The address to start at.
2036 @param[in] CapPtr The offset from the address.
2037 @param[in] EnhancedDump The print format for the dump data.
2039 @retval EFI_SUCCESS The operation was successful.
2042 PciExplainCapabilityStruct (
2043 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2046 IN CONST UINT16 EnhancedDump
2050 Display Pcie device structure.
2052 @param[in] IoDev The pointer to the root pci protocol.
2053 @param[in] Address The Address to start at.
2054 @param[in] CapabilityPtr The offset from the address to start.
2055 @param[in] EnhancedDump The print format for the dump data.
2057 @retval EFI_SUCCESS The command completed successfully.
2058 @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted.
2061 PciExplainPciExpress (
2062 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2064 IN UINT8 CapabilityPtr
,
2065 IN CONST UINT16 EnhancedDump
2069 Print out information of the capability information.
2071 @param[in] PciExpressCap The pointer to the structure about the device.
2073 @retval EFI_SUCCESS The operation was successful.
2077 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2081 Print out information of the device capability information.
2083 @param[in] PciExpressCap The pointer to the structure about the device.
2085 @retval EFI_SUCCESS The operation was successful.
2088 ExplainPcieDeviceCap (
2089 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2093 Print out information of the device control information.
2095 @param[in] PciExpressCap The pointer to the structure about the device.
2097 @retval EFI_SUCCESS The operation was successful.
2100 ExplainPcieDeviceControl (
2101 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2105 Print out information of the device status information.
2107 @param[in] PciExpressCap The pointer to the structure about the device.
2109 @retval EFI_SUCCESS The operation was successful.
2112 ExplainPcieDeviceStatus (
2113 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2117 Print out information of the device link information.
2119 @param[in] PciExpressCap The pointer to the structure about the device.
2121 @retval EFI_SUCCESS The operation was successful.
2124 ExplainPcieLinkCap (
2125 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2129 Print out information of the device link control information.
2131 @param[in] PciExpressCap The pointer to the structure about the device.
2133 @retval EFI_SUCCESS The operation was successful.
2136 ExplainPcieLinkControl (
2137 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2141 Print out information of the device link status information.
2143 @param[in] PciExpressCap The pointer to the structure about the device.
2145 @retval EFI_SUCCESS The operation was successful.
2148 ExplainPcieLinkStatus (
2149 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2153 Print out information of the device slot information.
2155 @param[in] PciExpressCap The pointer to the structure about the device.
2157 @retval EFI_SUCCESS The operation was successful.
2160 ExplainPcieSlotCap (
2161 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2165 Print out information of the device slot control information.
2167 @param[in] PciExpressCap The pointer to the structure about the device.
2169 @retval EFI_SUCCESS The operation was successful.
2172 ExplainPcieSlotControl (
2173 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2177 Print out information of the device slot status information.
2179 @param[in] PciExpressCap The pointer to the structure about the device.
2181 @retval EFI_SUCCESS The operation was successful.
2184 ExplainPcieSlotStatus (
2185 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2189 Print out information of the device root information.
2191 @param[in] PciExpressCap The pointer to the structure about the device.
2193 @retval EFI_SUCCESS The operation was successful.
2196 ExplainPcieRootControl (
2197 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2201 Print out information of the device root capability information.
2203 @param[in] PciExpressCap The pointer to the structure about the device.
2205 @retval EFI_SUCCESS The operation was successful.
2208 ExplainPcieRootCap (
2209 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2213 Print out information of the device root status information.
2215 @param[in] PciExpressCap The pointer to the structure about the device.
2217 @retval EFI_SUCCESS The operation was successful.
2220 ExplainPcieRootStatus (
2221 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2224 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STRUCTURE
*PciExpressCap
);
2230 } PCIE_CAPREG_FIELD_WIDTH
;
2233 PcieExplainTypeCommon
,
2234 PcieExplainTypeDevice
,
2235 PcieExplainTypeLink
,
2236 PcieExplainTypeSlot
,
2237 PcieExplainTypeRoot
,
2239 } PCIE_EXPLAIN_TYPE
;
2245 PCIE_CAPREG_FIELD_WIDTH Width
;
2246 PCIE_EXPLAIN_FUNCTION Func
;
2247 PCIE_EXPLAIN_TYPE Type
;
2248 } PCIE_EXPLAIN_STRUCT
;
2250 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
2252 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
2256 PcieExplainTypeCommon
2259 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
2263 PcieExplainTypeCommon
2266 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
2270 PcieExplainTypeCommon
2273 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
2276 ExplainPcieDeviceCap
,
2277 PcieExplainTypeDevice
2280 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
2283 ExplainPcieDeviceControl
,
2284 PcieExplainTypeDevice
2287 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
2290 ExplainPcieDeviceStatus
,
2291 PcieExplainTypeDevice
2294 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
2301 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
2304 ExplainPcieLinkControl
,
2308 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
2311 ExplainPcieLinkStatus
,
2315 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
2322 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
2325 ExplainPcieSlotControl
,
2329 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
2332 ExplainPcieSlotStatus
,
2336 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
2339 ExplainPcieRootControl
,
2343 STRING_TOKEN (STR_PCIEX_RSVDP
),
2350 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
2353 ExplainPcieRootStatus
,
2359 (PCIE_CAPREG_FIELD_WIDTH
)0,
2368 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
2369 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
2375 CHAR16
*DevicePortTypeTable
[] = {
2376 L
"PCI Express Endpoint",
2377 L
"Legacy PCI Express Endpoint",
2380 L
"Root Port of PCI Express Root Complex",
2381 L
"Upstream Port of PCI Express Switch",
2382 L
"Downstream Port of PCI Express Switch",
2383 L
"PCI Express to PCI/PCI-X Bridge",
2384 L
"PCI/PCI-X to PCI Express Bridge",
2385 L
"Root Complex Integrated Endpoint",
2386 L
"Root Complex Event Collector"
2389 CHAR16
*L0sLatencyStrTable
[] = {
2391 L
"64ns to less than 128ns",
2392 L
"128ns to less than 256ns",
2393 L
"256ns to less than 512ns",
2394 L
"512ns to less than 1us",
2395 L
"1us to less than 2us",
2400 CHAR16
*L1LatencyStrTable
[] = {
2402 L
"1us to less than 2us",
2403 L
"2us to less than 4us",
2404 L
"4us to less than 8us",
2405 L
"8us to less than 16us",
2406 L
"16us to less than 32us",
2411 CHAR16
*ASPMCtrlStrTable
[] = {
2413 L
"L0s Entry Enabled",
2414 L
"L1 Entry Enabled",
2415 L
"L0s and L1 Entry Enabled"
2418 CHAR16
*SlotPwrLmtScaleTable
[] = {
2425 CHAR16
*IndicatorTable
[] = {
2434 Function for 'pci' command.
2436 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2437 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2441 ShellCommandRunPci (
2442 IN EFI_HANDLE ImageHandle
,
2443 IN EFI_SYSTEM_TABLE
*SystemTable
2451 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2453 PCI_COMMON_HEADER PciHeader
;
2454 PCI_CONFIG_SPACE ConfigSpace
;
2458 BOOLEAN ExplainData
;
2462 UINTN HandleBufSize
;
2463 EFI_HANDLE
*HandleBuf
;
2465 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2469 LIST_ENTRY
*Package
;
2470 CHAR16
*ProblemParam
;
2471 SHELL_STATUS ShellStatus
;
2474 UINT16 EnhancedDump
;
2476 ShellStatus
= SHELL_SUCCESS
;
2477 Status
= EFI_SUCCESS
;
2484 // initialize the shell lib (we must be in non-auto-init...)
2486 Status
= ShellInitialize();
2487 ASSERT_EFI_ERROR(Status
);
2489 Status
= CommandInit();
2490 ASSERT_EFI_ERROR(Status
);
2493 // parse the command line
2495 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2496 if (EFI_ERROR(Status
)) {
2497 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2498 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, ProblemParam
);
2499 FreePool(ProblemParam
);
2500 ShellStatus
= SHELL_INVALID_PARAMETER
;
2506 if (ShellCommandLineGetCount(Package
) == 2) {
2507 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
);
2508 ShellStatus
= SHELL_INVALID_PARAMETER
;
2512 if (ShellCommandLineGetCount(Package
) > 4) {
2513 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
);
2514 ShellStatus
= SHELL_INVALID_PARAMETER
;
2517 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2518 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"-s");
2519 ShellStatus
= SHELL_INVALID_PARAMETER
;
2523 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2524 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2525 // space for handles and call it again.
2527 HandleBufSize
= sizeof (EFI_HANDLE
);
2528 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2529 if (HandleBuf
== NULL
) {
2530 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2531 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2535 Status
= gBS
->LocateHandle (
2537 &gEfiPciRootBridgeIoProtocolGuid
,
2543 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2544 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2545 if (HandleBuf
== NULL
) {
2546 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2547 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2551 Status
= gBS
->LocateHandle (
2553 &gEfiPciRootBridgeIoProtocolGuid
,
2560 if (EFI_ERROR (Status
)) {
2561 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
);
2562 ShellStatus
= SHELL_NOT_FOUND
;
2566 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2568 // Argument Count == 1(no other argument): enumerate all pci functions
2570 if (ShellCommandLineGetCount(Package
) == 1) {
2571 gST
->ConOut
->QueryMode (
2573 gST
->ConOut
->Mode
->Mode
,
2580 if ((ScreenSize
& 1) == 1) {
2587 // For each handle, which decides a segment and a bus number range,
2588 // enumerate all devices on it.
2590 for (Index
= 0; Index
< HandleCount
; Index
++) {
2591 Status
= PciGetProtocolAndResource (
2596 if (EFI_ERROR (Status
)) {
2597 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, Status
);
2598 ShellStatus
= SHELL_NOT_FOUND
;
2602 // No document say it's impossible for a RootBridgeIo protocol handle
2603 // to have more than one address space descriptors, so find out every
2604 // bus range and for each of them do device enumeration.
2607 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2609 if (EFI_ERROR (Status
)) {
2610 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, Status
);
2611 ShellStatus
= SHELL_NOT_FOUND
;
2619 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2621 // For each devices, enumerate all functions it contains
2623 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2625 // For each function, read its configuration space and print summary
2627 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2628 if (ShellGetExecutionBreakFlag ()) {
2629 ShellStatus
= SHELL_ABORTED
;
2632 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2642 // If VendorId = 0xffff, there does not exist a device at this
2643 // location. For each device, if there is any function on it,
2644 // there must be 1 function at Function 0. So if Func = 0, there
2645 // will be no more functions in the same device, so we can break
2646 // loop to deal with the next device.
2648 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2652 if (PciHeader
.VendorId
!= 0xffff) {
2655 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2663 sizeof (PciHeader
) / sizeof (UINT32
),
2668 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2669 IoDev
->SegmentNumber
,
2675 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2677 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2680 PciHeader
.ClassCode
[0]
2684 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2686 // If ScreenSize == 0 we have the console redirected so don't
2692 // If this is not a multi-function device, we can leave the loop
2693 // to deal with the next device.
2695 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2703 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2704 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2705 // devices on all bus, we can leave loop.
2707 if (Descriptors
== NULL
) {
2713 Status
= EFI_SUCCESS
;
2717 ExplainData
= FALSE
;
2722 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2726 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2729 // Input converted to hexadecimal number.
2731 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2732 Segment
= (UINT16
) RetVal
;
2734 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2735 ShellStatus
= SHELL_INVALID_PARAMETER
;
2741 // The first Argument(except "-i") is assumed to be Bus number, second
2742 // to be Device number, and third to be Func number.
2744 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2747 // Input converted to hexadecimal number.
2749 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2750 Bus
= (UINT16
) RetVal
;
2752 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2753 ShellStatus
= SHELL_INVALID_PARAMETER
;
2757 if (Bus
> MAX_BUS_NUMBER
) {
2758 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2759 ShellStatus
= SHELL_INVALID_PARAMETER
;
2763 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2766 // Input converted to hexadecimal number.
2768 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2769 Device
= (UINT16
) RetVal
;
2771 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2772 ShellStatus
= SHELL_INVALID_PARAMETER
;
2776 if (Device
> MAX_DEVICE_NUMBER
){
2777 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2778 ShellStatus
= SHELL_INVALID_PARAMETER
;
2783 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2786 // Input converted to hexadecimal number.
2788 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2789 Func
= (UINT16
) RetVal
;
2791 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2792 ShellStatus
= SHELL_INVALID_PARAMETER
;
2796 if (Func
> MAX_FUNCTION_NUMBER
){
2797 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2798 ShellStatus
= SHELL_INVALID_PARAMETER
;
2804 // Find the protocol interface who's in charge of current segment, and its
2805 // bus range covers the current bus
2807 Status
= PciFindProtocolInterface (
2815 if (EFI_ERROR (Status
)) {
2817 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
,
2821 ShellStatus
= SHELL_NOT_FOUND
;
2825 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2826 Status
= IoDev
->Pci
.Read (
2830 sizeof (ConfigSpace
),
2834 if (EFI_ERROR (Status
)) {
2835 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, Status
);
2836 ShellStatus
= SHELL_ACCESS_DENIED
;
2840 mConfigSpace
= &ConfigSpace
;
2845 STRING_TOKEN (STR_PCI_INFO
),
2846 gShellDebug1HiiHandle
,
2858 // Dump standard header of configuration space
2860 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2862 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2863 ShellPrintEx(-1,-1, L
"\r\n");
2866 // Dump device dependent Part of configuration space
2871 sizeof (ConfigSpace
) - SizeOfHeader
,
2876 // If "-i" appears in command line, interpret data in configuration space
2880 if (ShellCommandLineGetFlag(Package
, L
"-_e")) {
2881 EnhancedDump
= 0xFFFF;
2882 Temp
= ShellCommandLineGetValue(Package
, L
"-_e");
2884 EnhancedDump
= (UINT16
) ShellHexStrToUintn (Temp
);
2887 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
, EnhancedDump
);
2891 if (HandleBuf
!= NULL
) {
2892 FreePool (HandleBuf
);
2894 if (Package
!= NULL
) {
2895 ShellCommandLineFreeVarList (Package
);
2897 mConfigSpace
= NULL
;
2902 This function finds out the protocol which is in charge of the given
2903 segment, and its bus range covers the current bus number. It lookes
2904 each instances of RootBridgeIoProtocol handle, until the one meets the
2907 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2908 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2909 @param[in] Segment Segment number of device we are dealing with.
2910 @param[in] Bus Bus number of device we are dealing with.
2911 @param[out] IoDev Handle used to access configuration space of PCI device.
2913 @retval EFI_SUCCESS The command completed successfully.
2914 @retval EFI_INVALID_PARAMETER Invalid parameter.
2918 PciFindProtocolInterface (
2919 IN EFI_HANDLE
*HandleBuf
,
2920 IN UINTN HandleCount
,
2923 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2928 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2934 // Go through all handles, until the one meets the criteria is found
2936 for (Index
= 0; Index
< HandleCount
; Index
++) {
2937 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2938 if (EFI_ERROR (Status
)) {
2942 // When Descriptors == NULL, the Configuration() is not implemented,
2943 // so we only check the Segment number
2945 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2949 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2954 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2955 if (EFI_ERROR (Status
)) {
2963 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2969 return EFI_NOT_FOUND
;
2973 This function gets the protocol interface from the given handle, and
2974 obtains its address space descriptors.
2976 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2977 @param[out] IoDev Handle used to access configuration space of PCI device.
2978 @param[out] Descriptors Points to the address space descriptors.
2980 @retval EFI_SUCCESS The command completed successfully
2983 PciGetProtocolAndResource (
2984 IN EFI_HANDLE Handle
,
2985 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2986 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2992 // Get inferface from protocol
2994 Status
= gBS
->HandleProtocol (
2996 &gEfiPciRootBridgeIoProtocolGuid
,
3000 if (EFI_ERROR (Status
)) {
3004 // Call Configuration() to get address space descriptors
3006 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
3007 if (Status
== EFI_UNSUPPORTED
) {
3008 *Descriptors
= NULL
;
3017 This function get the next bus range of given address space descriptors.
3018 It also moves the pointer backward a node, to get prepared to be called
3021 @param[in, out] Descriptors Points to current position of a serial of address space
3023 @param[out] MinBus The lower range of bus number.
3024 @param[out] MaxBus The upper range of bus number.
3025 @param[out] IsEnd Meet end of the serial of descriptors.
3027 @retval EFI_SUCCESS The command completed successfully.
3030 PciGetNextBusRange (
3031 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
3040 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3041 // range is 0~PCI_MAX_BUS
3043 if ((*Descriptors
) == NULL
) {
3045 *MaxBus
= PCI_MAX_BUS
;
3049 // *Descriptors points to one or more address space descriptors, which
3050 // ends with a end tagged descriptor. Examine each of the descriptors,
3051 // if a bus typed one is found and its bus range covers bus, this handle
3052 // is the handle we are looking for.
3055 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
3056 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
3057 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
3058 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
3060 return (EFI_SUCCESS
);
3066 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
3074 Explain the data in PCI configuration space. The part which is common for
3075 PCI device and bridge is interpreted in this function. It calls other
3076 functions to interpret data unique for device or bridge.
3078 @param[in] ConfigSpace Data in PCI configuration space.
3079 @param[in] Address Address used to access configuration space of this PCI device.
3080 @param[in] IoDev Handle used to access configuration space of PCI device.
3081 @param[in] EnhancedDump The print format for the dump data.
3083 @retval EFI_SUCCESS The command completed successfully.
3087 IN PCI_CONFIG_SPACE
*ConfigSpace
,
3089 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3090 IN CONST UINT16 EnhancedDump
3093 PCI_COMMON_HEADER
*Common
;
3094 PCI_HEADER_TYPE HeaderType
;
3098 Common
= &(ConfigSpace
->Common
);
3100 ShellPrintEx (-1, -1, L
"\r\n");
3103 // Print Vendor Id and Device Id
3105 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
3106 INDEX_OF (&(Common
->VendorId
)),
3108 INDEX_OF (&(Common
->DeviceId
)),
3113 // Print register Command
3115 PciExplainCommand (&(Common
->Command
));
3118 // Print register Status
3120 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
3123 // Print register Revision ID
3125 ShellPrintEx(-1, -1, L
"\r\n");
3126 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
3127 INDEX_OF (&(Common
->RevisionId
)),
3132 // Print register BIST
3134 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->Bist
)));
3135 if ((Common
->Bist
& PCI_BIT_7
) != 0) {
3136 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->Bist
);
3138 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
3141 // Print register Cache Line Size
3143 ShellPrintHiiEx(-1, -1, NULL
,
3144 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
3145 gShellDebug1HiiHandle
,
3146 INDEX_OF (&(Common
->CacheLineSize
)),
3147 Common
->CacheLineSize
3151 // Print register Latency Timer
3153 ShellPrintHiiEx(-1, -1, NULL
,
3154 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
3155 gShellDebug1HiiHandle
,
3156 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
3157 Common
->PrimaryLatencyTimer
3161 // Print register Header Type
3163 ShellPrintHiiEx(-1, -1, NULL
,
3164 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
3165 gShellDebug1HiiHandle
,
3166 INDEX_OF (&(Common
->HeaderType
)),
3170 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
3171 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
3174 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
3177 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
3178 switch (HeaderType
) {
3180 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
3184 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
3187 case PciCardBusBridge
:
3188 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
3192 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
3193 HeaderType
= PciUndefined
;
3197 // Print register Class Code
3199 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
3200 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
3201 ShellPrintEx (-1, -1, L
"\r\n");
3203 if (ShellGetExecutionBreakFlag()) {
3208 // Interpret remaining part of PCI configuration header depending on
3212 Status
= EFI_SUCCESS
;
3213 switch (HeaderType
) {
3215 Status
= PciExplainDeviceData (
3216 &(ConfigSpace
->NonCommon
.Device
),
3220 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
3224 Status
= PciExplainBridgeData (
3225 &(ConfigSpace
->NonCommon
.Bridge
),
3229 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
3232 case PciCardBusBridge
:
3233 Status
= PciExplainCardBusData (
3234 &(ConfigSpace
->NonCommon
.CardBus
),
3238 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
3245 // If Status bit4 is 1, dump or explain capability structure
3247 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
3248 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
, EnhancedDump
);
3255 Explain the device specific part of data in PCI configuration space.
3257 @param[in] Device Data in PCI configuration space.
3258 @param[in] Address Address used to access configuration space of this PCI device.
3259 @param[in] IoDev Handle used to access configuration space of PCI device.
3261 @retval EFI_SUCCESS The command completed successfully.
3264 PciExplainDeviceData (
3265 IN PCI_DEVICE_HEADER
*Device
,
3267 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3276 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3277 // exist. If these no Bar for this function, print "none", otherwise
3278 // list detail information about this Bar.
3280 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
3283 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
3284 for (Index
= 0; Index
< BarCount
; Index
++) {
3285 if (Device
->Bar
[Index
] == 0) {
3291 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
3292 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3295 Status
= PciExplainBar (
3296 &(Device
->Bar
[Index
]),
3297 &(mConfigSpace
->Common
.Command
),
3303 if (EFI_ERROR (Status
)) {
3309 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3312 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3316 // Print register Expansion ROM Base Address
3318 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
3319 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
3322 ShellPrintHiiEx(-1, -1, NULL
,
3323 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
3324 gShellDebug1HiiHandle
,
3325 INDEX_OF (&(Device
->ROMBar
)),
3330 // Print register Cardbus CIS ptr
3332 ShellPrintHiiEx(-1, -1, NULL
,
3333 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
3334 gShellDebug1HiiHandle
,
3335 INDEX_OF (&(Device
->CardBusCISPtr
)),
3336 Device
->CardBusCISPtr
3340 // Print register Sub-vendor ID and subsystem ID
3342 ShellPrintHiiEx(-1, -1, NULL
,
3343 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
3344 gShellDebug1HiiHandle
,
3345 INDEX_OF (&(Device
->SubVendorId
)),
3349 ShellPrintHiiEx(-1, -1, NULL
,
3350 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
3351 gShellDebug1HiiHandle
,
3352 INDEX_OF (&(Device
->SubSystemId
)),
3357 // Print register Capabilities Ptr
3359 ShellPrintHiiEx(-1, -1, NULL
,
3360 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
3361 gShellDebug1HiiHandle
,
3362 INDEX_OF (&(Device
->CapabilitiesPtr
)),
3363 Device
->CapabilitiesPtr
3367 // Print register Interrupt Line and interrupt pin
3369 ShellPrintHiiEx(-1, -1, NULL
,
3370 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
3371 gShellDebug1HiiHandle
,
3372 INDEX_OF (&(Device
->InterruptLine
)),
3373 Device
->InterruptLine
3376 ShellPrintHiiEx(-1, -1, NULL
,
3377 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3378 gShellDebug1HiiHandle
,
3379 INDEX_OF (&(Device
->InterruptPin
)),
3380 Device
->InterruptPin
3384 // Print register Min_Gnt and Max_Lat
3386 ShellPrintHiiEx(-1, -1, NULL
,
3387 STRING_TOKEN (STR_PCI2_MIN_GNT
),
3388 gShellDebug1HiiHandle
,
3389 INDEX_OF (&(Device
->MinGnt
)),
3393 ShellPrintHiiEx(-1, -1, NULL
,
3394 STRING_TOKEN (STR_PCI2_MAX_LAT
),
3395 gShellDebug1HiiHandle
,
3396 INDEX_OF (&(Device
->MaxLat
)),
3404 Explain the bridge specific part of data in PCI configuration space.
3406 @param[in] Bridge Bridge specific data region in PCI configuration space.
3407 @param[in] Address Address used to access configuration space of this PCI device.
3408 @param[in] IoDev Handle used to access configuration space of PCI device.
3410 @retval EFI_SUCCESS The command completed successfully.
3413 PciExplainBridgeData (
3414 IN PCI_BRIDGE_HEADER
*Bridge
,
3416 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3426 // Print Base Address Registers. When Bar = 0, this Bar does not
3427 // exist. If these no Bar for this function, print "none", otherwise
3428 // list detail information about this Bar.
3430 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3433 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3435 for (Index
= 0; Index
< BarCount
; Index
++) {
3436 if (Bridge
->Bar
[Index
] == 0) {
3442 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3443 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3446 Status
= PciExplainBar (
3447 &(Bridge
->Bar
[Index
]),
3448 &(mConfigSpace
->Common
.Command
),
3454 if (EFI_ERROR (Status
)) {
3460 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3462 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3466 // Expansion register ROM Base Address
3468 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
3469 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
3472 ShellPrintHiiEx(-1, -1, NULL
,
3473 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3474 gShellDebug1HiiHandle
,
3475 INDEX_OF (&(Bridge
->ROMBar
)),
3480 // Print Bus Numbers(Primary, Secondary, and Subordinate
3482 ShellPrintHiiEx(-1, -1, NULL
,
3483 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3484 gShellDebug1HiiHandle
,
3485 INDEX_OF (&(Bridge
->PrimaryBus
)),
3486 INDEX_OF (&(Bridge
->SecondaryBus
)),
3487 INDEX_OF (&(Bridge
->SubordinateBus
))
3490 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3492 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3493 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3494 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3497 // Print register Secondary Latency Timer
3499 ShellPrintHiiEx(-1, -1, NULL
,
3500 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3501 gShellDebug1HiiHandle
,
3502 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3503 Bridge
->SecondaryLatencyTimer
3507 // Print register Secondary Status
3509 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3512 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3513 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3514 // base and limit address are listed.
3516 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3517 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3522 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
3523 IoAddress32
&= 0xfffff000;
3524 ShellPrintHiiEx(-1, -1, NULL
,
3525 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3526 gShellDebug1HiiHandle
,
3527 INDEX_OF (&(Bridge
->IoBase
)),
3531 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
3532 IoAddress32
|= 0x00000fff;
3533 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3536 // Memory Base & Limit
3538 ShellPrintHiiEx(-1, -1, NULL
,
3539 STRING_TOKEN (STR_PCI2_MEMORY
),
3540 gShellDebug1HiiHandle
,
3541 INDEX_OF (&(Bridge
->MemoryBase
)),
3542 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3545 ShellPrintHiiEx(-1, -1, NULL
,
3546 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3547 gShellDebug1HiiHandle
,
3548 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3552 // Pre-fetch-able Memory Base & Limit
3554 ShellPrintHiiEx(-1, -1, NULL
,
3555 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3556 gShellDebug1HiiHandle
,
3557 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
3558 Bridge
->PrefetchableBaseUpper
,
3559 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3562 ShellPrintHiiEx(-1, -1, NULL
,
3563 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3564 gShellDebug1HiiHandle
,
3565 Bridge
->PrefetchableLimitUpper
,
3566 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3570 // Print register Capabilities Pointer
3572 ShellPrintHiiEx(-1, -1, NULL
,
3573 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3574 gShellDebug1HiiHandle
,
3575 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3576 Bridge
->CapabilitiesPtr
3580 // Print register Bridge Control
3582 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3585 // Print register Interrupt Line & PIN
3587 ShellPrintHiiEx(-1, -1, NULL
,
3588 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3589 gShellDebug1HiiHandle
,
3590 INDEX_OF (&(Bridge
->InterruptLine
)),
3591 Bridge
->InterruptLine
3594 ShellPrintHiiEx(-1, -1, NULL
,
3595 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3596 gShellDebug1HiiHandle
,
3597 INDEX_OF (&(Bridge
->InterruptPin
)),
3598 Bridge
->InterruptPin
3605 Explain the Base Address Register(Bar) in PCI configuration space.
3607 @param[in] Bar Points to the Base Address Register intended to interpret.
3608 @param[in] Command Points to the register Command.
3609 @param[in] Address Address used to access configuration space of this PCI device.
3610 @param[in] IoDev Handle used to access configuration space of PCI device.
3611 @param[in, out] Index The Index.
3613 @retval EFI_SUCCESS The command completed successfully.
3620 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3641 // According the bar type, list detail about this bar, for example: 32 or
3642 // 64 bits; pre-fetchable or not.
3644 if ((*Bar
& PCI_BIT_0
) == 0) {
3646 // This bar is of memory type
3650 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3651 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3652 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3653 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3655 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3657 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3658 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3659 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3660 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3661 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3669 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3670 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3673 if ((*Bar
& PCI_BIT_3
) == 0) {
3674 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3677 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3682 // This bar is of io type
3685 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3686 ShellPrintEx (-1, -1, L
"I/O ");
3690 // Get BAR length(or the amount of resource this bar demands for). To get
3691 // Bar length, first we should temporarily disable I/O and memory access
3692 // of this function(by set bits in the register Command), then write all
3693 // "1"s to this bar. The bar value read back is the amount of resource
3694 // this bar demands for.
3697 // Disable io & mem access
3699 OldCommand
= *Command
;
3700 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3701 RegAddress
= Address
| INDEX_OF (Command
);
3702 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3704 RegAddress
= Address
| INDEX_OF (Bar
);
3707 // Read after write the BAR to get the size
3711 NewBar32
= 0xffffffff;
3713 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3714 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3715 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3718 NewBar32
= NewBar32
& 0xfffffff0;
3719 NewBar32
= (~NewBar32
) + 1;
3722 NewBar32
= NewBar32
& 0xfffffffc;
3723 NewBar32
= (~NewBar32
) + 1;
3724 NewBar32
= NewBar32
& 0x0000ffff;
3729 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3730 NewBar64
= 0xffffffffffffffffULL
;
3732 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3733 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3734 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3737 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3738 NewBar64
= (~NewBar64
) + 1;
3741 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3742 NewBar64
= (~NewBar64
) + 1;
3743 NewBar64
= NewBar64
& 0x000000000000ffff;
3747 // Enable io & mem access
3749 RegAddress
= Address
| INDEX_OF (Command
);
3750 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3754 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3755 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3758 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3759 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3760 ShellPrintEx (-1, -1, L
" ");
3761 ShellPrintHiiEx(-1, -1, NULL
,
3762 STRING_TOKEN (STR_PCI2_RSHIFT
),
3763 gShellDebug1HiiHandle
,
3764 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3766 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3770 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3771 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3778 Explain the cardbus specific part of data in PCI configuration space.
3780 @param[in] CardBus CardBus specific region of PCI configuration space.
3781 @param[in] Address Address used to access configuration space of this PCI device.
3782 @param[in] IoDev Handle used to access configuration space of PCI device.
3784 @retval EFI_SUCCESS The command completed successfully.
3787 PciExplainCardBusData (
3788 IN PCI_CARDBUS_HEADER
*CardBus
,
3790 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3794 PCI_CARDBUS_DATA
*CardBusData
;
3796 ShellPrintHiiEx(-1, -1, NULL
,
3797 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3798 gShellDebug1HiiHandle
,
3799 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3800 CardBus
->CardBusSocketReg
3804 // Print Secondary Status
3806 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3809 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3810 // Subordinate bus number
3812 ShellPrintHiiEx(-1, -1, NULL
,
3813 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3814 gShellDebug1HiiHandle
,
3815 INDEX_OF (&(CardBus
->PciBusNumber
)),
3816 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3817 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3820 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3822 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3823 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3824 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3827 // Print CardBus Latency Timer
3829 ShellPrintHiiEx(-1, -1, NULL
,
3830 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3831 gShellDebug1HiiHandle
,
3832 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3833 CardBus
->CardBusLatencyTimer
3837 // Print Memory/Io ranges this cardbus bridge forwards
3839 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3840 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3842 ShellPrintHiiEx(-1, -1, NULL
,
3843 STRING_TOKEN (STR_PCI2_MEM_3
),
3844 gShellDebug1HiiHandle
,
3845 INDEX_OF (&(CardBus
->MemoryBase0
)),
3846 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3847 CardBus
->MemoryBase0
& 0xfffff000,
3848 CardBus
->MemoryLimit0
| 0x00000fff
3851 ShellPrintHiiEx(-1, -1, NULL
,
3852 STRING_TOKEN (STR_PCI2_MEM_3
),
3853 gShellDebug1HiiHandle
,
3854 INDEX_OF (&(CardBus
->MemoryBase1
)),
3855 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3856 CardBus
->MemoryBase1
& 0xfffff000,
3857 CardBus
->MemoryLimit1
| 0x00000fff
3860 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3861 ShellPrintHiiEx(-1, -1, NULL
,
3862 STRING_TOKEN (STR_PCI2_IO_2
),
3863 gShellDebug1HiiHandle
,
3864 INDEX_OF (&(CardBus
->IoBase0
)),
3865 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3866 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3867 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3870 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3871 ShellPrintHiiEx(-1, -1, NULL
,
3872 STRING_TOKEN (STR_PCI2_IO_2
),
3873 gShellDebug1HiiHandle
,
3874 INDEX_OF (&(CardBus
->IoBase1
)),
3875 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3876 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3877 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3881 // Print register Interrupt Line & PIN
3883 ShellPrintHiiEx(-1, -1, NULL
,
3884 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3885 gShellDebug1HiiHandle
,
3886 INDEX_OF (&(CardBus
->InterruptLine
)),
3887 CardBus
->InterruptLine
,
3888 INDEX_OF (&(CardBus
->InterruptPin
)),
3889 CardBus
->InterruptPin
3893 // Print register Bridge Control
3895 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3898 // Print some registers in data region of PCI configuration space for cardbus
3899 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3902 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3904 ShellPrintHiiEx(-1, -1, NULL
,
3905 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3906 gShellDebug1HiiHandle
,
3907 INDEX_OF (&(CardBusData
->SubVendorId
)),
3908 CardBusData
->SubVendorId
,
3909 INDEX_OF (&(CardBusData
->SubSystemId
)),
3910 CardBusData
->SubSystemId
3913 ShellPrintHiiEx(-1, -1, NULL
,
3914 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3915 gShellDebug1HiiHandle
,
3916 INDEX_OF (&(CardBusData
->LegacyBase
)),
3917 CardBusData
->LegacyBase
3924 Explain each meaningful bit of register Status. The definition of Status is
3925 slightly different depending on the PCI header type.
3927 @param[in] Status Points to the content of register Status.
3928 @param[in] MainStatus Indicates if this register is main status(not secondary
3930 @param[in] HeaderType Header type of this PCI device.
3932 @retval EFI_SUCCESS The command completed successfully.
3937 IN BOOLEAN MainStatus
,
3938 IN PCI_HEADER_TYPE HeaderType
3942 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3945 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3948 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3951 // Bit 5 is meaningless for CardBus Bridge
3953 if (HeaderType
== PciCardBusBridge
) {
3954 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3957 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3960 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3962 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3964 // Bit 9 and bit 10 together decides the DEVSEL timing
3966 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3967 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3968 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3970 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3971 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3973 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3974 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3977 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3980 ShellPrintHiiEx(-1, -1, NULL
,
3981 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3982 gShellDebug1HiiHandle
,
3983 (*Status
& PCI_BIT_11
) != 0
3986 ShellPrintHiiEx(-1, -1, NULL
,
3987 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3988 gShellDebug1HiiHandle
,
3989 (*Status
& PCI_BIT_12
) != 0
3992 ShellPrintHiiEx(-1, -1, NULL
,
3993 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3994 gShellDebug1HiiHandle
,
3995 (*Status
& PCI_BIT_13
) != 0
3999 ShellPrintHiiEx(-1, -1, NULL
,
4000 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
4001 gShellDebug1HiiHandle
,
4002 (*Status
& PCI_BIT_14
) != 0
4006 ShellPrintHiiEx(-1, -1, NULL
,
4007 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
4008 gShellDebug1HiiHandle
,
4009 (*Status
& PCI_BIT_14
) != 0
4013 ShellPrintHiiEx(-1, -1, NULL
,
4014 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
4015 gShellDebug1HiiHandle
,
4016 (*Status
& PCI_BIT_15
) != 0
4023 Explain each meaningful bit of register Command.
4025 @param[in] Command Points to the content of register Command.
4027 @retval EFI_SUCCESS The command completed successfully.
4035 // Print the binary value of register Command
4037 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
4040 // Explain register Command bit by bit
4042 ShellPrintHiiEx(-1, -1, NULL
,
4043 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
4044 gShellDebug1HiiHandle
,
4045 (*Command
& PCI_BIT_0
) != 0
4048 ShellPrintHiiEx(-1, -1, NULL
,
4049 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
4050 gShellDebug1HiiHandle
,
4051 (*Command
& PCI_BIT_1
) != 0
4054 ShellPrintHiiEx(-1, -1, NULL
,
4055 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
4056 gShellDebug1HiiHandle
,
4057 (*Command
& PCI_BIT_2
) != 0
4060 ShellPrintHiiEx(-1, -1, NULL
,
4061 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
4062 gShellDebug1HiiHandle
,
4063 (*Command
& PCI_BIT_3
) != 0
4066 ShellPrintHiiEx(-1, -1, NULL
,
4067 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
4068 gShellDebug1HiiHandle
,
4069 (*Command
& PCI_BIT_4
) != 0
4072 ShellPrintHiiEx(-1, -1, NULL
,
4073 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
4074 gShellDebug1HiiHandle
,
4075 (*Command
& PCI_BIT_5
) != 0
4078 ShellPrintHiiEx(-1, -1, NULL
,
4079 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
4080 gShellDebug1HiiHandle
,
4081 (*Command
& PCI_BIT_6
) != 0
4084 ShellPrintHiiEx(-1, -1, NULL
,
4085 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
4086 gShellDebug1HiiHandle
,
4087 (*Command
& PCI_BIT_7
) != 0
4090 ShellPrintHiiEx(-1, -1, NULL
,
4091 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
4092 gShellDebug1HiiHandle
,
4093 (*Command
& PCI_BIT_8
) != 0
4096 ShellPrintHiiEx(-1, -1, NULL
,
4097 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
4098 gShellDebug1HiiHandle
,
4099 (*Command
& PCI_BIT_9
) != 0
4106 Explain each meaningful bit of register Bridge Control.
4108 @param[in] BridgeControl Points to the content of register Bridge Control.
4109 @param[in] HeaderType The headertype.
4111 @retval EFI_SUCCESS The command completed successfully.
4114 PciExplainBridgeControl (
4115 IN UINT16
*BridgeControl
,
4116 IN PCI_HEADER_TYPE HeaderType
4119 ShellPrintHiiEx(-1, -1, NULL
,
4120 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
4121 gShellDebug1HiiHandle
,
4122 INDEX_OF (BridgeControl
),
4126 ShellPrintHiiEx(-1, -1, NULL
,
4127 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
4128 gShellDebug1HiiHandle
,
4129 (*BridgeControl
& PCI_BIT_0
) != 0
4131 ShellPrintHiiEx(-1, -1, NULL
,
4132 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
4133 gShellDebug1HiiHandle
,
4134 (*BridgeControl
& PCI_BIT_1
) != 0
4136 ShellPrintHiiEx(-1, -1, NULL
,
4137 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
4138 gShellDebug1HiiHandle
,
4139 (*BridgeControl
& PCI_BIT_2
) != 0
4141 ShellPrintHiiEx(-1, -1, NULL
,
4142 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
4143 gShellDebug1HiiHandle
,
4144 (*BridgeControl
& PCI_BIT_3
) != 0
4146 ShellPrintHiiEx(-1, -1, NULL
,
4147 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
4148 gShellDebug1HiiHandle
,
4149 (*BridgeControl
& PCI_BIT_5
) != 0
4153 // Register Bridge Control has some slight differences between P2P bridge
4154 // and Cardbus bridge from bit 6 to bit 11.
4156 if (HeaderType
== PciP2pBridge
) {
4157 ShellPrintHiiEx(-1, -1, NULL
,
4158 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
4159 gShellDebug1HiiHandle
,
4160 (*BridgeControl
& PCI_BIT_6
) != 0
4162 ShellPrintHiiEx(-1, -1, NULL
,
4163 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
4164 gShellDebug1HiiHandle
,
4165 (*BridgeControl
& PCI_BIT_7
) != 0
4167 ShellPrintHiiEx(-1, -1, NULL
,
4168 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
4169 gShellDebug1HiiHandle
,
4170 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
4172 ShellPrintHiiEx(-1, -1, NULL
,
4173 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
4174 gShellDebug1HiiHandle
,
4175 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
4177 ShellPrintHiiEx(-1, -1, NULL
,
4178 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
4179 gShellDebug1HiiHandle
,
4180 (*BridgeControl
& PCI_BIT_10
) != 0
4182 ShellPrintHiiEx(-1, -1, NULL
,
4183 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
4184 gShellDebug1HiiHandle
,
4185 (*BridgeControl
& PCI_BIT_11
) != 0
4189 ShellPrintHiiEx(-1, -1, NULL
,
4190 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
4191 gShellDebug1HiiHandle
,
4192 (*BridgeControl
& PCI_BIT_6
) != 0
4194 ShellPrintHiiEx(-1, -1, NULL
,
4195 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
4196 gShellDebug1HiiHandle
,
4197 (*BridgeControl
& PCI_BIT_7
) != 0
4199 ShellPrintHiiEx(-1, -1, NULL
,
4200 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
4201 gShellDebug1HiiHandle
,
4202 (*BridgeControl
& PCI_BIT_10
) != 0
4210 Print each capability structure.
4212 @param[in] IoDev The pointer to the deivce.
4213 @param[in] Address The address to start at.
4214 @param[in] CapPtr The offset from the address.
4215 @param[in] EnhancedDump The print format for the dump data.
4217 @retval EFI_SUCCESS The operation was successful.
4220 PciExplainCapabilityStruct (
4221 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4224 IN CONST UINT16 EnhancedDump
4227 UINT8 CapabilityPtr
;
4228 UINT16 CapabilityEntry
;
4232 CapabilityPtr
= CapPtr
;
4235 // Go through the Capability list
4237 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
4238 RegAddress
= Address
+ CapabilityPtr
;
4239 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
4241 CapabilityID
= (UINT8
) CapabilityEntry
;
4244 // Explain PciExpress data
4246 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
4247 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
, EnhancedDump
);
4251 // Explain other capabilities here
4253 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
4260 Print out information of the capability information.
4262 @param[in] PciExpressCap The pointer to the structure about the device.
4264 @retval EFI_SUCCESS The operation was successful.
4268 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4272 CHAR16
*DevicePortType
;
4274 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4275 ShellPrintEx (-1, -1,
4276 L
" Capability Version(3:0): %E0x%04x%N\r\n",
4277 PCIE_CAP_VERSION (PcieCapReg
)
4279 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
4280 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
4282 DevicePortType
= L
"Unknown Type";
4284 ShellPrintEx (-1, -1,
4285 L
" Device/PortType(7:4): %E%s%N\r\n",
4289 // 'Slot Implemented' is only valid for:
4290 // a) Root Port of PCI Express Root Complex, or
4291 // b) Downstream Port of PCI Express Switch
4293 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
4294 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
4295 ShellPrintEx (-1, -1,
4296 L
" Slot Implemented(8): %E%d%N\r\n",
4297 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
4300 ShellPrintEx (-1, -1,
4301 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4302 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
4308 Print out information of the device capability information.
4310 @param[in] PciExpressCap The pointer to the structure about the device.
4312 @retval EFI_SUCCESS The operation was successful.
4315 ExplainPcieDeviceCap (
4316 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4320 UINT32 PcieDeviceCap
;
4321 UINT8 DevicePortType
;
4325 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4326 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
4327 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
4328 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
4329 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
4330 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
4332 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4334 ShellPrintEx (-1, -1,
4335 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
4336 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
4338 ShellPrintEx (-1, -1,
4339 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4340 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
4343 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4345 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4346 L0sLatency
= (UINT8
) PCIE_CAP_L0SLATENCY (PcieDeviceCap
);
4347 L1Latency
= (UINT8
) PCIE_CAP_L1LATENCY (PcieDeviceCap
);
4348 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
4349 if (L0sLatency
< 4) {
4350 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
4352 if (L0sLatency
< 7) {
4353 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
4355 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4358 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
4359 if (L1Latency
< 7) {
4360 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
4362 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4365 ShellPrintEx (-1, -1,
4366 L
" Role-based Error Reporting(15): %E%d%N\r\n",
4367 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
4370 // Only valid for Upstream Port:
4371 // a) Captured Slot Power Limit Value
4372 // b) Captured Slot Power Scale
4374 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
4375 ShellPrintEx (-1, -1,
4376 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4377 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
4379 ShellPrintEx (-1, -1,
4380 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4381 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
4385 // Function Level Reset Capability is only valid for Endpoint
4387 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4388 ShellPrintEx (-1, -1,
4389 L
" Function Level Reset Capability(28): %E%d%N\r\n",
4390 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
4397 Print out information of the device control information.
4399 @param[in] PciExpressCap The pointer to the structure about the device.
4401 @retval EFI_SUCCESS The operation was successful.
4404 ExplainPcieDeviceControl (
4405 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4409 UINT16 PcieDeviceControl
;
4411 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4412 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
4413 ShellPrintEx (-1, -1,
4414 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4415 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4417 ShellPrintEx (-1, -1,
4418 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4419 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4421 ShellPrintEx (-1, -1,
4422 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4423 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4425 ShellPrintEx (-1, -1,
4426 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4427 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
4429 ShellPrintEx (-1, -1,
4430 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4431 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
4433 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4434 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
4435 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
4437 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4439 ShellPrintEx (-1, -1,
4440 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4441 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
4443 ShellPrintEx (-1, -1,
4444 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4445 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
4447 ShellPrintEx (-1, -1,
4448 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4449 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
4451 ShellPrintEx (-1, -1,
4452 L
" Enable No Snoop(11): %E%d%N\r\n",
4453 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
4455 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4456 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
4457 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
4459 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4462 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4464 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
4465 ShellPrintEx (-1, -1,
4466 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4467 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
4474 Print out information of the device status information.
4476 @param[in] PciExpressCap The pointer to the structure about the device.
4478 @retval EFI_SUCCESS The operation was successful.
4481 ExplainPcieDeviceStatus (
4482 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4485 UINT16 PcieDeviceStatus
;
4487 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
4488 ShellPrintEx (-1, -1,
4489 L
" Correctable Error Detected(0): %E%d%N\r\n",
4490 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
4492 ShellPrintEx (-1, -1,
4493 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4494 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
4496 ShellPrintEx (-1, -1,
4497 L
" Fatal Error Detected(2): %E%d%N\r\n",
4498 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
4500 ShellPrintEx (-1, -1,
4501 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4502 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
4504 ShellPrintEx (-1, -1,
4505 L
" AUX Power Detected(4): %E%d%N\r\n",
4506 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
4508 ShellPrintEx (-1, -1,
4509 L
" Transactions Pending(5): %E%d%N\r\n",
4510 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
4516 Print out information of the device link information.
4518 @param[in] PciExpressCap The pointer to the structure about the device.
4520 @retval EFI_SUCCESS The operation was successful.
4523 ExplainPcieLinkCap (
4524 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4528 CHAR16
*MaxLinkSpeed
;
4531 PcieLinkCap
= PciExpressCap
->LinkCap
;
4532 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap
)) {
4534 MaxLinkSpeed
= L
"2.5 GT/s";
4537 MaxLinkSpeed
= L
"5.0 GT/s";
4540 MaxLinkSpeed
= L
"8.0 GT/s";
4543 MaxLinkSpeed
= L
"Unknown";
4546 ShellPrintEx (-1, -1,
4547 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4550 ShellPrintEx (-1, -1,
4551 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4552 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
4554 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
4565 AspmValue
= L
"L0s and L1";
4568 AspmValue
= L
"Reserved";
4571 ShellPrintEx (-1, -1,
4572 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4575 ShellPrintEx (-1, -1,
4576 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4577 L0sLatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4579 ShellPrintEx (-1, -1,
4580 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4581 L1LatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4583 ShellPrintEx (-1, -1,
4584 L
" Clock Power Management(18): %E%d%N\r\n",
4585 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4587 ShellPrintEx (-1, -1,
4588 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4589 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4591 ShellPrintEx (-1, -1,
4592 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4593 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4595 ShellPrintEx (-1, -1,
4596 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4597 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4599 ShellPrintEx (-1, -1,
4600 L
" Port Number(31:24): %E0x%02x%N\r\n",
4601 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4607 Print out information of the device link control information.
4609 @param[in] PciExpressCap The pointer to the structure about the device.
4611 @retval EFI_SUCCESS The operation was successful.
4614 ExplainPcieLinkControl (
4615 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4618 UINT16 PcieLinkControl
;
4619 UINT8 DevicePortType
;
4621 PcieLinkControl
= PciExpressCap
->LinkControl
;
4622 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4623 ShellPrintEx (-1, -1,
4624 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4625 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4628 // RCB is not applicable to switches
4630 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4631 ShellPrintEx (-1, -1,
4632 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4633 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4637 // Link Disable is reserved on
4639 // b) PCI Express to PCI/PCI-X bridges
4640 // c) Upstream Ports of Switches
4642 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4643 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4644 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4645 ShellPrintEx (-1, -1,
4646 L
" Link Disable(4): %E%d%N\r\n",
4647 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4650 ShellPrintEx (-1, -1,
4651 L
" Common Clock Configuration(6): %E%d%N\r\n",
4652 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4654 ShellPrintEx (-1, -1,
4655 L
" Extended Synch(7): %E%d%N\r\n",
4656 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4658 ShellPrintEx (-1, -1,
4659 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4660 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4662 ShellPrintEx (-1, -1,
4663 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4664 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4666 ShellPrintEx (-1, -1,
4667 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4668 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4670 ShellPrintEx (-1, -1,
4671 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4672 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4678 Print out information of the device link status information.
4680 @param[in] PciExpressCap The pointer to the structure about the device.
4682 @retval EFI_SUCCESS The operation was successful.
4685 ExplainPcieLinkStatus (
4686 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4689 UINT16 PcieLinkStatus
;
4690 CHAR16
*CurLinkSpeed
;
4692 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4693 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4695 CurLinkSpeed
= L
"2.5 GT/s";
4698 CurLinkSpeed
= L
"5.0 GT/s";
4701 CurLinkSpeed
= L
"8.0 GT/s";
4704 CurLinkSpeed
= L
"Reserved";
4707 ShellPrintEx (-1, -1,
4708 L
" Current Link Speed(3:0): %E%s%N\r\n",
4711 ShellPrintEx (-1, -1,
4712 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4713 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4715 ShellPrintEx (-1, -1,
4716 L
" Link Training(11): %E%d%N\r\n",
4717 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4719 ShellPrintEx (-1, -1,
4720 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4721 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4723 ShellPrintEx (-1, -1,
4724 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4725 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4727 ShellPrintEx (-1, -1,
4728 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4729 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4731 ShellPrintEx (-1, -1,
4732 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4733 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4739 Print out information of the device slot information.
4741 @param[in] PciExpressCap The pointer to the structure about the device.
4743 @retval EFI_SUCCESS The operation was successful.
4746 ExplainPcieSlotCap (
4747 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4752 PcieSlotCap
= PciExpressCap
->SlotCap
;
4754 ShellPrintEx (-1, -1,
4755 L
" Attention Button Present(0): %E%d%N\r\n",
4756 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4758 ShellPrintEx (-1, -1,
4759 L
" Power Controller Present(1): %E%d%N\r\n",
4760 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4762 ShellPrintEx (-1, -1,
4763 L
" MRL Sensor Present(2): %E%d%N\r\n",
4764 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4766 ShellPrintEx (-1, -1,
4767 L
" Attention Indicator Present(3): %E%d%N\r\n",
4768 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4770 ShellPrintEx (-1, -1,
4771 L
" Power Indicator Present(4): %E%d%N\r\n",
4772 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4774 ShellPrintEx (-1, -1,
4775 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4776 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4778 ShellPrintEx (-1, -1,
4779 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4780 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4782 ShellPrintEx (-1, -1,
4783 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4784 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4786 ShellPrintEx (-1, -1,
4787 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4788 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4790 ShellPrintEx (-1, -1,
4791 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4792 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4794 ShellPrintEx (-1, -1,
4795 L
" No Command Completed Support(18): %E%d%N\r\n",
4796 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4798 ShellPrintEx (-1, -1,
4799 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4800 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4807 Print out information of the device slot control information.
4809 @param[in] PciExpressCap The pointer to the structure about the device.
4811 @retval EFI_SUCCESS The operation was successful.
4814 ExplainPcieSlotControl (
4815 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4818 UINT16 PcieSlotControl
;
4820 PcieSlotControl
= PciExpressCap
->SlotControl
;
4821 ShellPrintEx (-1, -1,
4822 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4823 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4825 ShellPrintEx (-1, -1,
4826 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4827 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4829 ShellPrintEx (-1, -1,
4830 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4831 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4833 ShellPrintEx (-1, -1,
4834 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4835 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4837 ShellPrintEx (-1, -1,
4838 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4839 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4841 ShellPrintEx (-1, -1,
4842 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4843 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4845 ShellPrintEx (-1, -1,
4846 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4847 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4849 ShellPrintEx (-1, -1,
4850 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4851 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4853 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4854 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4855 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4857 ShellPrintEx (-1, -1, L
"On%N\r\n");
4859 ShellPrintEx (-1, -1,
4860 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4861 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4863 ShellPrintEx (-1, -1,
4864 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4865 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4871 Print out information of the device slot status information.
4873 @param[in] PciExpressCap The pointer to the structure about the device.
4875 @retval EFI_SUCCESS The operation was successful.
4878 ExplainPcieSlotStatus (
4879 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4882 UINT16 PcieSlotStatus
;
4884 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4886 ShellPrintEx (-1, -1,
4887 L
" Attention Button Pressed(0): %E%d%N\r\n",
4888 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4890 ShellPrintEx (-1, -1,
4891 L
" Power Fault Detected(1): %E%d%N\r\n",
4892 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4894 ShellPrintEx (-1, -1,
4895 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4896 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4898 ShellPrintEx (-1, -1,
4899 L
" Presence Detect Changed(3): %E%d%N\r\n",
4900 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4902 ShellPrintEx (-1, -1,
4903 L
" Command Completed(4): %E%d%N\r\n",
4904 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4906 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4907 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4908 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4910 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4912 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4913 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4914 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4916 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4918 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4919 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4920 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4922 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4924 ShellPrintEx (-1, -1,
4925 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4926 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4932 Print out information of the device root information.
4934 @param[in] PciExpressCap The pointer to the structure about the device.
4936 @retval EFI_SUCCESS The operation was successful.
4939 ExplainPcieRootControl (
4940 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4943 UINT16 PcieRootControl
;
4945 PcieRootControl
= PciExpressCap
->RootControl
;
4947 ShellPrintEx (-1, -1,
4948 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4949 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4951 ShellPrintEx (-1, -1,
4952 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4953 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4955 ShellPrintEx (-1, -1,
4956 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4957 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4959 ShellPrintEx (-1, -1,
4960 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4961 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4963 ShellPrintEx (-1, -1,
4964 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4965 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4972 Print out information of the device root capability information.
4974 @param[in] PciExpressCap The pointer to the structure about the device.
4976 @retval EFI_SUCCESS The operation was successful.
4979 ExplainPcieRootCap (
4980 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4985 PcieRootCap
= PciExpressCap
->RsvdP
;
4987 ShellPrintEx (-1, -1,
4988 L
" CRS Software Visibility(0): %E%d%N\r\n",
4989 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4996 Print out information of the device root status information.
4998 @param[in] PciExpressCap The pointer to the structure about the device.
5000 @retval EFI_SUCCESS The operation was successful.
5003 ExplainPcieRootStatus (
5004 IN PCIE_CAP_STRUCTURE
*PciExpressCap
5007 UINT32 PcieRootStatus
;
5009 PcieRootStatus
= PciExpressCap
->RootStatus
;
5011 ShellPrintEx (-1, -1,
5012 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
5013 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
5015 ShellPrintEx (-1, -1,
5016 L
" PME Status(16): %E%d%N\r\n",
5017 PCIE_CAP_PME_STATUS (PcieRootStatus
)
5019 ShellPrintEx (-1, -1,
5020 L
" PME Pending(17): %E%d%N\r\n",
5021 PCIE_CAP_PME_PENDING (PcieRootStatus
)
5027 Function to interpret and print out the link control structure
5029 @param[in] HeaderAddress The Address of this capability header.
5030 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5034 PrintInterpretedExtendedCompatibilityLinkControl (
5035 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5036 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5039 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
5040 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
5044 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
5045 gShellDebug1HiiHandle
,
5046 Header
->RootComplexLinkCapabilities
,
5047 Header
->RootComplexLinkControl
,
5048 Header
->RootComplexLinkStatus
5052 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5053 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
5054 (VOID
*) (HeaderAddress
)
5056 return (EFI_SUCCESS
);
5060 Function to interpret and print out the power budgeting structure
5062 @param[in] HeaderAddress The Address of this capability header.
5063 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5067 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5068 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5069 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5072 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
5073 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
5077 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
5078 gShellDebug1HiiHandle
,
5081 Header
->PowerBudgetCapability
5085 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5086 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
5087 (VOID
*) (HeaderAddress
)
5089 return (EFI_SUCCESS
);
5093 Function to interpret and print out the ACS structure
5095 @param[in] HeaderAddress The Address of this capability header.
5096 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5100 PrintInterpretedExtendedCompatibilityAcs (
5101 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5102 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5105 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
5109 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
5114 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
5115 gShellDebug1HiiHandle
,
5116 Header
->AcsCapability
,
5119 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header
)) {
5120 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header
);
5121 if (VectorSize
== 0) {
5124 for (LoopCounter
= 0 ; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
5127 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
5128 gShellDebug1HiiHandle
,
5130 Header
->EgressControlVectorArray
[LoopCounter
]
5136 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5137 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
5138 (VOID
*) (HeaderAddress
)
5140 return (EFI_SUCCESS
);
5144 Function to interpret and print out the latency tolerance reporting structure
5146 @param[in] HeaderAddress The Address of this capability header.
5147 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5151 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5152 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5153 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5156 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
5157 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
5161 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
5162 gShellDebug1HiiHandle
,
5163 Header
->MaxSnoopLatency
,
5164 Header
->MaxNoSnoopLatency
5168 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5169 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
5170 (VOID
*) (HeaderAddress
)
5172 return (EFI_SUCCESS
);
5176 Function to interpret and print out the serial number structure
5178 @param[in] HeaderAddress The Address of this capability header.
5179 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5183 PrintInterpretedExtendedCompatibilitySerialNumber (
5184 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5185 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5188 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
5189 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
5193 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
5194 gShellDebug1HiiHandle
,
5195 Header
->SerialNumber
5199 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5200 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
5201 (VOID
*) (HeaderAddress
)
5203 return (EFI_SUCCESS
);
5207 Function to interpret and print out the RCRB structure
5209 @param[in] HeaderAddress The Address of this capability header.
5210 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5214 PrintInterpretedExtendedCompatibilityRcrb (
5215 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5216 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5219 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
5220 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
5224 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
5225 gShellDebug1HiiHandle
,
5228 Header
->RcrbCapabilities
,
5233 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5234 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
5235 (VOID
*) (HeaderAddress
)
5237 return (EFI_SUCCESS
);
5241 Function to interpret and print out the vendor specific structure
5243 @param[in] HeaderAddress The Address of this capability header.
5244 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5248 PrintInterpretedExtendedCompatibilityVendorSpecific (
5249 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5250 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5253 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
5254 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
5258 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
5259 gShellDebug1HiiHandle
,
5260 Header
->VendorSpecificHeader
5264 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5265 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header
),
5266 (VOID
*) (HeaderAddress
)
5268 return (EFI_SUCCESS
);
5272 Function to interpret and print out the Event Collector Endpoint Association structure
5274 @param[in] HeaderAddress The Address of this capability header.
5275 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5279 PrintInterpretedExtendedCompatibilityECEA (
5280 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5281 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5284 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
5285 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
5289 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
5290 gShellDebug1HiiHandle
,
5291 Header
->AssociationBitmap
5295 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5296 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
5297 (VOID
*) (HeaderAddress
)
5299 return (EFI_SUCCESS
);
5303 Function to interpret and print out the ARI structure
5305 @param[in] HeaderAddress The Address of this capability header.
5306 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5310 PrintInterpretedExtendedCompatibilityAri (
5311 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5312 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5315 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
5316 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
5320 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
5321 gShellDebug1HiiHandle
,
5322 Header
->AriCapability
,
5327 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5328 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
5329 (VOID
*) (HeaderAddress
)
5331 return (EFI_SUCCESS
);
5335 Function to interpret and print out the DPA structure
5337 @param[in] HeaderAddress The Address of this capability header.
5338 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5342 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5343 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5344 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5347 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
5349 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
5353 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
5354 gShellDebug1HiiHandle
,
5355 Header
->DpaCapability
,
5356 Header
->DpaLatencyIndicator
,
5360 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
) + 1 ; LinkCount
++) {
5363 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
5364 gShellDebug1HiiHandle
,
5366 Header
->DpaPowerAllocationArray
[LinkCount
]
5371 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5372 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
),
5373 (VOID
*) (HeaderAddress
)
5375 return (EFI_SUCCESS
);
5379 Function to interpret and print out the link declaration structure
5381 @param[in] HeaderAddress The Address of this capability header.
5382 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5386 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5387 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5388 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5391 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
5393 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
5397 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
5398 gShellDebug1HiiHandle
,
5399 Header
->ElementSelfDescription
5402 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
) ; LinkCount
++) {
5405 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
5406 gShellDebug1HiiHandle
,
5408 Header
->LinkEntry
[LinkCount
]
5413 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5414 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
)-1)*sizeof(UINT32
),
5415 (VOID
*) (HeaderAddress
)
5417 return (EFI_SUCCESS
);
5421 Function to interpret and print out the Advanced Error Reporting structure
5423 @param[in] HeaderAddress The Address of this capability header.
5424 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5428 PrintInterpretedExtendedCompatibilityAer (
5429 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5430 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5433 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5434 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5438 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5439 gShellDebug1HiiHandle
,
5440 Header
->UncorrectableErrorStatus
,
5441 Header
->UncorrectableErrorMask
,
5442 Header
->UncorrectableErrorSeverity
,
5443 Header
->CorrectableErrorStatus
,
5444 Header
->CorrectableErrorMask
,
5445 Header
->AdvancedErrorCapabilitiesAndControl
,
5447 Header
->RootErrorCommand
,
5448 Header
->RootErrorStatus
,
5449 Header
->ErrorSourceIdentification
,
5450 Header
->CorrectableErrorSourceIdentification
,
5451 Header
->TlpPrefixLog
[0],
5452 Header
->TlpPrefixLog
[1],
5453 Header
->TlpPrefixLog
[2],
5454 Header
->TlpPrefixLog
[3]
5458 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5459 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5460 (VOID
*) (HeaderAddress
)
5462 return (EFI_SUCCESS
);
5466 Function to interpret and print out the multicast structure
5468 @param[in] HeaderAddress The Address of this capability header.
5469 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5470 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5474 PrintInterpretedExtendedCompatibilityMulticast (
5475 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5476 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5477 IN CONST PCIE_CAP_STRUCTURE
*PciExpressCapPtr
5480 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5481 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5485 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5486 gShellDebug1HiiHandle
,
5487 Header
->MultiCastCapability
,
5488 Header
->MulticastControl
,
5489 Header
->McBaseAddress
,
5490 Header
->McReceiveAddress
,
5492 Header
->McBlockUntranslated
,
5493 Header
->McOverlayBar
5498 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5499 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5500 (VOID
*) (HeaderAddress
)
5503 return (EFI_SUCCESS
);
5507 Function to interpret and print out the virtual channel and multi virtual channel structure
5509 @param[in] HeaderAddress The Address of this capability header.
5510 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5514 PrintInterpretedExtendedCompatibilityVirtualChannel (
5515 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5516 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5519 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5520 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5522 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5526 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5527 gShellDebug1HiiHandle
,
5528 Header
->ExtendedVcCount
,
5529 Header
->PortVcCapability1
,
5530 Header
->PortVcCapability2
,
5531 Header
->VcArbTableOffset
,
5532 Header
->PortVcControl
,
5533 Header
->PortVcStatus
5535 for (ItemCount
= 0 ; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5536 CapabilityItem
= &Header
->Capability
[ItemCount
];
5539 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5540 gShellDebug1HiiHandle
,
5542 CapabilityItem
->VcResourceCapability
,
5543 CapabilityItem
->PortArbTableOffset
,
5544 CapabilityItem
->VcResourceControl
,
5545 CapabilityItem
->VcResourceStatus
5551 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5552 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
) + (Header
->ExtendedVcCount
- 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
),
5553 (VOID
*) (HeaderAddress
)
5556 return (EFI_SUCCESS
);
5560 Function to interpret and print out the resizeable bar structure
5562 @param[in] HeaderAddress The Address of this capability header.
5563 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5567 PrintInterpretedExtendedCompatibilityResizeableBar (
5568 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5569 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5572 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
5574 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
5576 for (ItemCount
= 0 ; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) ; ItemCount
++) {
5579 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
5580 gShellDebug1HiiHandle
,
5582 Header
->Capability
[ItemCount
].ResizableBarCapability
,
5583 Header
->Capability
[ItemCount
].ResizableBarControl
5589 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5590 (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
5591 (VOID
*) (HeaderAddress
)
5594 return (EFI_SUCCESS
);
5598 Function to interpret and print out the TPH structure
5600 @param[in] HeaderAddress The Address of this capability header.
5601 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5605 PrintInterpretedExtendedCompatibilityTph (
5606 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5607 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5610 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
5611 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
5615 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
5616 gShellDebug1HiiHandle
,
5617 Header
->TphRequesterCapability
,
5618 Header
->TphRequesterControl
5622 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
5623 GET_TPH_TABLE_SIZE(Header
),
5624 (VOID
*)Header
->TphStTable
5629 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5630 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE(Header
) - sizeof(UINT16
),
5631 (VOID
*) (HeaderAddress
)
5634 return (EFI_SUCCESS
);
5638 Function to interpret and print out the secondary PCIe capability structure
5640 @param[in] HeaderAddress The Address of this capability header.
5641 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5642 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5646 PrintInterpretedExtendedCompatibilitySecondary (
5647 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5648 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5649 IN CONST PCIE_CAP_STRUCTURE
*PciExpressCapPtr
5652 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
5653 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
5657 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
5658 gShellDebug1HiiHandle
,
5659 Header
->LinkControl3
,
5660 Header
->LaneErrorStatus
5664 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
5665 PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr
->LinkCap
),
5666 (VOID
*)Header
->EqualizationControl
5671 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5672 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) - sizeof(Header
->EqualizationControl
) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr
->LinkCap
),
5673 (VOID
*) (HeaderAddress
)
5676 return (EFI_SUCCESS
);
5680 Display Pcie extended capability details
5682 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5683 @param[in] HeaderAddress The address of this capability header.
5684 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5688 PrintPciExtendedCapabilityDetails(
5689 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5690 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5691 IN CONST PCIE_CAP_STRUCTURE
*PciExpressCapPtr
5694 switch (HeaderAddress
->CapabilityId
){
5695 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
5696 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress
, HeadersBaseAddress
);
5697 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
5698 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress
, HeadersBaseAddress
);
5699 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
5700 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress
, HeadersBaseAddress
);
5701 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
5702 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress
, HeadersBaseAddress
);
5703 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
5704 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress
, HeadersBaseAddress
);
5705 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
5706 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress
, HeadersBaseAddress
);
5707 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
5708 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress
, HeadersBaseAddress
);
5709 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
5710 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress
, HeadersBaseAddress
);
5711 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
5712 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress
, HeadersBaseAddress
);
5713 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
5714 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress
, HeadersBaseAddress
);
5715 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
5716 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress
, HeadersBaseAddress
);
5717 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
5718 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress
, HeadersBaseAddress
);
5719 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
5720 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
5721 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress
, HeadersBaseAddress
);
5722 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
5724 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
5726 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5727 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
5728 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress
, HeadersBaseAddress
);
5729 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
5730 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress
, HeadersBaseAddress
);
5731 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
5732 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5734 ShellPrintEx (-1, -1,
5735 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
5736 HeaderAddress
->CapabilityId
5744 Display Pcie device structure.
5746 @param[in] IoDev The pointer to the root pci protocol.
5747 @param[in] Address The Address to start at.
5748 @param[in] CapabilityPtr The offset from the address to start.
5749 @param[in] EnhancedDump The print format for the dump data.
5753 PciExplainPciExpress (
5754 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
5756 IN UINT8 CapabilityPtr
,
5757 IN CONST UINT16 EnhancedDump
5761 PCIE_CAP_STRUCTURE PciExpressCap
;
5763 UINT64 CapRegAddress
;
5768 UINTN ExtendRegSize
;
5769 UINT64 Pciex_Address
;
5770 UINT8 DevicePortType
;
5774 PCI_EXP_EXT_HDR
*ExtHdr
;
5776 CapRegAddress
= Address
+ CapabilityPtr
;
5781 sizeof (PciExpressCap
) / sizeof (UINT32
),
5785 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
5787 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
5789 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
5790 if (ShellGetExecutionBreakFlag()) {
5793 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
5794 switch (PcieExplainList
[Index
].Width
) {
5795 case FieldWidthUINT8
:
5796 RegValue
= *(UINT8
*) RegAddr
;
5798 case FieldWidthUINT16
:
5799 RegValue
= *(UINT16
*) RegAddr
;
5801 case FieldWidthUINT32
:
5802 RegValue
= *(UINT32
*) RegAddr
;
5808 ShellPrintHiiEx(-1, -1, NULL
,
5809 PcieExplainList
[Index
].Token
,
5810 gShellDebug1HiiHandle
,
5811 PcieExplainList
[Index
].Offset
,
5814 if (PcieExplainList
[Index
].Func
== NULL
) {
5817 switch (PcieExplainList
[Index
].Type
) {
5818 case PcieExplainTypeLink
:
5820 // Link registers should not be used by
5821 // a) Root Complex Integrated Endpoint
5822 // b) Root Complex Event Collector
5824 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
5825 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
5829 case PcieExplainTypeSlot
:
5831 // Slot registers are only valid for
5832 // a) Root Port of PCI Express Root Complex
5833 // b) Downstream Port of PCI Express Switch
5834 // and when SlotImplemented bit is set in PCIE cap register.
5836 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
5837 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
5838 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
5842 case PcieExplainTypeRoot
:
5844 // Root registers are only valid for
5845 // Root Port of PCI Express Root Complex
5847 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
5854 PcieExplainList
[Index
].Func (&PciExpressCap
);
5857 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
5858 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
5859 Func
= (UINT8
) (RShiftU64 (Address
, 8));
5861 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
);
5863 ExtendRegSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
5865 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
5868 // PciRootBridgeIo protocol should support pci express extend space IO
5869 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)
5871 Status
= IoDev
->Pci
.Read (
5875 (ExtendRegSize
) / sizeof (UINT32
),
5876 (VOID
*) (ExRegBuffer
)
5878 if (EFI_ERROR (Status
) || ExRegBuffer
== NULL
) {
5879 SHELL_FREE_NON_NULL(ExRegBuffer
);
5880 return EFI_UNSUPPORTED
;
5883 if (EnhancedDump
== 0) {
5885 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
5887 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
5891 EFI_PCIE_CAPABILITY_BASE_OFFSET
,
5893 (VOID
*) (ExRegBuffer
)
5896 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExRegBuffer
;
5897 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0) {
5899 // Process this item
5901 if (EnhancedDump
== 0xFFFF || EnhancedDump
== ExtHdr
->CapabilityId
) {
5905 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR
*)ExRegBuffer
, ExtHdr
, &PciExpressCap
);
5909 // Advance to the next item if it exists
5911 if (ExtHdr
->NextCapabilityOffset
!= 0) {
5912 ExtHdr
= (PCI_EXP_EXT_HDR
*)((UINT8
*)ExRegBuffer
+ ExtHdr
->NextCapabilityOffset
);
5918 SHELL_FREE_NON_NULL(ExRegBuffer
);