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1 /** @file
2 Main file for Pci shell Debug1 function.
3
4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "UefiShellDebug1CommandsLib.h"
16 #include <Protocol/PciRootBridgeIo.h>
17 #include <Library/ShellLib.h>
18 #include <IndustryStandard/Pci.h>
19 #include <IndustryStandard/Acpi.h>
20 #include "Pci.h"
21
22 #define PCI_CLASS_STRING_LIMIT 54
23 //
24 // Printable strings for Pci class code
25 //
26 typedef struct {
27 CHAR16 *BaseClass; // Pointer to the PCI base class string
28 CHAR16 *SubClass; // Pointer to the PCI sub class string
29 CHAR16 *PIFClass; // Pointer to the PCI programming interface string
30 } PCI_CLASS_STRINGS;
31
32 //
33 // a structure holding a single entry, which also points to its lower level
34 // class
35 //
36 typedef struct PCI_CLASS_ENTRY_TAG {
37 UINT8 Code; // Class, subclass or I/F code
38 CHAR16 *DescText; // Description string
39 struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any
40 } PCI_CLASS_ENTRY;
41
42 //
43 // Declarations of entries which contain printable strings for class codes
44 // in PCI configuration space
45 //
46 PCI_CLASS_ENTRY PCIBlankEntry[];
47 PCI_CLASS_ENTRY PCISubClass_00[];
48 PCI_CLASS_ENTRY PCISubClass_01[];
49 PCI_CLASS_ENTRY PCISubClass_02[];
50 PCI_CLASS_ENTRY PCISubClass_03[];
51 PCI_CLASS_ENTRY PCISubClass_04[];
52 PCI_CLASS_ENTRY PCISubClass_05[];
53 PCI_CLASS_ENTRY PCISubClass_06[];
54 PCI_CLASS_ENTRY PCISubClass_07[];
55 PCI_CLASS_ENTRY PCISubClass_08[];
56 PCI_CLASS_ENTRY PCISubClass_09[];
57 PCI_CLASS_ENTRY PCISubClass_0a[];
58 PCI_CLASS_ENTRY PCISubClass_0b[];
59 PCI_CLASS_ENTRY PCISubClass_0c[];
60 PCI_CLASS_ENTRY PCISubClass_0d[];
61 PCI_CLASS_ENTRY PCISubClass_0e[];
62 PCI_CLASS_ENTRY PCISubClass_0f[];
63 PCI_CLASS_ENTRY PCISubClass_10[];
64 PCI_CLASS_ENTRY PCISubClass_11[];
65 PCI_CLASS_ENTRY PCIPIFClass_0101[];
66 PCI_CLASS_ENTRY PCIPIFClass_0300[];
67 PCI_CLASS_ENTRY PCIPIFClass_0604[];
68 PCI_CLASS_ENTRY PCIPIFClass_0700[];
69 PCI_CLASS_ENTRY PCIPIFClass_0701[];
70 PCI_CLASS_ENTRY PCIPIFClass_0703[];
71 PCI_CLASS_ENTRY PCIPIFClass_0800[];
72 PCI_CLASS_ENTRY PCIPIFClass_0801[];
73 PCI_CLASS_ENTRY PCIPIFClass_0802[];
74 PCI_CLASS_ENTRY PCIPIFClass_0803[];
75 PCI_CLASS_ENTRY PCIPIFClass_0904[];
76 PCI_CLASS_ENTRY PCIPIFClass_0c00[];
77 PCI_CLASS_ENTRY PCIPIFClass_0c03[];
78 PCI_CLASS_ENTRY PCIPIFClass_0e00[];
79
80 //
81 // Base class strings entries
82 //
83 PCI_CLASS_ENTRY gClassStringList[] = {
84 {
85 0x00,
86 L"Pre 2.0 device",
87 PCISubClass_00
88 },
89 {
90 0x01,
91 L"Mass Storage Controller",
92 PCISubClass_01
93 },
94 {
95 0x02,
96 L"Network Controller",
97 PCISubClass_02
98 },
99 {
100 0x03,
101 L"Display Controller",
102 PCISubClass_03
103 },
104 {
105 0x04,
106 L"Multimedia Device",
107 PCISubClass_04
108 },
109 {
110 0x05,
111 L"Memory Controller",
112 PCISubClass_05
113 },
114 {
115 0x06,
116 L"Bridge Device",
117 PCISubClass_06
118 },
119 {
120 0x07,
121 L"Simple Communications Controllers",
122 PCISubClass_07
123 },
124 {
125 0x08,
126 L"Base System Peripherals",
127 PCISubClass_08
128 },
129 {
130 0x09,
131 L"Input Devices",
132 PCISubClass_09
133 },
134 {
135 0x0a,
136 L"Docking Stations",
137 PCISubClass_0a
138 },
139 {
140 0x0b,
141 L"Processors",
142 PCISubClass_0b
143 },
144 {
145 0x0c,
146 L"Serial Bus Controllers",
147 PCISubClass_0c
148 },
149 {
150 0x0d,
151 L"Wireless Controllers",
152 PCISubClass_0d
153 },
154 {
155 0x0e,
156 L"Intelligent IO Controllers",
157 PCISubClass_0e
158 },
159 {
160 0x0f,
161 L"Satellite Communications Controllers",
162 PCISubClass_0f
163 },
164 {
165 0x10,
166 L"Encryption/Decryption Controllers",
167 PCISubClass_10
168 },
169 {
170 0x11,
171 L"Data Acquisition & Signal Processing Controllers",
172 PCISubClass_11
173 },
174 {
175 0xff,
176 L"Device does not fit in any defined classes",
177 PCIBlankEntry
178 },
179 {
180 0x00,
181 NULL,
182 /* null string ends the list */NULL
183 }
184 };
185
186 //
187 // Subclass strings entries
188 //
189 PCI_CLASS_ENTRY PCIBlankEntry[] = {
190 {
191 0x00,
192 L"",
193 PCIBlankEntry
194 },
195 {
196 0x00,
197 NULL,
198 /* null string ends the list */NULL
199 }
200 };
201
202 PCI_CLASS_ENTRY PCISubClass_00[] = {
203 {
204 0x00,
205 L"All devices other than VGA",
206 PCIBlankEntry
207 },
208 {
209 0x01,
210 L"VGA-compatible devices",
211 PCIBlankEntry
212 },
213 {
214 0x00,
215 NULL,
216 /* null string ends the list */NULL
217 }
218 };
219
220 PCI_CLASS_ENTRY PCISubClass_01[] = {
221 {
222 0x00,
223 L"SCSI controller",
224 PCIBlankEntry
225 },
226 {
227 0x01,
228 L"IDE controller",
229 PCIPIFClass_0101
230 },
231 {
232 0x02,
233 L"Floppy disk controller",
234 PCIBlankEntry
235 },
236 {
237 0x03,
238 L"IPI controller",
239 PCIBlankEntry
240 },
241 {
242 0x04,
243 L"RAID controller",
244 PCIBlankEntry
245 },
246 {
247 0x80,
248 L"Other mass storage controller",
249 PCIBlankEntry
250 },
251 {
252 0x00,
253 NULL,
254 /* null string ends the list */NULL
255 }
256 };
257
258 PCI_CLASS_ENTRY PCISubClass_02[] = {
259 {
260 0x00,
261 L"Ethernet controller",
262 PCIBlankEntry
263 },
264 {
265 0x01,
266 L"Token ring controller",
267 PCIBlankEntry
268 },
269 {
270 0x02,
271 L"FDDI controller",
272 PCIBlankEntry
273 },
274 {
275 0x03,
276 L"ATM controller",
277 PCIBlankEntry
278 },
279 {
280 0x04,
281 L"ISDN controller",
282 PCIBlankEntry
283 },
284 {
285 0x80,
286 L"Other network controller",
287 PCIBlankEntry
288 },
289 {
290 0x00,
291 NULL,
292 /* null string ends the list */NULL
293 }
294 };
295
296 PCI_CLASS_ENTRY PCISubClass_03[] = {
297 {
298 0x00,
299 L"VGA/8514 controller",
300 PCIPIFClass_0300
301 },
302 {
303 0x01,
304 L"XGA controller",
305 PCIBlankEntry
306 },
307 {
308 0x02,
309 L"3D controller",
310 PCIBlankEntry
311 },
312 {
313 0x80,
314 L"Other display controller",
315 PCIBlankEntry
316 },
317 {
318 0x00,
319 NULL,
320 /* null string ends the list */PCIBlankEntry
321 }
322 };
323
324 PCI_CLASS_ENTRY PCISubClass_04[] = {
325 {
326 0x00,
327 L"Video device",
328 PCIBlankEntry
329 },
330 {
331 0x01,
332 L"Audio device",
333 PCIBlankEntry
334 },
335 {
336 0x02,
337 L"Computer Telephony device",
338 PCIBlankEntry
339 },
340 {
341 0x80,
342 L"Other multimedia device",
343 PCIBlankEntry
344 },
345 {
346 0x00,
347 NULL,
348 /* null string ends the list */NULL
349 }
350 };
351
352 PCI_CLASS_ENTRY PCISubClass_05[] = {
353 {
354 0x00,
355 L"RAM memory controller",
356 PCIBlankEntry
357 },
358 {
359 0x01,
360 L"Flash memory controller",
361 PCIBlankEntry
362 },
363 {
364 0x80,
365 L"Other memory controller",
366 PCIBlankEntry
367 },
368 {
369 0x00,
370 NULL,
371 /* null string ends the list */NULL
372 }
373 };
374
375 PCI_CLASS_ENTRY PCISubClass_06[] = {
376 {
377 0x00,
378 L"Host/PCI bridge",
379 PCIBlankEntry
380 },
381 {
382 0x01,
383 L"PCI/ISA bridge",
384 PCIBlankEntry
385 },
386 {
387 0x02,
388 L"PCI/EISA bridge",
389 PCIBlankEntry
390 },
391 {
392 0x03,
393 L"PCI/Micro Channel bridge",
394 PCIBlankEntry
395 },
396 {
397 0x04,
398 L"PCI/PCI bridge",
399 PCIPIFClass_0604
400 },
401 {
402 0x05,
403 L"PCI/PCMCIA bridge",
404 PCIBlankEntry
405 },
406 {
407 0x06,
408 L"NuBus bridge",
409 PCIBlankEntry
410 },
411 {
412 0x07,
413 L"CardBus bridge",
414 PCIBlankEntry
415 },
416 {
417 0x08,
418 L"RACEway bridge",
419 PCIBlankEntry
420 },
421 {
422 0x80,
423 L"Other bridge type",
424 PCIBlankEntry
425 },
426 {
427 0x00,
428 NULL,
429 /* null string ends the list */NULL
430 }
431 };
432
433 PCI_CLASS_ENTRY PCISubClass_07[] = {
434 {
435 0x00,
436 L"Serial controller",
437 PCIPIFClass_0700
438 },
439 {
440 0x01,
441 L"Parallel port",
442 PCIPIFClass_0701
443 },
444 {
445 0x02,
446 L"Multiport serial controller",
447 PCIBlankEntry
448 },
449 {
450 0x03,
451 L"Modem",
452 PCIPIFClass_0703
453 },
454 {
455 0x80,
456 L"Other communication device",
457 PCIBlankEntry
458 },
459 {
460 0x00,
461 NULL,
462 /* null string ends the list */NULL
463 }
464 };
465
466 PCI_CLASS_ENTRY PCISubClass_08[] = {
467 {
468 0x00,
469 L"PIC",
470 PCIPIFClass_0800
471 },
472 {
473 0x01,
474 L"DMA controller",
475 PCIPIFClass_0801
476 },
477 {
478 0x02,
479 L"System timer",
480 PCIPIFClass_0802
481 },
482 {
483 0x03,
484 L"RTC controller",
485 PCIPIFClass_0803
486 },
487 {
488 0x04,
489 L"Generic PCI Hot-Plug controller",
490 PCIBlankEntry
491 },
492 {
493 0x80,
494 L"Other system peripheral",
495 PCIBlankEntry
496 },
497 {
498 0x00,
499 NULL,
500 /* null string ends the list */NULL
501 }
502 };
503
504 PCI_CLASS_ENTRY PCISubClass_09[] = {
505 {
506 0x00,
507 L"Keyboard controller",
508 PCIBlankEntry
509 },
510 {
511 0x01,
512 L"Digitizer (pen)",
513 PCIBlankEntry
514 },
515 {
516 0x02,
517 L"Mouse controller",
518 PCIBlankEntry
519 },
520 {
521 0x03,
522 L"Scanner controller",
523 PCIBlankEntry
524 },
525 {
526 0x04,
527 L"Gameport controller",
528 PCIPIFClass_0904
529 },
530 {
531 0x80,
532 L"Other input controller",
533 PCIBlankEntry
534 },
535 {
536 0x00,
537 NULL,
538 /* null string ends the list */NULL
539 }
540 };
541
542 PCI_CLASS_ENTRY PCISubClass_0a[] = {
543 {
544 0x00,
545 L"Generic docking station",
546 PCIBlankEntry
547 },
548 {
549 0x80,
550 L"Other type of docking station",
551 PCIBlankEntry
552 },
553 {
554 0x00,
555 NULL,
556 /* null string ends the list */NULL
557 }
558 };
559
560 PCI_CLASS_ENTRY PCISubClass_0b[] = {
561 {
562 0x00,
563 L"386",
564 PCIBlankEntry
565 },
566 {
567 0x01,
568 L"486",
569 PCIBlankEntry
570 },
571 {
572 0x02,
573 L"Pentium",
574 PCIBlankEntry
575 },
576 {
577 0x10,
578 L"Alpha",
579 PCIBlankEntry
580 },
581 {
582 0x20,
583 L"PowerPC",
584 PCIBlankEntry
585 },
586 {
587 0x30,
588 L"MIPS",
589 PCIBlankEntry
590 },
591 {
592 0x40,
593 L"Co-processor",
594 PCIBlankEntry
595 },
596 {
597 0x80,
598 L"Other processor",
599 PCIBlankEntry
600 },
601 {
602 0x00,
603 NULL,
604 /* null string ends the list */NULL
605 }
606 };
607
608 PCI_CLASS_ENTRY PCISubClass_0c[] = {
609 {
610 0x00,
611 L"Firewire(IEEE 1394)",
612 PCIPIFClass_0c03
613 },
614 {
615 0x01,
616 L"ACCESS.bus",
617 PCIBlankEntry
618 },
619 {
620 0x02,
621 L"SSA",
622 PCIBlankEntry
623 },
624 {
625 0x03,
626 L"USB",
627 PCIPIFClass_0c00
628 },
629 {
630 0x04,
631 L"Fibre Channel",
632 PCIBlankEntry
633 },
634 {
635 0x05,
636 L"System Management Bus",
637 PCIBlankEntry
638 },
639 {
640 0x80,
641 L"Other bus type",
642 PCIBlankEntry
643 },
644 {
645 0x00,
646 NULL,
647 /* null string ends the list */NULL
648 }
649 };
650
651 PCI_CLASS_ENTRY PCISubClass_0d[] = {
652 {
653 0x00,
654 L"iRDA compatible controller",
655 PCIBlankEntry
656 },
657 {
658 0x01,
659 L"Consumer IR controller",
660 PCIBlankEntry
661 },
662 {
663 0x10,
664 L"RF controller",
665 PCIBlankEntry
666 },
667 {
668 0x80,
669 L"Other type of wireless controller",
670 PCIBlankEntry
671 },
672 {
673 0x00,
674 NULL,
675 /* null string ends the list */NULL
676 }
677 };
678
679 PCI_CLASS_ENTRY PCISubClass_0e[] = {
680 {
681 0x00,
682 L"I2O Architecture",
683 PCIPIFClass_0e00
684 },
685 {
686 0x00,
687 NULL,
688 /* null string ends the list */NULL
689 }
690 };
691
692 PCI_CLASS_ENTRY PCISubClass_0f[] = {
693 {
694 0x00,
695 L"TV",
696 PCIBlankEntry
697 },
698 {
699 0x01,
700 L"Audio",
701 PCIBlankEntry
702 },
703 {
704 0x02,
705 L"Voice",
706 PCIBlankEntry
707 },
708 {
709 0x03,
710 L"Data",
711 PCIBlankEntry
712 },
713 {
714 0x00,
715 NULL,
716 /* null string ends the list */NULL
717 }
718 };
719
720 PCI_CLASS_ENTRY PCISubClass_10[] = {
721 {
722 0x00,
723 L"Network & computing Encrypt/Decrypt",
724 PCIBlankEntry
725 },
726 {
727 0x01,
728 L"Entertainment Encrypt/Decrypt",
729 PCIBlankEntry
730 },
731 {
732 0x80,
733 L"Other Encrypt/Decrypt",
734 PCIBlankEntry
735 },
736 {
737 0x00,
738 NULL,
739 /* null string ends the list */NULL
740 }
741 };
742
743 PCI_CLASS_ENTRY PCISubClass_11[] = {
744 {
745 0x00,
746 L"DPIO modules",
747 PCIBlankEntry
748 },
749 {
750 0x80,
751 L"Other DAQ & SP controllers",
752 PCIBlankEntry
753 },
754 {
755 0x00,
756 NULL,
757 /* null string ends the list */NULL
758 }
759 };
760
761 //
762 // Programming Interface entries
763 //
764 PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
765 {
766 0x00,
767 L"",
768 PCIBlankEntry
769 },
770 {
771 0x01,
772 L"OM-primary",
773 PCIBlankEntry
774 },
775 {
776 0x02,
777 L"PI-primary",
778 PCIBlankEntry
779 },
780 {
781 0x03,
782 L"OM/PI-primary",
783 PCIBlankEntry
784 },
785 {
786 0x04,
787 L"OM-secondary",
788 PCIBlankEntry
789 },
790 {
791 0x05,
792 L"OM-primary, OM-secondary",
793 PCIBlankEntry
794 },
795 {
796 0x06,
797 L"PI-primary, OM-secondary",
798 PCIBlankEntry
799 },
800 {
801 0x07,
802 L"OM/PI-primary, OM-secondary",
803 PCIBlankEntry
804 },
805 {
806 0x08,
807 L"OM-secondary",
808 PCIBlankEntry
809 },
810 {
811 0x09,
812 L"OM-primary, PI-secondary",
813 PCIBlankEntry
814 },
815 {
816 0x0a,
817 L"PI-primary, PI-secondary",
818 PCIBlankEntry
819 },
820 {
821 0x0b,
822 L"OM/PI-primary, PI-secondary",
823 PCIBlankEntry
824 },
825 {
826 0x0c,
827 L"OM-secondary",
828 PCIBlankEntry
829 },
830 {
831 0x0d,
832 L"OM-primary, OM/PI-secondary",
833 PCIBlankEntry
834 },
835 {
836 0x0e,
837 L"PI-primary, OM/PI-secondary",
838 PCIBlankEntry
839 },
840 {
841 0x0f,
842 L"OM/PI-primary, OM/PI-secondary",
843 PCIBlankEntry
844 },
845 {
846 0x80,
847 L"Master",
848 PCIBlankEntry
849 },
850 {
851 0x81,
852 L"Master, OM-primary",
853 PCIBlankEntry
854 },
855 {
856 0x82,
857 L"Master, PI-primary",
858 PCIBlankEntry
859 },
860 {
861 0x83,
862 L"Master, OM/PI-primary",
863 PCIBlankEntry
864 },
865 {
866 0x84,
867 L"Master, OM-secondary",
868 PCIBlankEntry
869 },
870 {
871 0x85,
872 L"Master, OM-primary, OM-secondary",
873 PCIBlankEntry
874 },
875 {
876 0x86,
877 L"Master, PI-primary, OM-secondary",
878 PCIBlankEntry
879 },
880 {
881 0x87,
882 L"Master, OM/PI-primary, OM-secondary",
883 PCIBlankEntry
884 },
885 {
886 0x88,
887 L"Master, OM-secondary",
888 PCIBlankEntry
889 },
890 {
891 0x89,
892 L"Master, OM-primary, PI-secondary",
893 PCIBlankEntry
894 },
895 {
896 0x8a,
897 L"Master, PI-primary, PI-secondary",
898 PCIBlankEntry
899 },
900 {
901 0x8b,
902 L"Master, OM/PI-primary, PI-secondary",
903 PCIBlankEntry
904 },
905 {
906 0x8c,
907 L"Master, OM-secondary",
908 PCIBlankEntry
909 },
910 {
911 0x8d,
912 L"Master, OM-primary, OM/PI-secondary",
913 PCIBlankEntry
914 },
915 {
916 0x8e,
917 L"Master, PI-primary, OM/PI-secondary",
918 PCIBlankEntry
919 },
920 {
921 0x8f,
922 L"Master, OM/PI-primary, OM/PI-secondary",
923 PCIBlankEntry
924 },
925 {
926 0x00,
927 NULL,
928 /* null string ends the list */NULL
929 }
930 };
931
932 PCI_CLASS_ENTRY PCIPIFClass_0300[] = {
933 {
934 0x00,
935 L"VGA compatible",
936 PCIBlankEntry
937 },
938 {
939 0x01,
940 L"8514 compatible",
941 PCIBlankEntry
942 },
943 {
944 0x00,
945 NULL,
946 /* null string ends the list */NULL
947 }
948 };
949
950 PCI_CLASS_ENTRY PCIPIFClass_0604[] = {
951 {
952 0x00,
953 L"",
954 PCIBlankEntry
955 },
956 {
957 0x01,
958 L"Subtractive decode",
959 PCIBlankEntry
960 },
961 {
962 0x00,
963 NULL,
964 /* null string ends the list */NULL
965 }
966 };
967
968 PCI_CLASS_ENTRY PCIPIFClass_0700[] = {
969 {
970 0x00,
971 L"Generic XT-compatible",
972 PCIBlankEntry
973 },
974 {
975 0x01,
976 L"16450-compatible",
977 PCIBlankEntry
978 },
979 {
980 0x02,
981 L"16550-compatible",
982 PCIBlankEntry
983 },
984 {
985 0x03,
986 L"16650-compatible",
987 PCIBlankEntry
988 },
989 {
990 0x04,
991 L"16750-compatible",
992 PCIBlankEntry
993 },
994 {
995 0x05,
996 L"16850-compatible",
997 PCIBlankEntry
998 },
999 {
1000 0x06,
1001 L"16950-compatible",
1002 PCIBlankEntry
1003 },
1004 {
1005 0x00,
1006 NULL,
1007 /* null string ends the list */NULL
1008 }
1009 };
1010
1011 PCI_CLASS_ENTRY PCIPIFClass_0701[] = {
1012 {
1013 0x00,
1014 L"",
1015 PCIBlankEntry
1016 },
1017 {
1018 0x01,
1019 L"Bi-directional",
1020 PCIBlankEntry
1021 },
1022 {
1023 0x02,
1024 L"ECP 1.X-compliant",
1025 PCIBlankEntry
1026 },
1027 {
1028 0x03,
1029 L"IEEE 1284",
1030 PCIBlankEntry
1031 },
1032 {
1033 0xfe,
1034 L"IEEE 1284 target (not a controller)",
1035 PCIBlankEntry
1036 },
1037 {
1038 0x00,
1039 NULL,
1040 /* null string ends the list */NULL
1041 }
1042 };
1043
1044 PCI_CLASS_ENTRY PCIPIFClass_0703[] = {
1045 {
1046 0x00,
1047 L"Generic",
1048 PCIBlankEntry
1049 },
1050 {
1051 0x01,
1052 L"Hayes-compatible 16450",
1053 PCIBlankEntry
1054 },
1055 {
1056 0x02,
1057 L"Hayes-compatible 16550",
1058 PCIBlankEntry
1059 },
1060 {
1061 0x03,
1062 L"Hayes-compatible 16650",
1063 PCIBlankEntry
1064 },
1065 {
1066 0x04,
1067 L"Hayes-compatible 16750",
1068 PCIBlankEntry
1069 },
1070 {
1071 0x00,
1072 NULL,
1073 /* null string ends the list */NULL
1074 }
1075 };
1076
1077 PCI_CLASS_ENTRY PCIPIFClass_0800[] = {
1078 {
1079 0x00,
1080 L"Generic 8259",
1081 PCIBlankEntry
1082 },
1083 {
1084 0x01,
1085 L"ISA",
1086 PCIBlankEntry
1087 },
1088 {
1089 0x02,
1090 L"EISA",
1091 PCIBlankEntry
1092 },
1093 {
1094 0x10,
1095 L"IO APIC",
1096 PCIBlankEntry
1097 },
1098 {
1099 0x20,
1100 L"IO(x) APIC interrupt controller",
1101 PCIBlankEntry
1102 },
1103 {
1104 0x00,
1105 NULL,
1106 /* null string ends the list */NULL
1107 }
1108 };
1109
1110 PCI_CLASS_ENTRY PCIPIFClass_0801[] = {
1111 {
1112 0x00,
1113 L"Generic 8237",
1114 PCIBlankEntry
1115 },
1116 {
1117 0x01,
1118 L"ISA",
1119 PCIBlankEntry
1120 },
1121 {
1122 0x02,
1123 L"EISA",
1124 PCIBlankEntry
1125 },
1126 {
1127 0x00,
1128 NULL,
1129 /* null string ends the list */NULL
1130 }
1131 };
1132
1133 PCI_CLASS_ENTRY PCIPIFClass_0802[] = {
1134 {
1135 0x00,
1136 L"Generic 8254",
1137 PCIBlankEntry
1138 },
1139 {
1140 0x01,
1141 L"ISA",
1142 PCIBlankEntry
1143 },
1144 {
1145 0x02,
1146 L"EISA",
1147 PCIBlankEntry
1148 },
1149 {
1150 0x00,
1151 NULL,
1152 /* null string ends the list */NULL
1153 }
1154 };
1155
1156 PCI_CLASS_ENTRY PCIPIFClass_0803[] = {
1157 {
1158 0x00,
1159 L"Generic",
1160 PCIBlankEntry
1161 },
1162 {
1163 0x01,
1164 L"ISA",
1165 PCIBlankEntry
1166 },
1167 {
1168 0x02,
1169 L"EISA",
1170 PCIBlankEntry
1171 },
1172 {
1173 0x00,
1174 NULL,
1175 /* null string ends the list */NULL
1176 }
1177 };
1178
1179 PCI_CLASS_ENTRY PCIPIFClass_0904[] = {
1180 {
1181 0x00,
1182 L"Generic",
1183 PCIBlankEntry
1184 },
1185 {
1186 0x10,
1187 L"",
1188 PCIBlankEntry
1189 },
1190 {
1191 0x00,
1192 NULL,
1193 /* null string ends the list */NULL
1194 }
1195 };
1196
1197 PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
1198 {
1199 0x00,
1200 L"Universal Host Controller spec",
1201 PCIBlankEntry
1202 },
1203 {
1204 0x10,
1205 L"Open Host Controller spec",
1206 PCIBlankEntry
1207 },
1208 {
1209 0x80,
1210 L"No specific programming interface",
1211 PCIBlankEntry
1212 },
1213 {
1214 0xfe,
1215 L"(Not Host Controller)",
1216 PCIBlankEntry
1217 },
1218 {
1219 0x00,
1220 NULL,
1221 /* null string ends the list */NULL
1222 }
1223 };
1224
1225 PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {
1226 {
1227 0x00,
1228 L"",
1229 PCIBlankEntry
1230 },
1231 {
1232 0x10,
1233 L"Using 1394 OpenHCI spec",
1234 PCIBlankEntry
1235 },
1236 {
1237 0x00,
1238 NULL,
1239 /* null string ends the list */NULL
1240 }
1241 };
1242
1243 PCI_CLASS_ENTRY PCIPIFClass_0e00[] = {
1244 {
1245 0x00,
1246 L"Message FIFO at offset 40h",
1247 PCIBlankEntry
1248 },
1249 {
1250 0x01,
1251 L"",
1252 PCIBlankEntry
1253 },
1254 {
1255 0x00,
1256 NULL,
1257 /* null string ends the list */NULL
1258 }
1259 };
1260
1261
1262 /**
1263 Generates printable Unicode strings that represent PCI device class,
1264 subclass and programmed I/F based on a value passed to the function.
1265
1266 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1267 PCI device. The encodings are:
1268 bits 23:16 - Base Class Code
1269 bits 15:8 - Sub-Class Code
1270 bits 7:0 - Programming Interface
1271 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1272 printable class strings corresponding to ClassCode. The
1273 caller must not modify the strings that are pointed by
1274 the fields in ClassStrings.
1275 **/
1276 VOID
1277 PciGetClassStrings (
1278 IN UINT32 ClassCode,
1279 IN OUT PCI_CLASS_STRINGS *ClassStrings
1280 )
1281 {
1282 INTN Index;
1283 UINT8 Code;
1284 PCI_CLASS_ENTRY *CurrentClass;
1285
1286 //
1287 // Assume no strings found
1288 //
1289 ClassStrings->BaseClass = L"UNDEFINED";
1290 ClassStrings->SubClass = L"UNDEFINED";
1291 ClassStrings->PIFClass = L"UNDEFINED";
1292
1293 CurrentClass = gClassStringList;
1294 Code = (UINT8) (ClassCode >> 16);
1295 Index = 0;
1296
1297 //
1298 // Go through all entries of the base class, until the entry with a matching
1299 // base class code is found. If reaches an entry with a null description
1300 // text, the last entry is met, which means no text for the base class was
1301 // found, so no more action is needed.
1302 //
1303 while (Code != CurrentClass[Index].Code) {
1304 if (NULL == CurrentClass[Index].DescText) {
1305 return ;
1306 }
1307
1308 Index++;
1309 }
1310 //
1311 // A base class was found. Assign description, and check if this class has
1312 // sub-class defined. If sub-class defined, no more action is needed,
1313 // otherwise, continue to find description for the sub-class code.
1314 //
1315 ClassStrings->BaseClass = CurrentClass[Index].DescText;
1316 if (NULL == CurrentClass[Index].LowerLevelClass) {
1317 return ;
1318 }
1319 //
1320 // find Subclass entry
1321 //
1322 CurrentClass = CurrentClass[Index].LowerLevelClass;
1323 Code = (UINT8) (ClassCode >> 8);
1324 Index = 0;
1325
1326 //
1327 // Go through all entries of the sub-class, until the entry with a matching
1328 // sub-class code is found. If reaches an entry with a null description
1329 // text, the last entry is met, which means no text for the sub-class was
1330 // found, so no more action is needed.
1331 //
1332 while (Code != CurrentClass[Index].Code) {
1333 if (NULL == CurrentClass[Index].DescText) {
1334 return ;
1335 }
1336
1337 Index++;
1338 }
1339 //
1340 // A class was found for the sub-class code. Assign description, and check if
1341 // this sub-class has programming interface defined. If no, no more action is
1342 // needed, otherwise, continue to find description for the programming
1343 // interface.
1344 //
1345 ClassStrings->SubClass = CurrentClass[Index].DescText;
1346 if (NULL == CurrentClass[Index].LowerLevelClass) {
1347 return ;
1348 }
1349 //
1350 // Find programming interface entry
1351 //
1352 CurrentClass = CurrentClass[Index].LowerLevelClass;
1353 Code = (UINT8) ClassCode;
1354 Index = 0;
1355
1356 //
1357 // Go through all entries of the I/F entries, until the entry with a
1358 // matching I/F code is found. If reaches an entry with a null description
1359 // text, the last entry is met, which means no text was found, so no more
1360 // action is needed.
1361 //
1362 while (Code != CurrentClass[Index].Code) {
1363 if (NULL == CurrentClass[Index].DescText) {
1364 return ;
1365 }
1366
1367 Index++;
1368 }
1369 //
1370 // A class was found for the I/F code. Assign description, done!
1371 //
1372 ClassStrings->PIFClass = CurrentClass[Index].DescText;
1373 return ;
1374 }
1375
1376 /**
1377 Print strings that represent PCI device class, subclass and programmed I/F.
1378
1379 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1380 configuation space.
1381 @param[in] IncludePIF If the printed string should include the programming I/F part
1382 **/
1383 VOID
1384 PciPrintClassCode (
1385 IN UINT8 *ClassCodePtr,
1386 IN BOOLEAN IncludePIF
1387 )
1388 {
1389 UINT32 ClassCode;
1390 PCI_CLASS_STRINGS ClassStrings;
1391 CHAR16 OutputString[PCI_CLASS_STRING_LIMIT + 1];
1392
1393 ClassCode = 0;
1394 ClassCode |= ClassCodePtr[0];
1395 ClassCode |= (ClassCodePtr[1] << 8);
1396 ClassCode |= (ClassCodePtr[2] << 16);
1397
1398 //
1399 // Get name from class code
1400 //
1401 PciGetClassStrings (ClassCode, &ClassStrings);
1402
1403 if (IncludePIF) {
1404 //
1405 // Only print base class and sub class name
1406 //
1407 ShellPrintEx(-1,-1, L"%s - %s - %s",
1408 ClassStrings.BaseClass,
1409 ClassStrings.SubClass,
1410 ClassStrings.PIFClass
1411 );
1412
1413 } else {
1414 //
1415 // Print base class, sub class, and programming inferface name
1416 //
1417 UnicodeSPrint (
1418 OutputString,
1419 PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),
1420 L"%s - %s",
1421 ClassStrings.BaseClass,
1422 ClassStrings.SubClass
1423 );
1424
1425 OutputString[PCI_CLASS_STRING_LIMIT] = 0;
1426 ShellPrintEx(-1,-1, L"%s", OutputString);
1427 }
1428 }
1429
1430 /**
1431 This function finds out the protocol which is in charge of the given
1432 segment, and its bus range covers the current bus number. It lookes
1433 each instances of RootBridgeIoProtocol handle, until the one meets the
1434 criteria is found.
1435
1436 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1437 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1438 @param[in] Segment Segment number of device we are dealing with.
1439 @param[in] Bus Bus number of device we are dealing with.
1440 @param[out] IoDev Handle used to access configuration space of PCI device.
1441
1442 @retval EFI_SUCCESS The command completed successfully.
1443 @retval EFI_INVALID_PARAMETER Invalid parameter.
1444
1445 **/
1446 EFI_STATUS
1447 PciFindProtocolInterface (
1448 IN EFI_HANDLE *HandleBuf,
1449 IN UINTN HandleCount,
1450 IN UINT16 Segment,
1451 IN UINT16 Bus,
1452 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev
1453 );
1454
1455 /**
1456 This function gets the protocol interface from the given handle, and
1457 obtains its address space descriptors.
1458
1459 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1460 @param[out] IoDev Handle used to access configuration space of PCI device.
1461 @param[out] Descriptors Points to the address space descriptors.
1462
1463 @retval EFI_SUCCESS The command completed successfully
1464 **/
1465 EFI_STATUS
1466 PciGetProtocolAndResource (
1467 IN EFI_HANDLE Handle,
1468 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,
1469 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
1470 );
1471
1472 /**
1473 This function get the next bus range of given address space descriptors.
1474 It also moves the pointer backward a node, to get prepared to be called
1475 again.
1476
1477 @param[in, out] Descriptors Points to current position of a serial of address space
1478 descriptors.
1479 @param[out] MinBus The lower range of bus number.
1480 @param[out] MaxBus The upper range of bus number.
1481 @param[out] IsEnd Meet end of the serial of descriptors.
1482
1483 @retval EFI_SUCCESS The command completed successfully.
1484 **/
1485 EFI_STATUS
1486 PciGetNextBusRange (
1487 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
1488 OUT UINT16 *MinBus,
1489 OUT UINT16 *MaxBus,
1490 OUT BOOLEAN *IsEnd
1491 );
1492
1493 /**
1494 Explain the data in PCI configuration space. The part which is common for
1495 PCI device and bridge is interpreted in this function. It calls other
1496 functions to interpret data unique for device or bridge.
1497
1498 @param[in] ConfigSpace Data in PCI configuration space.
1499 @param[in] Address Address used to access configuration space of this PCI device.
1500 @param[in] IoDev Handle used to access configuration space of PCI device.
1501
1502 @retval EFI_SUCCESS The command completed successfully.
1503 **/
1504 EFI_STATUS
1505 PciExplainData (
1506 IN PCI_CONFIG_SPACE *ConfigSpace,
1507 IN UINT64 Address,
1508 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1509 );
1510
1511 /**
1512 Explain the device specific part of data in PCI configuration space.
1513
1514 @param[in] Device Data in PCI configuration space.
1515 @param[in] Address Address used to access configuration space of this PCI device.
1516 @param[in] IoDev Handle used to access configuration space of PCI device.
1517
1518 @retval EFI_SUCCESS The command completed successfully.
1519 **/
1520 EFI_STATUS
1521 PciExplainDeviceData (
1522 IN PCI_DEVICE_HEADER *Device,
1523 IN UINT64 Address,
1524 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1525 );
1526
1527 /**
1528 Explain the bridge specific part of data in PCI configuration space.
1529
1530 @param[in] Bridge Bridge specific data region in PCI configuration space.
1531 @param[in] Address Address used to access configuration space of this PCI device.
1532 @param[in] IoDev Handle used to access configuration space of PCI device.
1533
1534 @retval EFI_SUCCESS The command completed successfully.
1535 **/
1536 EFI_STATUS
1537 PciExplainBridgeData (
1538 IN PCI_BRIDGE_HEADER *Bridge,
1539 IN UINT64 Address,
1540 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1541 );
1542
1543 /**
1544 Explain the Base Address Register(Bar) in PCI configuration space.
1545
1546 @param[in] Bar Points to the Base Address Register intended to interpret.
1547 @param[in] Command Points to the register Command.
1548 @param[in] Address Address used to access configuration space of this PCI device.
1549 @param[in] IoDev Handle used to access configuration space of PCI device.
1550 @param[in, out] Index The Index.
1551
1552 @retval EFI_SUCCESS The command completed successfully.
1553 **/
1554 EFI_STATUS
1555 PciExplainBar (
1556 IN UINT32 *Bar,
1557 IN UINT16 *Command,
1558 IN UINT64 Address,
1559 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
1560 IN OUT UINTN *Index
1561 );
1562
1563 /**
1564 Explain the cardbus specific part of data in PCI configuration space.
1565
1566 @param[in] CardBus CardBus specific region of PCI configuration space.
1567 @param[in] Address Address used to access configuration space of this PCI device.
1568 @param[in] IoDev Handle used to access configuration space of PCI device.
1569
1570 @retval EFI_SUCCESS The command completed successfully.
1571 **/
1572 EFI_STATUS
1573 PciExplainCardBusData (
1574 IN PCI_CARDBUS_HEADER *CardBus,
1575 IN UINT64 Address,
1576 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
1577 );
1578
1579 /**
1580 Explain each meaningful bit of register Status. The definition of Status is
1581 slightly different depending on the PCI header type.
1582
1583 @param[in] Status Points to the content of register Status.
1584 @param[in] MainStatus Indicates if this register is main status(not secondary
1585 status).
1586 @param[in] HeaderType Header type of this PCI device.
1587
1588 @retval EFI_SUCCESS The command completed successfully.
1589 **/
1590 EFI_STATUS
1591 PciExplainStatus (
1592 IN UINT16 *Status,
1593 IN BOOLEAN MainStatus,
1594 IN PCI_HEADER_TYPE HeaderType
1595 );
1596
1597 /**
1598 Explain each meaningful bit of register Command.
1599
1600 @param[in] Command Points to the content of register Command.
1601
1602 @retval EFI_SUCCESS The command completed successfully.
1603 **/
1604 EFI_STATUS
1605 PciExplainCommand (
1606 IN UINT16 *Command
1607 );
1608
1609 /**
1610 Explain each meaningful bit of register Bridge Control.
1611
1612 @param[in] BridgeControl Points to the content of register Bridge Control.
1613 @param[in] HeaderType The headertype.
1614
1615 @retval EFI_SUCCESS The command completed successfully.
1616 **/
1617 EFI_STATUS
1618 PciExplainBridgeControl (
1619 IN UINT16 *BridgeControl,
1620 IN PCI_HEADER_TYPE HeaderType
1621 );
1622
1623 /**
1624 Print each capability structure.
1625
1626 @param[in] IoDev The pointer to the deivce.
1627 @param[in] Address The address to start at.
1628 @param[in] CapPtr The offset from the address.
1629
1630 @retval EFI_SUCCESS The operation was successful.
1631 **/
1632 EFI_STATUS
1633 PciExplainCapabilityStruct (
1634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
1635 IN UINT64 Address,
1636 IN UINT8 CapPtr
1637 );
1638
1639 /**
1640 Display Pcie device structure.
1641
1642 @param[in] IoDev The pointer to the root pci protocol.
1643 @param[in] Address The Address to start at.
1644 @param[in] CapabilityPtr The offset from the address to start.
1645 **/
1646 EFI_STATUS
1647 PciExplainPciExpress (
1648 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
1649 IN UINT64 Address,
1650 IN UINT8 CapabilityPtr
1651 );
1652
1653 /**
1654 Print out information of the capability information.
1655
1656 @param[in] PciExpressCap The pointer to the structure about the device.
1657
1658 @retval EFI_SUCCESS The operation was successful.
1659 **/
1660 EFI_STATUS
1661 ExplainPcieCapReg (
1662 IN PCIE_CAP_STURCTURE *PciExpressCap
1663 );
1664
1665 /**
1666 Print out information of the device capability information.
1667
1668 @param[in] PciExpressCap The pointer to the structure about the device.
1669
1670 @retval EFI_SUCCESS The operation was successful.
1671 **/
1672 EFI_STATUS
1673 ExplainPcieDeviceCap (
1674 IN PCIE_CAP_STURCTURE *PciExpressCap
1675 );
1676
1677 /**
1678 Print out information of the device control information.
1679
1680 @param[in] PciExpressCap The pointer to the structure about the device.
1681
1682 @retval EFI_SUCCESS The operation was successful.
1683 **/
1684 EFI_STATUS
1685 ExplainPcieDeviceControl (
1686 IN PCIE_CAP_STURCTURE *PciExpressCap
1687 );
1688
1689 /**
1690 Print out information of the device status information.
1691
1692 @param[in] PciExpressCap The pointer to the structure about the device.
1693
1694 @retval EFI_SUCCESS The operation was successful.
1695 **/
1696 EFI_STATUS
1697 ExplainPcieDeviceStatus (
1698 IN PCIE_CAP_STURCTURE *PciExpressCap
1699 );
1700
1701 /**
1702 Print out information of the device link information.
1703
1704 @param[in] PciExpressCap The pointer to the structure about the device.
1705
1706 @retval EFI_SUCCESS The operation was successful.
1707 **/
1708 EFI_STATUS
1709 ExplainPcieLinkCap (
1710 IN PCIE_CAP_STURCTURE *PciExpressCap
1711 );
1712
1713 /**
1714 Print out information of the device link control information.
1715
1716 @param[in] PciExpressCap The pointer to the structure about the device.
1717
1718 @retval EFI_SUCCESS The operation was successful.
1719 **/
1720 EFI_STATUS
1721 ExplainPcieLinkControl (
1722 IN PCIE_CAP_STURCTURE *PciExpressCap
1723 );
1724
1725 /**
1726 Print out information of the device link status information.
1727
1728 @param[in] PciExpressCap The pointer to the structure about the device.
1729
1730 @retval EFI_SUCCESS The operation was successful.
1731 **/
1732 EFI_STATUS
1733 ExplainPcieLinkStatus (
1734 IN PCIE_CAP_STURCTURE *PciExpressCap
1735 );
1736
1737 /**
1738 Print out information of the device slot information.
1739
1740 @param[in] PciExpressCap The pointer to the structure about the device.
1741
1742 @retval EFI_SUCCESS The operation was successful.
1743 **/
1744 EFI_STATUS
1745 ExplainPcieSlotCap (
1746 IN PCIE_CAP_STURCTURE *PciExpressCap
1747 );
1748
1749 /**
1750 Print out information of the device slot control information.
1751
1752 @param[in] PciExpressCap The pointer to the structure about the device.
1753
1754 @retval EFI_SUCCESS The operation was successful.
1755 **/
1756 EFI_STATUS
1757 ExplainPcieSlotControl (
1758 IN PCIE_CAP_STURCTURE *PciExpressCap
1759 );
1760
1761 /**
1762 Print out information of the device slot status information.
1763
1764 @param[in] PciExpressCap The pointer to the structure about the device.
1765
1766 @retval EFI_SUCCESS The operation was successful.
1767 **/
1768 EFI_STATUS
1769 ExplainPcieSlotStatus (
1770 IN PCIE_CAP_STURCTURE *PciExpressCap
1771 );
1772
1773 /**
1774 Print out information of the device root information.
1775
1776 @param[in] PciExpressCap The pointer to the structure about the device.
1777
1778 @retval EFI_SUCCESS The operation was successful.
1779 **/
1780 EFI_STATUS
1781 ExplainPcieRootControl (
1782 IN PCIE_CAP_STURCTURE *PciExpressCap
1783 );
1784
1785 /**
1786 Print out information of the device root capability information.
1787
1788 @param[in] PciExpressCap The pointer to the structure about the device.
1789
1790 @retval EFI_SUCCESS The operation was successful.
1791 **/
1792 EFI_STATUS
1793 ExplainPcieRootCap (
1794 IN PCIE_CAP_STURCTURE *PciExpressCap
1795 );
1796
1797 /**
1798 Print out information of the device root status information.
1799
1800 @param[in] PciExpressCap The pointer to the structure about the device.
1801
1802 @retval EFI_SUCCESS The operation was successful.
1803 **/
1804 EFI_STATUS
1805 ExplainPcieRootStatus (
1806 IN PCIE_CAP_STURCTURE *PciExpressCap
1807 );
1808
1809 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);
1810
1811 typedef enum {
1812 FieldWidthUINT8,
1813 FieldWidthUINT16,
1814 FieldWidthUINT32
1815 } PCIE_CAPREG_FIELD_WIDTH;
1816
1817 typedef enum {
1818 PcieExplainTypeCommon,
1819 PcieExplainTypeDevice,
1820 PcieExplainTypeLink,
1821 PcieExplainTypeSlot,
1822 PcieExplainTypeRoot,
1823 PcieExplainTypeMax
1824 } PCIE_EXPLAIN_TYPE;
1825
1826 typedef struct
1827 {
1828 UINT16 Token;
1829 UINTN Offset;
1830 PCIE_CAPREG_FIELD_WIDTH Width;
1831 PCIE_EXPLAIN_FUNCTION Func;
1832 PCIE_EXPLAIN_TYPE Type;
1833 } PCIE_EXPLAIN_STRUCT;
1834
1835 PCIE_EXPLAIN_STRUCT PcieExplainList[] = {
1836 {
1837 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID),
1838 0x00,
1839 FieldWidthUINT8,
1840 NULL,
1841 PcieExplainTypeCommon
1842 },
1843 {
1844 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR),
1845 0x01,
1846 FieldWidthUINT8,
1847 NULL,
1848 PcieExplainTypeCommon
1849 },
1850 {
1851 STRING_TOKEN (STR_PCIEX_CAP_REGISTER),
1852 0x02,
1853 FieldWidthUINT16,
1854 ExplainPcieCapReg,
1855 PcieExplainTypeCommon
1856 },
1857 {
1858 STRING_TOKEN (STR_PCIEX_DEVICE_CAP),
1859 0x04,
1860 FieldWidthUINT32,
1861 ExplainPcieDeviceCap,
1862 PcieExplainTypeDevice
1863 },
1864 {
1865 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL),
1866 0x08,
1867 FieldWidthUINT16,
1868 ExplainPcieDeviceControl,
1869 PcieExplainTypeDevice
1870 },
1871 {
1872 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS),
1873 0x0a,
1874 FieldWidthUINT16,
1875 ExplainPcieDeviceStatus,
1876 PcieExplainTypeDevice
1877 },
1878 {
1879 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES),
1880 0x0c,
1881 FieldWidthUINT32,
1882 ExplainPcieLinkCap,
1883 PcieExplainTypeLink
1884 },
1885 {
1886 STRING_TOKEN (STR_PCIEX_LINK_CONTROL),
1887 0x10,
1888 FieldWidthUINT16,
1889 ExplainPcieLinkControl,
1890 PcieExplainTypeLink
1891 },
1892 {
1893 STRING_TOKEN (STR_PCIEX_LINK_STATUS),
1894 0x12,
1895 FieldWidthUINT16,
1896 ExplainPcieLinkStatus,
1897 PcieExplainTypeLink
1898 },
1899 {
1900 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES),
1901 0x14,
1902 FieldWidthUINT32,
1903 ExplainPcieSlotCap,
1904 PcieExplainTypeSlot
1905 },
1906 {
1907 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL),
1908 0x18,
1909 FieldWidthUINT16,
1910 ExplainPcieSlotControl,
1911 PcieExplainTypeSlot
1912 },
1913 {
1914 STRING_TOKEN (STR_PCIEX_SLOT_STATUS),
1915 0x1a,
1916 FieldWidthUINT16,
1917 ExplainPcieSlotStatus,
1918 PcieExplainTypeSlot
1919 },
1920 {
1921 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL),
1922 0x1c,
1923 FieldWidthUINT16,
1924 ExplainPcieRootControl,
1925 PcieExplainTypeRoot
1926 },
1927 {
1928 STRING_TOKEN (STR_PCIEX_RSVDP),
1929 0x1e,
1930 FieldWidthUINT16,
1931 ExplainPcieRootCap,
1932 PcieExplainTypeRoot
1933 },
1934 {
1935 STRING_TOKEN (STR_PCIEX_ROOT_STATUS),
1936 0x20,
1937 FieldWidthUINT32,
1938 ExplainPcieRootStatus,
1939 PcieExplainTypeRoot
1940 },
1941 {
1942 0,
1943 0,
1944 (PCIE_CAPREG_FIELD_WIDTH)0,
1945 NULL,
1946 PcieExplainTypeMax
1947 }
1948 };
1949
1950 //
1951 // Global Variables
1952 //
1953 PCI_CONFIG_SPACE *mConfigSpace = NULL;
1954 STATIC CONST SHELL_PARAM_ITEM ParamList[] = {
1955 {L"-s", TypeValue},
1956 {L"-i", TypeFlag},
1957 {NULL, TypeMax}
1958 };
1959
1960 CHAR16 *DevicePortTypeTable[] = {
1961 L"PCI Express Endpoint",
1962 L"Legacy PCI Express Endpoint",
1963 L"Unknown Type",
1964 L"Unknonw Type",
1965 L"Root Port of PCI Express Root Complex",
1966 L"Upstream Port of PCI Express Switch",
1967 L"Downstream Port of PCI Express Switch",
1968 L"PCI Express to PCI/PCI-X Bridge",
1969 L"PCI/PCI-X to PCI Express Bridge",
1970 L"Root Complex Integrated Endpoint",
1971 L"Root Complex Event Collector"
1972 };
1973
1974 CHAR16 *L0sLatencyStrTable[] = {
1975 L"Less than 64ns",
1976 L"64ns to less than 128ns",
1977 L"128ns to less than 256ns",
1978 L"256ns to less than 512ns",
1979 L"512ns to less than 1us",
1980 L"1us to less than 2us",
1981 L"2us-4us",
1982 L"More than 4us"
1983 };
1984
1985 CHAR16 *L1LatencyStrTable[] = {
1986 L"Less than 1us",
1987 L"1us to less than 2us",
1988 L"2us to less than 4us",
1989 L"4us to less than 8us",
1990 L"8us to less than 16us",
1991 L"16us to less than 32us",
1992 L"32us-64us",
1993 L"More than 64us"
1994 };
1995
1996 CHAR16 *ASPMCtrlStrTable[] = {
1997 L"Disabled",
1998 L"L0s Entry Enabled",
1999 L"L1 Entry Enabled",
2000 L"L0s and L1 Entry Enabled"
2001 };
2002
2003 CHAR16 *SlotPwrLmtScaleTable[] = {
2004 L"1.0x",
2005 L"0.1x",
2006 L"0.01x",
2007 L"0.001x"
2008 };
2009
2010 CHAR16 *IndicatorTable[] = {
2011 L"Reserved",
2012 L"On",
2013 L"Blink",
2014 L"Off"
2015 };
2016
2017
2018 /**
2019 Function for 'pci' command.
2020
2021 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2022 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2023 **/
2024 SHELL_STATUS
2025 EFIAPI
2026 ShellCommandRunPci (
2027 IN EFI_HANDLE ImageHandle,
2028 IN EFI_SYSTEM_TABLE *SystemTable
2029 )
2030 {
2031 UINT16 Segment;
2032 UINT16 Bus;
2033 UINT16 Device;
2034 UINT16 Func;
2035 UINT64 Address;
2036 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev;
2037 EFI_STATUS Status;
2038 PCI_COMMON_HEADER PciHeader;
2039 PCI_CONFIG_SPACE ConfigSpace;
2040 UINTN ScreenCount;
2041 UINTN TempColumn;
2042 UINTN ScreenSize;
2043 BOOLEAN ExplainData;
2044 UINTN Index;
2045 UINTN SizeOfHeader;
2046 BOOLEAN PrintTitle;
2047 UINTN HandleBufSize;
2048 EFI_HANDLE *HandleBuf;
2049 UINTN HandleCount;
2050 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
2051 UINT16 MinBus;
2052 UINT16 MaxBus;
2053 BOOLEAN IsEnd;
2054 LIST_ENTRY *Package;
2055 CHAR16 *ProblemParam;
2056 SHELL_STATUS ShellStatus;
2057 CONST CHAR16 *Temp;
2058
2059 ShellStatus = SHELL_SUCCESS;
2060 Status = EFI_SUCCESS;
2061 Address = 0;
2062 IoDev = NULL;
2063 HandleBuf = NULL;
2064 Package = NULL;
2065
2066 //
2067 // initialize the shell lib (we must be in non-auto-init...)
2068 //
2069 Status = ShellInitialize();
2070 ASSERT_EFI_ERROR(Status);
2071
2072 Status = CommandInit();
2073 ASSERT_EFI_ERROR(Status);
2074
2075 //
2076 // parse the command line
2077 //
2078 Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
2079 if (EFI_ERROR(Status)) {
2080 if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {
2081 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);
2082 FreePool(ProblemParam);
2083 ShellStatus = SHELL_INVALID_PARAMETER;
2084 } else {
2085 ASSERT(FALSE);
2086 }
2087 } else {
2088
2089 if (ShellCommandLineGetCount(Package) == 2) {
2090 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);
2091 ShellStatus = SHELL_INVALID_PARAMETER;
2092 goto Done;
2093 }
2094
2095 if (ShellCommandLineGetCount(Package) > 4) {
2096 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
2097 ShellStatus = SHELL_INVALID_PARAMETER;
2098 goto Done;
2099 }
2100 if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {
2101 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");
2102 ShellStatus = SHELL_INVALID_PARAMETER;
2103 goto Done;
2104 }
2105 //
2106 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2107 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2108 // space for handles and call it again.
2109 //
2110 HandleBufSize = sizeof (EFI_HANDLE);
2111 HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);
2112 if (HandleBuf == NULL) {
2113 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
2114 ShellStatus = SHELL_OUT_OF_RESOURCES;
2115 goto Done;
2116 }
2117
2118 Status = gBS->LocateHandle (
2119 ByProtocol,
2120 &gEfiPciRootBridgeIoProtocolGuid,
2121 NULL,
2122 &HandleBufSize,
2123 HandleBuf
2124 );
2125
2126 if (Status == EFI_BUFFER_TOO_SMALL) {
2127 HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);
2128 if (HandleBuf == NULL) {
2129 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
2130 ShellStatus = SHELL_OUT_OF_RESOURCES;
2131 goto Done;
2132 }
2133
2134 Status = gBS->LocateHandle (
2135 ByProtocol,
2136 &gEfiPciRootBridgeIoProtocolGuid,
2137 NULL,
2138 &HandleBufSize,
2139 HandleBuf
2140 );
2141 }
2142
2143 if (EFI_ERROR (Status)) {
2144 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);
2145 ShellStatus = SHELL_NOT_FOUND;
2146 goto Done;
2147 }
2148
2149 HandleCount = HandleBufSize / sizeof (EFI_HANDLE);
2150 //
2151 // Argument Count == 1(no other argument): enumerate all pci functions
2152 //
2153 if (ShellCommandLineGetCount(Package) == 1) {
2154 gST->ConOut->QueryMode (
2155 gST->ConOut,
2156 gST->ConOut->Mode->Mode,
2157 &TempColumn,
2158 &ScreenSize
2159 );
2160
2161 ScreenCount = 0;
2162 ScreenSize -= 4;
2163 if ((ScreenSize & 1) == 1) {
2164 ScreenSize -= 1;
2165 }
2166
2167 PrintTitle = TRUE;
2168
2169 //
2170 // For each handle, which decides a segment and a bus number range,
2171 // enumerate all devices on it.
2172 //
2173 for (Index = 0; Index < HandleCount; Index++) {
2174 Status = PciGetProtocolAndResource (
2175 HandleBuf[Index],
2176 &IoDev,
2177 &Descriptors
2178 );
2179 if (EFI_ERROR (Status)) {
2180 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);
2181 ShellStatus = SHELL_NOT_FOUND;
2182 goto Done;
2183 }
2184 //
2185 // No document say it's impossible for a RootBridgeIo protocol handle
2186 // to have more than one address space descriptors, so find out every
2187 // bus range and for each of them do device enumeration.
2188 //
2189 while (TRUE) {
2190 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
2191
2192 if (EFI_ERROR (Status)) {
2193 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);
2194 ShellStatus = SHELL_NOT_FOUND;
2195 goto Done;
2196 }
2197
2198 if (IsEnd) {
2199 break;
2200 }
2201
2202 for (Bus = MinBus; Bus <= MaxBus; Bus++) {
2203 //
2204 // For each devices, enumerate all functions it contains
2205 //
2206 for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
2207 //
2208 // For each function, read its configuration space and print summary
2209 //
2210 for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
2211 if (ShellGetExecutionBreakFlag ()) {
2212 ShellStatus = SHELL_ABORTED;
2213 goto Done;
2214 }
2215 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);
2216 IoDev->Pci.Read (
2217 IoDev,
2218 EfiPciWidthUint16,
2219 Address,
2220 1,
2221 &PciHeader.VendorId
2222 );
2223
2224 //
2225 // If VendorId = 0xffff, there does not exist a device at this
2226 // location. For each device, if there is any function on it,
2227 // there must be 1 function at Function 0. So if Func = 0, there
2228 // will be no more functions in the same device, so we can break
2229 // loop to deal with the next device.
2230 //
2231 if (PciHeader.VendorId == 0xffff && Func == 0) {
2232 break;
2233 }
2234
2235 if (PciHeader.VendorId != 0xffff) {
2236
2237 if (PrintTitle) {
2238 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);
2239 PrintTitle = FALSE;
2240 }
2241
2242 IoDev->Pci.Read (
2243 IoDev,
2244 EfiPciWidthUint32,
2245 Address,
2246 sizeof (PciHeader) / sizeof (UINT32),
2247 &PciHeader
2248 );
2249
2250 ShellPrintHiiEx(
2251 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,
2252 IoDev->SegmentNumber,
2253 Bus,
2254 Device,
2255 Func
2256 );
2257
2258 PciPrintClassCode (PciHeader.ClassCode, FALSE);
2259 ShellPrintHiiEx(
2260 -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,
2261 PciHeader.VendorId,
2262 PciHeader.DeviceId,
2263 PciHeader.ClassCode[0]
2264 );
2265
2266 ScreenCount += 2;
2267 if (ScreenCount >= ScreenSize && ScreenSize != 0) {
2268 //
2269 // If ScreenSize == 0 we have the console redirected so don't
2270 // block updates
2271 //
2272 ScreenCount = 0;
2273 }
2274 //
2275 // If this is not a multi-function device, we can leave the loop
2276 // to deal with the next device.
2277 //
2278 if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {
2279 break;
2280 }
2281 }
2282 }
2283 }
2284 }
2285 //
2286 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2287 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2288 // devices on all bus, we can leave loop.
2289 //
2290 if (Descriptors == NULL) {
2291 break;
2292 }
2293 }
2294 }
2295
2296 Status = EFI_SUCCESS;
2297 goto Done;
2298 }
2299
2300 ExplainData = FALSE;
2301 Segment = 0;
2302 Bus = 0;
2303 Device = 0;
2304 Func = 0;
2305 if (ShellCommandLineGetFlag(Package, L"-i")) {
2306 ExplainData = TRUE;
2307 }
2308
2309 Temp = ShellCommandLineGetValue(Package, L"-s");
2310 if (Temp != NULL) {
2311 Segment = (UINT16) ShellStrToUintn (Temp);
2312 }
2313
2314 //
2315 // The first Argument(except "-i") is assumed to be Bus number, second
2316 // to be Device number, and third to be Func number.
2317 //
2318 Temp = ShellCommandLineGetRawValue(Package, 1);
2319 if (Temp != NULL) {
2320 Bus = (UINT16)ShellStrToUintn(Temp);
2321 if (Bus > MAX_BUS_NUMBER) {
2322 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
2323 ShellStatus = SHELL_INVALID_PARAMETER;
2324 goto Done;
2325 }
2326 }
2327 Temp = ShellCommandLineGetRawValue(Package, 2);
2328 if (Temp != NULL) {
2329 Device = (UINT16) ShellStrToUintn(Temp);
2330 if (Device > MAX_DEVICE_NUMBER){
2331 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
2332 ShellStatus = SHELL_INVALID_PARAMETER;
2333 goto Done;
2334 }
2335 }
2336
2337 Temp = ShellCommandLineGetRawValue(Package, 3);
2338 if (Temp != NULL) {
2339 Func = (UINT16) ShellStrToUintn(Temp);
2340 if (Func > MAX_FUNCTION_NUMBER){
2341 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
2342 ShellStatus = SHELL_INVALID_PARAMETER;
2343 goto Done;
2344 }
2345 }
2346
2347 //
2348 // Find the protocol interface who's in charge of current segment, and its
2349 // bus range covers the current bus
2350 //
2351 Status = PciFindProtocolInterface (
2352 HandleBuf,
2353 HandleCount,
2354 Segment,
2355 Bus,
2356 &IoDev
2357 );
2358
2359 if (EFI_ERROR (Status)) {
2360 ShellPrintHiiEx(
2361 -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,
2362 gShellDebug1HiiHandle,
2363 Segment,
2364 Bus
2365 );
2366 ShellStatus = SHELL_NOT_FOUND;
2367 goto Done;
2368 }
2369
2370 Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);
2371 Status = IoDev->Pci.Read (
2372 IoDev,
2373 EfiPciWidthUint8,
2374 Address,
2375 sizeof (ConfigSpace),
2376 &ConfigSpace
2377 );
2378
2379 if (EFI_ERROR (Status)) {
2380 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);
2381 ShellStatus = SHELL_ACCESS_DENIED;
2382 goto Done;
2383 }
2384
2385 mConfigSpace = &ConfigSpace;
2386 ShellPrintHiiEx(
2387 -1,
2388 -1,
2389 NULL,
2390 STRING_TOKEN (STR_PCI_INFO),
2391 gShellDebug1HiiHandle,
2392 Segment,
2393 Bus,
2394 Device,
2395 Func,
2396 Segment,
2397 Bus,
2398 Device,
2399 Func
2400 );
2401
2402 //
2403 // Dump standard header of configuration space
2404 //
2405 SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);
2406
2407 DumpHex (2, 0, SizeOfHeader, &ConfigSpace);
2408 ShellPrintEx(-1,-1, L"\r\n");
2409
2410 //
2411 // Dump device dependent Part of configuration space
2412 //
2413 DumpHex (
2414 2,
2415 SizeOfHeader,
2416 sizeof (ConfigSpace) - SizeOfHeader,
2417 ConfigSpace.Data
2418 );
2419
2420 //
2421 // If "-i" appears in command line, interpret data in configuration space
2422 //
2423 if (ExplainData) {
2424 Status = PciExplainData (&ConfigSpace, Address, IoDev);
2425 }
2426 }
2427 Done:
2428 if (HandleBuf != NULL) {
2429 FreePool (HandleBuf);
2430 }
2431 if (Package != NULL) {
2432 ShellCommandLineFreeVarList (Package);
2433 }
2434 mConfigSpace = NULL;
2435 return ShellStatus;
2436 }
2437
2438 /**
2439 This function finds out the protocol which is in charge of the given
2440 segment, and its bus range covers the current bus number. It lookes
2441 each instances of RootBridgeIoProtocol handle, until the one meets the
2442 criteria is found.
2443
2444 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2445 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2446 @param[in] Segment Segment number of device we are dealing with.
2447 @param[in] Bus Bus number of device we are dealing with.
2448 @param[out] IoDev Handle used to access configuration space of PCI device.
2449
2450 @retval EFI_SUCCESS The command completed successfully.
2451 @retval EFI_INVALID_PARAMETER Invalid parameter.
2452
2453 **/
2454 EFI_STATUS
2455 PciFindProtocolInterface (
2456 IN EFI_HANDLE *HandleBuf,
2457 IN UINTN HandleCount,
2458 IN UINT16 Segment,
2459 IN UINT16 Bus,
2460 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev
2461 )
2462 {
2463 UINTN Index;
2464 EFI_STATUS Status;
2465 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
2466 UINT16 MinBus;
2467 UINT16 MaxBus;
2468 BOOLEAN IsEnd;
2469
2470 //
2471 // Go through all handles, until the one meets the criteria is found
2472 //
2473 for (Index = 0; Index < HandleCount; Index++) {
2474 Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);
2475 if (EFI_ERROR (Status)) {
2476 return Status;
2477 }
2478 //
2479 // When Descriptors == NULL, the Configuration() is not implemented,
2480 // so we only check the Segment number
2481 //
2482 if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {
2483 return EFI_SUCCESS;
2484 }
2485
2486 if ((*IoDev)->SegmentNumber != Segment) {
2487 continue;
2488 }
2489
2490 while (TRUE) {
2491 Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
2492 if (EFI_ERROR (Status)) {
2493 return Status;
2494 }
2495
2496 if (IsEnd) {
2497 break;
2498 }
2499
2500 if (MinBus <= Bus && MaxBus >= Bus) {
2501 return EFI_SUCCESS;
2502 }
2503 }
2504 }
2505
2506 return EFI_NOT_FOUND;
2507 }
2508
2509 /**
2510 This function gets the protocol interface from the given handle, and
2511 obtains its address space descriptors.
2512
2513 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2514 @param[out] IoDev Handle used to access configuration space of PCI device.
2515 @param[out] Descriptors Points to the address space descriptors.
2516
2517 @retval EFI_SUCCESS The command completed successfully
2518 **/
2519 EFI_STATUS
2520 PciGetProtocolAndResource (
2521 IN EFI_HANDLE Handle,
2522 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **IoDev,
2523 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
2524 )
2525 {
2526 EFI_STATUS Status;
2527
2528 //
2529 // Get inferface from protocol
2530 //
2531 Status = gBS->HandleProtocol (
2532 Handle,
2533 &gEfiPciRootBridgeIoProtocolGuid,
2534 (VOID**)IoDev
2535 );
2536
2537 if (EFI_ERROR (Status)) {
2538 return Status;
2539 }
2540 //
2541 // Call Configuration() to get address space descriptors
2542 //
2543 Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);
2544 if (Status == EFI_UNSUPPORTED) {
2545 *Descriptors = NULL;
2546 return EFI_SUCCESS;
2547
2548 } else {
2549 return Status;
2550 }
2551 }
2552
2553 /**
2554 This function get the next bus range of given address space descriptors.
2555 It also moves the pointer backward a node, to get prepared to be called
2556 again.
2557
2558 @param[in, out] Descriptors Points to current position of a serial of address space
2559 descriptors.
2560 @param[out] MinBus The lower range of bus number.
2561 @param[out] MaxBus The upper range of bus number.
2562 @param[out] IsEnd Meet end of the serial of descriptors.
2563
2564 @retval EFI_SUCCESS The command completed successfully.
2565 **/
2566 EFI_STATUS
2567 PciGetNextBusRange (
2568 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
2569 OUT UINT16 *MinBus,
2570 OUT UINT16 *MaxBus,
2571 OUT BOOLEAN *IsEnd
2572 )
2573 {
2574 *IsEnd = FALSE;
2575
2576 //
2577 // When *Descriptors is NULL, Configuration() is not implemented, so assume
2578 // range is 0~PCI_MAX_BUS
2579 //
2580 if ((*Descriptors) == NULL) {
2581 *MinBus = 0;
2582 *MaxBus = PCI_MAX_BUS;
2583 return EFI_SUCCESS;
2584 }
2585 //
2586 // *Descriptors points to one or more address space descriptors, which
2587 // ends with a end tagged descriptor. Examine each of the descriptors,
2588 // if a bus typed one is found and its bus range covers bus, this handle
2589 // is the handle we are looking for.
2590 //
2591
2592 while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
2593 if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
2594 *MinBus = (UINT16) (*Descriptors)->AddrRangeMin;
2595 *MaxBus = (UINT16) (*Descriptors)->AddrRangeMax;
2596 (*Descriptors)++;
2597 return (EFI_SUCCESS);
2598 }
2599
2600 (*Descriptors)++;
2601 }
2602
2603 if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {
2604 *IsEnd = TRUE;
2605 }
2606
2607 return EFI_SUCCESS;
2608 }
2609
2610 /**
2611 Explain the data in PCI configuration space. The part which is common for
2612 PCI device and bridge is interpreted in this function. It calls other
2613 functions to interpret data unique for device or bridge.
2614
2615 @param[in] ConfigSpace Data in PCI configuration space.
2616 @param[in] Address Address used to access configuration space of this PCI device.
2617 @param[in] IoDev Handle used to access configuration space of PCI device.
2618
2619 @retval EFI_SUCCESS The command completed successfully.
2620 **/
2621 EFI_STATUS
2622 PciExplainData (
2623 IN PCI_CONFIG_SPACE *ConfigSpace,
2624 IN UINT64 Address,
2625 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
2626 )
2627 {
2628 PCI_COMMON_HEADER *Common;
2629 PCI_HEADER_TYPE HeaderType;
2630 EFI_STATUS Status;
2631 UINT8 CapPtr;
2632
2633 Common = &(ConfigSpace->Common);
2634
2635 Print (L"\n");
2636
2637 //
2638 // Print Vendor Id and Device Id
2639 //
2640 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,
2641 INDEX_OF (&(Common->VendorId)),
2642 Common->VendorId,
2643 INDEX_OF (&(Common->DeviceId)),
2644 Common->DeviceId
2645 );
2646
2647 //
2648 // Print register Command
2649 //
2650 PciExplainCommand (&(Common->Command));
2651
2652 //
2653 // Print register Status
2654 //
2655 PciExplainStatus (&(Common->Status), TRUE, PciUndefined);
2656
2657 //
2658 // Print register Revision ID
2659 //
2660 ShellPrintEx(-1, -1, L"/r/n");
2661 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,
2662 INDEX_OF (&(Common->RevisionId)),
2663 Common->RevisionId
2664 );
2665
2666 //
2667 // Print register BIST
2668 //
2669 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));
2670 if ((Common->Bist & PCI_BIT_7) != 0) {
2671 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);
2672 } else {
2673 ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);
2674 }
2675 //
2676 // Print register Cache Line Size
2677 //
2678 ShellPrintHiiEx(-1, -1, NULL,
2679 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE),
2680 gShellDebug1HiiHandle,
2681 INDEX_OF (&(Common->CacheLineSize)),
2682 Common->CacheLineSize
2683 );
2684
2685 //
2686 // Print register Latency Timer
2687 //
2688 ShellPrintHiiEx(-1, -1, NULL,
2689 STRING_TOKEN (STR_PCI2_LATENCY_TIMER),
2690 gShellDebug1HiiHandle,
2691 INDEX_OF (&(Common->PrimaryLatencyTimer)),
2692 Common->PrimaryLatencyTimer
2693 );
2694
2695 //
2696 // Print register Header Type
2697 //
2698 ShellPrintHiiEx(-1, -1, NULL,
2699 STRING_TOKEN (STR_PCI2_HEADER_TYPE),
2700 gShellDebug1HiiHandle,
2701 INDEX_OF (&(Common->HeaderType)),
2702 Common->HeaderType
2703 );
2704
2705 if ((Common->HeaderType & PCI_BIT_7) != 0) {
2706 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);
2707
2708 } else {
2709 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);
2710 }
2711
2712 HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);
2713 switch (HeaderType) {
2714 case PciDevice:
2715 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);
2716 break;
2717
2718 case PciP2pBridge:
2719 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);
2720 break;
2721
2722 case PciCardBusBridge:
2723 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);
2724 break;
2725
2726 default:
2727 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);
2728 HeaderType = PciUndefined;
2729 }
2730
2731 //
2732 // Print register Class Code
2733 //
2734 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);
2735 PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);
2736 Print (L"\n");
2737
2738 if (ShellGetExecutionBreakFlag()) {
2739 return EFI_SUCCESS;
2740 }
2741
2742 //
2743 // Interpret remaining part of PCI configuration header depending on
2744 // HeaderType
2745 //
2746 CapPtr = 0;
2747 Status = EFI_SUCCESS;
2748 switch (HeaderType) {
2749 case PciDevice:
2750 Status = PciExplainDeviceData (
2751 &(ConfigSpace->NonCommon.Device),
2752 Address,
2753 IoDev
2754 );
2755 CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;
2756 break;
2757
2758 case PciP2pBridge:
2759 Status = PciExplainBridgeData (
2760 &(ConfigSpace->NonCommon.Bridge),
2761 Address,
2762 IoDev
2763 );
2764 CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;
2765 break;
2766
2767 case PciCardBusBridge:
2768 Status = PciExplainCardBusData (
2769 &(ConfigSpace->NonCommon.CardBus),
2770 Address,
2771 IoDev
2772 );
2773 CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;
2774 break;
2775 case PciUndefined:
2776 default:
2777 break;
2778 }
2779 //
2780 // If Status bit4 is 1, dump or explain capability structure
2781 //
2782 if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {
2783 PciExplainCapabilityStruct (IoDev, Address, CapPtr);
2784 }
2785
2786 return Status;
2787 }
2788
2789 /**
2790 Explain the device specific part of data in PCI configuration space.
2791
2792 @param[in] Device Data in PCI configuration space.
2793 @param[in] Address Address used to access configuration space of this PCI device.
2794 @param[in] IoDev Handle used to access configuration space of PCI device.
2795
2796 @retval EFI_SUCCESS The command completed successfully.
2797 **/
2798 EFI_STATUS
2799 PciExplainDeviceData (
2800 IN PCI_DEVICE_HEADER *Device,
2801 IN UINT64 Address,
2802 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
2803 )
2804 {
2805 UINTN Index;
2806 BOOLEAN BarExist;
2807 EFI_STATUS Status;
2808 UINTN BarCount;
2809
2810 //
2811 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2812 // exist. If these no Bar for this function, print "none", otherwise
2813 // list detail information about this Bar.
2814 //
2815 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));
2816
2817 BarExist = FALSE;
2818 BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);
2819 for (Index = 0; Index < BarCount; Index++) {
2820 if (Device->Bar[Index] == 0) {
2821 continue;
2822 }
2823
2824 if (!BarExist) {
2825 BarExist = TRUE;
2826 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);
2827 Print (L" --------------------------------------------------------------------------");
2828 }
2829
2830 Status = PciExplainBar (
2831 &(Device->Bar[Index]),
2832 &(mConfigSpace->Common.Command),
2833 Address,
2834 IoDev,
2835 &Index
2836 );
2837
2838 if (EFI_ERROR (Status)) {
2839 break;
2840 }
2841 }
2842
2843 if (!BarExist) {
2844 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
2845
2846 } else {
2847 Print (L"\n --------------------------------------------------------------------------");
2848 }
2849
2850 //
2851 // Print register Expansion ROM Base Address
2852 //
2853 if ((Device->ROMBar & PCI_BIT_0) == 0) {
2854 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));
2855
2856 } else {
2857 ShellPrintHiiEx(-1, -1, NULL,
2858 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE),
2859 gShellDebug1HiiHandle,
2860 INDEX_OF (&(Device->ROMBar)),
2861 Device->ROMBar
2862 );
2863 }
2864 //
2865 // Print register Cardbus CIS ptr
2866 //
2867 ShellPrintHiiEx(-1, -1, NULL,
2868 STRING_TOKEN (STR_PCI2_CARDBUS_CIS),
2869 gShellDebug1HiiHandle,
2870 INDEX_OF (&(Device->CardBusCISPtr)),
2871 Device->CardBusCISPtr
2872 );
2873
2874 //
2875 // Print register Sub-vendor ID and subsystem ID
2876 //
2877 ShellPrintHiiEx(-1, -1, NULL,
2878 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID),
2879 gShellDebug1HiiHandle,
2880 INDEX_OF (&(Device->SubVendorId)),
2881 Device->SubVendorId
2882 );
2883
2884 ShellPrintHiiEx(-1, -1, NULL,
2885 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID),
2886 gShellDebug1HiiHandle,
2887 INDEX_OF (&(Device->SubSystemId)),
2888 Device->SubSystemId
2889 );
2890
2891 //
2892 // Print register Capabilities Ptr
2893 //
2894 ShellPrintHiiEx(-1, -1, NULL,
2895 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR),
2896 gShellDebug1HiiHandle,
2897 INDEX_OF (&(Device->CapabilitiesPtr)),
2898 Device->CapabilitiesPtr
2899 );
2900
2901 //
2902 // Print register Interrupt Line and interrupt pin
2903 //
2904 ShellPrintHiiEx(-1, -1, NULL,
2905 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE),
2906 gShellDebug1HiiHandle,
2907 INDEX_OF (&(Device->InterruptLine)),
2908 Device->InterruptLine
2909 );
2910
2911 ShellPrintHiiEx(-1, -1, NULL,
2912 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),
2913 gShellDebug1HiiHandle,
2914 INDEX_OF (&(Device->InterruptPin)),
2915 Device->InterruptPin
2916 );
2917
2918 //
2919 // Print register Min_Gnt and Max_Lat
2920 //
2921 ShellPrintHiiEx(-1, -1, NULL,
2922 STRING_TOKEN (STR_PCI2_MIN_GNT),
2923 gShellDebug1HiiHandle,
2924 INDEX_OF (&(Device->MinGnt)),
2925 Device->MinGnt
2926 );
2927
2928 ShellPrintHiiEx(-1, -1, NULL,
2929 STRING_TOKEN (STR_PCI2_MAX_LAT),
2930 gShellDebug1HiiHandle,
2931 INDEX_OF (&(Device->MaxLat)),
2932 Device->MaxLat
2933 );
2934
2935 return EFI_SUCCESS;
2936 }
2937
2938 /**
2939 Explain the bridge specific part of data in PCI configuration space.
2940
2941 @param[in] Bridge Bridge specific data region in PCI configuration space.
2942 @param[in] Address Address used to access configuration space of this PCI device.
2943 @param[in] IoDev Handle used to access configuration space of PCI device.
2944
2945 @retval EFI_SUCCESS The command completed successfully.
2946 **/
2947 EFI_STATUS
2948 PciExplainBridgeData (
2949 IN PCI_BRIDGE_HEADER *Bridge,
2950 IN UINT64 Address,
2951 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
2952 )
2953 {
2954 UINTN Index;
2955 BOOLEAN BarExist;
2956 UINTN BarCount;
2957 UINT32 IoAddress32;
2958 EFI_STATUS Status;
2959
2960 //
2961 // Print Base Address Registers. When Bar = 0, this Bar does not
2962 // exist. If these no Bar for this function, print "none", otherwise
2963 // list detail information about this Bar.
2964 //
2965 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));
2966
2967 BarExist = FALSE;
2968 BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);
2969
2970 for (Index = 0; Index < BarCount; Index++) {
2971 if (Bridge->Bar[Index] == 0) {
2972 continue;
2973 }
2974
2975 if (!BarExist) {
2976 BarExist = TRUE;
2977 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);
2978 Print (L" --------------------------------------------------------------------------");
2979 }
2980
2981 Status = PciExplainBar (
2982 &(Bridge->Bar[Index]),
2983 &(mConfigSpace->Common.Command),
2984 Address,
2985 IoDev,
2986 &Index
2987 );
2988
2989 if (EFI_ERROR (Status)) {
2990 break;
2991 }
2992 }
2993
2994 if (!BarExist) {
2995 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
2996 } else {
2997 Print (L"\n --------------------------------------------------------------------------");
2998 }
2999
3000 //
3001 // Expansion register ROM Base Address
3002 //
3003 if ((Bridge->ROMBar & PCI_BIT_0) == 0) {
3004 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));
3005
3006 } else {
3007 ShellPrintHiiEx(-1, -1, NULL,
3008 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2),
3009 gShellDebug1HiiHandle,
3010 INDEX_OF (&(Bridge->ROMBar)),
3011 Bridge->ROMBar
3012 );
3013 }
3014 //
3015 // Print Bus Numbers(Primary, Secondary, and Subordinate
3016 //
3017 ShellPrintHiiEx(-1, -1, NULL,
3018 STRING_TOKEN (STR_PCI2_BUS_NUMBERS),
3019 gShellDebug1HiiHandle,
3020 INDEX_OF (&(Bridge->PrimaryBus)),
3021 INDEX_OF (&(Bridge->SecondaryBus)),
3022 INDEX_OF (&(Bridge->SubordinateBus))
3023 );
3024
3025 Print (L" ------------------------------------------------------\n");
3026
3027 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);
3028 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);
3029 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);
3030
3031 //
3032 // Print register Secondary Latency Timer
3033 //
3034 ShellPrintHiiEx(-1, -1, NULL,
3035 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER),
3036 gShellDebug1HiiHandle,
3037 INDEX_OF (&(Bridge->SecondaryLatencyTimer)),
3038 Bridge->SecondaryLatencyTimer
3039 );
3040
3041 //
3042 // Print register Secondary Status
3043 //
3044 PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);
3045
3046 //
3047 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3048 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3049 // base and limit address are listed.
3050 //
3051 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);
3052 Print (L"----------------------------------------------------------------------\n");
3053
3054 //
3055 // IO Base & Limit
3056 //
3057 IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);
3058 IoAddress32 &= 0xfffff000;
3059 ShellPrintHiiEx(-1, -1, NULL,
3060 STRING_TOKEN (STR_PCI2_TWO_VARS),
3061 gShellDebug1HiiHandle,
3062 INDEX_OF (&(Bridge->IoBase)),
3063 IoAddress32
3064 );
3065
3066 IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);
3067 IoAddress32 |= 0x00000fff;
3068 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);
3069
3070 //
3071 // Memory Base & Limit
3072 //
3073 ShellPrintHiiEx(-1, -1, NULL,
3074 STRING_TOKEN (STR_PCI2_MEMORY),
3075 gShellDebug1HiiHandle,
3076 INDEX_OF (&(Bridge->MemoryBase)),
3077 (Bridge->MemoryBase << 16) & 0xfff00000
3078 );
3079
3080 ShellPrintHiiEx(-1, -1, NULL,
3081 STRING_TOKEN (STR_PCI2_ONE_VAR),
3082 gShellDebug1HiiHandle,
3083 (Bridge->MemoryLimit << 16) | 0x000fffff
3084 );
3085
3086 //
3087 // Pre-fetch-able Memory Base & Limit
3088 //
3089 ShellPrintHiiEx(-1, -1, NULL,
3090 STRING_TOKEN (STR_PCI2_PREFETCHABLE),
3091 gShellDebug1HiiHandle,
3092 INDEX_OF (&(Bridge->PrefetchableMemBase)),
3093 Bridge->PrefetchableBaseUpper,
3094 (Bridge->PrefetchableMemBase << 16) & 0xfff00000
3095 );
3096
3097 ShellPrintHiiEx(-1, -1, NULL,
3098 STRING_TOKEN (STR_PCI2_TWO_VARS_2),
3099 gShellDebug1HiiHandle,
3100 Bridge->PrefetchableLimitUpper,
3101 (Bridge->PrefetchableMemLimit << 16) | 0x000fffff
3102 );
3103
3104 //
3105 // Print register Capabilities Pointer
3106 //
3107 ShellPrintHiiEx(-1, -1, NULL,
3108 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2),
3109 gShellDebug1HiiHandle,
3110 INDEX_OF (&(Bridge->CapabilitiesPtr)),
3111 Bridge->CapabilitiesPtr
3112 );
3113
3114 //
3115 // Print register Bridge Control
3116 //
3117 PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);
3118
3119 //
3120 // Print register Interrupt Line & PIN
3121 //
3122 ShellPrintHiiEx(-1, -1, NULL,
3123 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2),
3124 gShellDebug1HiiHandle,
3125 INDEX_OF (&(Bridge->InterruptLine)),
3126 Bridge->InterruptLine
3127 );
3128
3129 ShellPrintHiiEx(-1, -1, NULL,
3130 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN),
3131 gShellDebug1HiiHandle,
3132 INDEX_OF (&(Bridge->InterruptPin)),
3133 Bridge->InterruptPin
3134 );
3135
3136 return EFI_SUCCESS;
3137 }
3138
3139 /**
3140 Explain the Base Address Register(Bar) in PCI configuration space.
3141
3142 @param[in] Bar Points to the Base Address Register intended to interpret.
3143 @param[in] Command Points to the register Command.
3144 @param[in] Address Address used to access configuration space of this PCI device.
3145 @param[in] IoDev Handle used to access configuration space of PCI device.
3146 @param[in, out] Index The Index.
3147
3148 @retval EFI_SUCCESS The command completed successfully.
3149 **/
3150 EFI_STATUS
3151 PciExplainBar (
3152 IN UINT32 *Bar,
3153 IN UINT16 *Command,
3154 IN UINT64 Address,
3155 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
3156 IN OUT UINTN *Index
3157 )
3158 {
3159 UINT16 OldCommand;
3160 UINT16 NewCommand;
3161 UINT64 Bar64;
3162 UINT32 OldBar32;
3163 UINT32 NewBar32;
3164 UINT64 OldBar64;
3165 UINT64 NewBar64;
3166 BOOLEAN IsMem;
3167 BOOLEAN IsBar32;
3168 UINT64 RegAddress;
3169
3170 IsBar32 = TRUE;
3171 Bar64 = 0;
3172 NewBar32 = 0;
3173 NewBar64 = 0;
3174
3175 //
3176 // According the bar type, list detail about this bar, for example: 32 or
3177 // 64 bits; pre-fetchable or not.
3178 //
3179 if ((*Bar & PCI_BIT_0) == 0) {
3180 //
3181 // This bar is of memory type
3182 //
3183 IsMem = TRUE;
3184
3185 if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {
3186 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
3187 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
3188 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);
3189
3190 } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {
3191 Bar64 = 0x0;
3192 CopyMem (&Bar64, Bar, sizeof (UINT64));
3193 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, (UINT32) RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));
3194 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));
3195 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
3196 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);
3197 IsBar32 = FALSE;
3198 *Index += 1;
3199
3200 } else {
3201 //
3202 // Reserved
3203 //
3204 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
3205 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);
3206 }
3207
3208 if ((*Bar & PCI_BIT_3) == 0) {
3209 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);
3210
3211 } else {
3212 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);
3213 }
3214
3215 } else {
3216 //
3217 // This bar is of io type
3218 //
3219 IsMem = FALSE;
3220 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);
3221 Print (L"I/O ");
3222 }
3223
3224 //
3225 // Get BAR length(or the amount of resource this bar demands for). To get
3226 // Bar length, first we should temporarily disable I/O and memory access
3227 // of this function(by set bits in the register Command), then write all
3228 // "1"s to this bar. The bar value read back is the amount of resource
3229 // this bar demands for.
3230 //
3231 //
3232 // Disable io & mem access
3233 //
3234 OldCommand = *Command;
3235 NewCommand = (UINT16) (OldCommand & 0xfffc);
3236 RegAddress = Address | INDEX_OF (Command);
3237 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);
3238
3239 RegAddress = Address | INDEX_OF (Bar);
3240
3241 //
3242 // Read after write the BAR to get the size
3243 //
3244 if (IsBar32) {
3245 OldBar32 = *Bar;
3246 NewBar32 = 0xffffffff;
3247
3248 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
3249 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
3250 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);
3251
3252 if (IsMem) {
3253 NewBar32 = NewBar32 & 0xfffffff0;
3254 NewBar32 = (~NewBar32) + 1;
3255
3256 } else {
3257 NewBar32 = NewBar32 & 0xfffffffc;
3258 NewBar32 = (~NewBar32) + 1;
3259 NewBar32 = NewBar32 & 0x0000ffff;
3260 }
3261 } else {
3262
3263 OldBar64 = 0x0;
3264 CopyMem (&OldBar64, Bar, sizeof (UINT64));
3265 NewBar64 = 0xffffffffffffffffULL;
3266
3267 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
3268 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
3269 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);
3270
3271 if (IsMem) {
3272 NewBar64 = NewBar64 & 0xfffffffffffffff0ULL;
3273 NewBar64 = (~NewBar64) + 1;
3274
3275 } else {
3276 NewBar64 = NewBar64 & 0xfffffffffffffffcULL;
3277 NewBar64 = (~NewBar64) + 1;
3278 NewBar64 = NewBar64 & 0x000000000000ffff;
3279 }
3280 }
3281 //
3282 // Enable io & mem access
3283 //
3284 RegAddress = Address | INDEX_OF (Command);
3285 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);
3286
3287 if (IsMem) {
3288 if (IsBar32) {
3289 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);
3290 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);
3291
3292 } else {
3293 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) RShiftU64 (NewBar64, 32));
3294 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);
3295 Print (L" ");
3296 ShellPrintHiiEx(-1, -1, NULL,
3297 STRING_TOKEN (STR_PCI2_RSHIFT),
3298 gShellDebug1HiiHandle,
3299 (UINT32) RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)
3300 );
3301 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));
3302
3303 }
3304 } else {
3305 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);
3306 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);
3307 }
3308
3309 return EFI_SUCCESS;
3310 }
3311
3312 /**
3313 Explain the cardbus specific part of data in PCI configuration space.
3314
3315 @param[in] CardBus CardBus specific region of PCI configuration space.
3316 @param[in] Address Address used to access configuration space of this PCI device.
3317 @param[in] IoDev Handle used to access configuration space of PCI device.
3318
3319 @retval EFI_SUCCESS The command completed successfully.
3320 **/
3321 EFI_STATUS
3322 PciExplainCardBusData (
3323 IN PCI_CARDBUS_HEADER *CardBus,
3324 IN UINT64 Address,
3325 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
3326 )
3327 {
3328 BOOLEAN Io32Bit;
3329 PCI_CARDBUS_DATA *CardBusData;
3330
3331 ShellPrintHiiEx(-1, -1, NULL,
3332 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET),
3333 gShellDebug1HiiHandle,
3334 INDEX_OF (&(CardBus->CardBusSocketReg)),
3335 CardBus->CardBusSocketReg
3336 );
3337
3338 //
3339 // Print Secondary Status
3340 //
3341 PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);
3342
3343 //
3344 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3345 // Subordinate bus number
3346 //
3347 ShellPrintHiiEx(-1, -1, NULL,
3348 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2),
3349 gShellDebug1HiiHandle,
3350 INDEX_OF (&(CardBus->PciBusNumber)),
3351 INDEX_OF (&(CardBus->CardBusBusNumber)),
3352 INDEX_OF (&(CardBus->SubordinateBusNumber))
3353 );
3354
3355 Print (L" ------------------------------------------------------\n");
3356
3357 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);
3358 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);
3359 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);
3360
3361 //
3362 // Print CardBus Latency Timer
3363 //
3364 ShellPrintHiiEx(-1, -1, NULL,
3365 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY),
3366 gShellDebug1HiiHandle,
3367 INDEX_OF (&(CardBus->CardBusLatencyTimer)),
3368 CardBus->CardBusLatencyTimer
3369 );
3370
3371 //
3372 // Print Memory/Io ranges this cardbus bridge forwards
3373 //
3374 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);
3375 Print (L"----------------------------------------------------------------------\n");
3376
3377 ShellPrintHiiEx(-1, -1, NULL,
3378 STRING_TOKEN (STR_PCI2_MEM_3),
3379 gShellDebug1HiiHandle,
3380 INDEX_OF (&(CardBus->MemoryBase0)),
3381 CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",
3382 CardBus->MemoryBase0 & 0xfffff000,
3383 CardBus->MemoryLimit0 | 0x00000fff
3384 );
3385
3386 ShellPrintHiiEx(-1, -1, NULL,
3387 STRING_TOKEN (STR_PCI2_MEM_3),
3388 gShellDebug1HiiHandle,
3389 INDEX_OF (&(CardBus->MemoryBase1)),
3390 CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",
3391 CardBus->MemoryBase1 & 0xfffff000,
3392 CardBus->MemoryLimit1 | 0x00000fff
3393 );
3394
3395 Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);
3396 ShellPrintHiiEx(-1, -1, NULL,
3397 STRING_TOKEN (STR_PCI2_IO_2),
3398 gShellDebug1HiiHandle,
3399 INDEX_OF (&(CardBus->IoBase0)),
3400 Io32Bit ? L" 32 bit" : L" 16 bit",
3401 CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
3402 (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003
3403 );
3404
3405 Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);
3406 ShellPrintHiiEx(-1, -1, NULL,
3407 STRING_TOKEN (STR_PCI2_IO_2),
3408 gShellDebug1HiiHandle,
3409 INDEX_OF (&(CardBus->IoBase1)),
3410 Io32Bit ? L" 32 bit" : L" 16 bit",
3411 CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
3412 (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003
3413 );
3414
3415 //
3416 // Print register Interrupt Line & PIN
3417 //
3418 ShellPrintHiiEx(-1, -1, NULL,
3419 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3),
3420 gShellDebug1HiiHandle,
3421 INDEX_OF (&(CardBus->InterruptLine)),
3422 CardBus->InterruptLine,
3423 INDEX_OF (&(CardBus->InterruptPin)),
3424 CardBus->InterruptPin
3425 );
3426
3427 //
3428 // Print register Bridge Control
3429 //
3430 PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);
3431
3432 //
3433 // Print some registers in data region of PCI configuration space for cardbus
3434 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3435 // Address.
3436 //
3437 CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));
3438
3439 ShellPrintHiiEx(-1, -1, NULL,
3440 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2),
3441 gShellDebug1HiiHandle,
3442 INDEX_OF (&(CardBusData->SubVendorId)),
3443 CardBusData->SubVendorId,
3444 INDEX_OF (&(CardBusData->SubSystemId)),
3445 CardBusData->SubSystemId
3446 );
3447
3448 ShellPrintHiiEx(-1, -1, NULL,
3449 STRING_TOKEN (STR_PCI2_OPTIONAL),
3450 gShellDebug1HiiHandle,
3451 INDEX_OF (&(CardBusData->LegacyBase)),
3452 CardBusData->LegacyBase
3453 );
3454
3455 return EFI_SUCCESS;
3456 }
3457
3458 /**
3459 Explain each meaningful bit of register Status. The definition of Status is
3460 slightly different depending on the PCI header type.
3461
3462 @param[in] Status Points to the content of register Status.
3463 @param[in] MainStatus Indicates if this register is main status(not secondary
3464 status).
3465 @param[in] HeaderType Header type of this PCI device.
3466
3467 @retval EFI_SUCCESS The command completed successfully.
3468 **/
3469 EFI_STATUS
3470 PciExplainStatus (
3471 IN UINT16 *Status,
3472 IN BOOLEAN MainStatus,
3473 IN PCI_HEADER_TYPE HeaderType
3474 )
3475 {
3476 if (MainStatus) {
3477 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
3478
3479 } else {
3480 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
3481 }
3482
3483 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);
3484
3485 //
3486 // Bit 5 is meaningless for CardBus Bridge
3487 //
3488 if (HeaderType == PciCardBusBridge) {
3489 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
3490
3491 } else {
3492 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
3493 }
3494
3495 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);
3496
3497 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);
3498 //
3499 // Bit 9 and bit 10 together decides the DEVSEL timing
3500 //
3501 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);
3502 if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {
3503 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);
3504
3505 } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {
3506 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);
3507
3508 } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {
3509 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);
3510
3511 } else {
3512 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);
3513 }
3514
3515 ShellPrintHiiEx(-1, -1, NULL,
3516 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET),
3517 gShellDebug1HiiHandle,
3518 (*Status & PCI_BIT_11) != 0
3519 );
3520
3521 ShellPrintHiiEx(-1, -1, NULL,
3522 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET),
3523 gShellDebug1HiiHandle,
3524 (*Status & PCI_BIT_12) != 0
3525 );
3526
3527 ShellPrintHiiEx(-1, -1, NULL,
3528 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER),
3529 gShellDebug1HiiHandle,
3530 (*Status & PCI_BIT_13) != 0
3531 );
3532
3533 if (MainStatus) {
3534 ShellPrintHiiEx(-1, -1, NULL,
3535 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR),
3536 gShellDebug1HiiHandle,
3537 (*Status & PCI_BIT_14) != 0
3538 );
3539
3540 } else {
3541 ShellPrintHiiEx(-1, -1, NULL,
3542 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR),
3543 gShellDebug1HiiHandle,
3544 (*Status & PCI_BIT_14) != 0
3545 );
3546 }
3547
3548 ShellPrintHiiEx(-1, -1, NULL,
3549 STRING_TOKEN (STR_PCI2_DETECTED_ERROR),
3550 gShellDebug1HiiHandle,
3551 (*Status & PCI_BIT_15) != 0
3552 );
3553
3554 return EFI_SUCCESS;
3555 }
3556
3557 /**
3558 Explain each meaningful bit of register Command.
3559
3560 @param[in] Command Points to the content of register Command.
3561
3562 @retval EFI_SUCCESS The command completed successfully.
3563 **/
3564 EFI_STATUS
3565 PciExplainCommand (
3566 IN UINT16 *Command
3567 )
3568 {
3569 //
3570 // Print the binary value of register Command
3571 //
3572 ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);
3573
3574 //
3575 // Explain register Command bit by bit
3576 //
3577 ShellPrintHiiEx(-1, -1, NULL,
3578 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED),
3579 gShellDebug1HiiHandle,
3580 (*Command & PCI_BIT_0) != 0
3581 );
3582
3583 ShellPrintHiiEx(-1, -1, NULL,
3584 STRING_TOKEN (STR_PCI2_MEMORY_SPACE),
3585 gShellDebug1HiiHandle,
3586 (*Command & PCI_BIT_1) != 0
3587 );
3588
3589 ShellPrintHiiEx(-1, -1, NULL,
3590 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER),
3591 gShellDebug1HiiHandle,
3592 (*Command & PCI_BIT_2) != 0
3593 );
3594
3595 ShellPrintHiiEx(-1, -1, NULL,
3596 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE),
3597 gShellDebug1HiiHandle,
3598 (*Command & PCI_BIT_3) != 0
3599 );
3600
3601 ShellPrintHiiEx(-1, -1, NULL,
3602 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE),
3603 gShellDebug1HiiHandle,
3604 (*Command & PCI_BIT_4) != 0
3605 );
3606
3607 ShellPrintHiiEx(-1, -1, NULL,
3608 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING),
3609 gShellDebug1HiiHandle,
3610 (*Command & PCI_BIT_5) != 0
3611 );
3612
3613 ShellPrintHiiEx(-1, -1, NULL,
3614 STRING_TOKEN (STR_PCI2_ASSERT_PERR),
3615 gShellDebug1HiiHandle,
3616 (*Command & PCI_BIT_6) != 0
3617 );
3618
3619 ShellPrintHiiEx(-1, -1, NULL,
3620 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING),
3621 gShellDebug1HiiHandle,
3622 (*Command & PCI_BIT_7) != 0
3623 );
3624
3625 ShellPrintHiiEx(-1, -1, NULL,
3626 STRING_TOKEN (STR_PCI2_SERR_DRIVER),
3627 gShellDebug1HiiHandle,
3628 (*Command & PCI_BIT_8) != 0
3629 );
3630
3631 ShellPrintHiiEx(-1, -1, NULL,
3632 STRING_TOKEN (STR_PCI2_FAST_BACK_2),
3633 gShellDebug1HiiHandle,
3634 (*Command & PCI_BIT_9) != 0
3635 );
3636
3637 return EFI_SUCCESS;
3638 }
3639
3640 /**
3641 Explain each meaningful bit of register Bridge Control.
3642
3643 @param[in] BridgeControl Points to the content of register Bridge Control.
3644 @param[in] HeaderType The headertype.
3645
3646 @retval EFI_SUCCESS The command completed successfully.
3647 **/
3648 EFI_STATUS
3649 PciExplainBridgeControl (
3650 IN UINT16 *BridgeControl,
3651 IN PCI_HEADER_TYPE HeaderType
3652 )
3653 {
3654 ShellPrintHiiEx(-1, -1, NULL,
3655 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL),
3656 gShellDebug1HiiHandle,
3657 INDEX_OF (BridgeControl),
3658 *BridgeControl
3659 );
3660
3661 ShellPrintHiiEx(-1, -1, NULL,
3662 STRING_TOKEN (STR_PCI2_PARITY_ERROR),
3663 gShellDebug1HiiHandle,
3664 (*BridgeControl & PCI_BIT_0) != 0
3665 );
3666 ShellPrintHiiEx(-1, -1, NULL,
3667 STRING_TOKEN (STR_PCI2_SERR_ENABLE),
3668 gShellDebug1HiiHandle,
3669 (*BridgeControl & PCI_BIT_1) != 0
3670 );
3671 ShellPrintHiiEx(-1, -1, NULL,
3672 STRING_TOKEN (STR_PCI2_ISA_ENABLE),
3673 gShellDebug1HiiHandle,
3674 (*BridgeControl & PCI_BIT_2) != 0
3675 );
3676 ShellPrintHiiEx(-1, -1, NULL,
3677 STRING_TOKEN (STR_PCI2_VGA_ENABLE),
3678 gShellDebug1HiiHandle,
3679 (*BridgeControl & PCI_BIT_3) != 0
3680 );
3681 ShellPrintHiiEx(-1, -1, NULL,
3682 STRING_TOKEN (STR_PCI2_MASTER_ABORT),
3683 gShellDebug1HiiHandle,
3684 (*BridgeControl & PCI_BIT_5) != 0
3685 );
3686
3687 //
3688 // Register Bridge Control has some slight differences between P2P bridge
3689 // and Cardbus bridge from bit 6 to bit 11.
3690 //
3691 if (HeaderType == PciP2pBridge) {
3692 ShellPrintHiiEx(-1, -1, NULL,
3693 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET),
3694 gShellDebug1HiiHandle,
3695 (*BridgeControl & PCI_BIT_6) != 0
3696 );
3697 ShellPrintHiiEx(-1, -1, NULL,
3698 STRING_TOKEN (STR_PCI2_FAST_ENABLE),
3699 gShellDebug1HiiHandle,
3700 (*BridgeControl & PCI_BIT_7) != 0
3701 );
3702 ShellPrintHiiEx(-1, -1, NULL,
3703 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER),
3704 gShellDebug1HiiHandle,
3705 (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"
3706 );
3707 ShellPrintHiiEx(-1, -1, NULL,
3708 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER),
3709 gShellDebug1HiiHandle,
3710 (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"
3711 );
3712 ShellPrintHiiEx(-1, -1, NULL,
3713 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS),
3714 gShellDebug1HiiHandle,
3715 (*BridgeControl & PCI_BIT_10) != 0
3716 );
3717 ShellPrintHiiEx(-1, -1, NULL,
3718 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR),
3719 gShellDebug1HiiHandle,
3720 (*BridgeControl & PCI_BIT_11) != 0
3721 );
3722
3723 } else {
3724 ShellPrintHiiEx(-1, -1, NULL,
3725 STRING_TOKEN (STR_PCI2_CARDBUS_RESET),
3726 gShellDebug1HiiHandle,
3727 (*BridgeControl & PCI_BIT_6) != 0
3728 );
3729 ShellPrintHiiEx(-1, -1, NULL,
3730 STRING_TOKEN (STR_PCI2_IREQ_ENABLE),
3731 gShellDebug1HiiHandle,
3732 (*BridgeControl & PCI_BIT_7) != 0
3733 );
3734 ShellPrintHiiEx(-1, -1, NULL,
3735 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE),
3736 gShellDebug1HiiHandle,
3737 (*BridgeControl & PCI_BIT_10) != 0
3738 );
3739 }
3740
3741 return EFI_SUCCESS;
3742 }
3743
3744 /**
3745 Print each capability structure.
3746
3747 @param[in] IoDev The pointer to the deivce.
3748 @param[in] Address The address to start at.
3749 @param[in] CapPtr The offset from the address.
3750
3751 @retval EFI_SUCCESS The operation was successful.
3752 **/
3753 EFI_STATUS
3754 PciExplainCapabilityStruct (
3755 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
3756 IN UINT64 Address,
3757 IN UINT8 CapPtr
3758 )
3759 {
3760 UINT8 CapabilityPtr;
3761 UINT16 CapabilityEntry;
3762 UINT8 CapabilityID;
3763 UINT64 RegAddress;
3764
3765 CapabilityPtr = CapPtr;
3766
3767 //
3768 // Go through the Capability list
3769 //
3770 while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
3771 RegAddress = Address + CapabilityPtr;
3772 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);
3773
3774 CapabilityID = (UINT8) CapabilityEntry;
3775
3776 //
3777 // Explain PciExpress data
3778 //
3779 if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {
3780 PciExplainPciExpress (IoDev, Address, CapabilityPtr);
3781 return EFI_SUCCESS;
3782 }
3783 //
3784 // Explain other capabilities here
3785 //
3786 CapabilityPtr = (UINT8) (CapabilityEntry >> 8);
3787 }
3788
3789 return EFI_SUCCESS;
3790 }
3791
3792 /**
3793 Print out information of the capability information.
3794
3795 @param[in] PciExpressCap The pointer to the structure about the device.
3796
3797 @retval EFI_SUCCESS The operation was successful.
3798 **/
3799 EFI_STATUS
3800 ExplainPcieCapReg (
3801 IN PCIE_CAP_STURCTURE *PciExpressCap
3802 )
3803 {
3804 UINT16 PcieCapReg;
3805 CHAR16 *DevicePortType;
3806
3807 PcieCapReg = PciExpressCap->PcieCapReg;
3808 Print (
3809 L" Capability Version(3:0): %E0x%04x%N\n",
3810 PCIE_CAP_VERSION (PcieCapReg)
3811 );
3812 if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {
3813 DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];
3814 } else {
3815 DevicePortType = L"Unknown Type";
3816 }
3817 Print (
3818 L" Device/PortType(7:4): %E%s%N\n",
3819 DevicePortType
3820 );
3821 //
3822 // 'Slot Implemented' is only valid for:
3823 // a) Root Port of PCI Express Root Complex, or
3824 // b) Downstream Port of PCI Express Switch
3825 //
3826 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||
3827 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {
3828 Print (
3829 L" Slot Implemented(8): %E%d%N\n",
3830 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg)
3831 );
3832 }
3833 Print (
3834 L" Interrupt Message Number(13:9): %E0x%05x%N\n",
3835 PCIE_CAP_INT_MSG_NUM (PcieCapReg)
3836 );
3837 return EFI_SUCCESS;
3838 }
3839
3840 /**
3841 Print out information of the device capability information.
3842
3843 @param[in] PciExpressCap The pointer to the structure about the device.
3844
3845 @retval EFI_SUCCESS The operation was successful.
3846 **/
3847 EFI_STATUS
3848 ExplainPcieDeviceCap (
3849 IN PCIE_CAP_STURCTURE *PciExpressCap
3850 )
3851 {
3852 UINT16 PcieCapReg;
3853 UINT32 PcieDeviceCap;
3854 UINT8 DevicePortType;
3855 UINT8 L0sLatency;
3856 UINT8 L1Latency;
3857
3858 PcieCapReg = PciExpressCap->PcieCapReg;
3859 PcieDeviceCap = PciExpressCap->PcieDeviceCap;
3860 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);
3861 Print (L" Max_Payload_Size Supported(2:0): ");
3862 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) < 6) {
3863 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));
3864 } else {
3865 Print (L"%EUnknown%N\n");
3866 }
3867 Print (
3868 L" Phantom Functions Supported(4:3): %E%d%N\n",
3869 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap)
3870 );
3871 Print (
3872 L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",
3873 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap) ? 8 : 5
3874 );
3875 //
3876 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3877 //
3878 if (IS_PCIE_ENDPOINT (DevicePortType)) {
3879 L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);
3880 L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);
3881 Print (L" Endpoint L0s Acceptable Latency(8:6): ");
3882 if (L0sLatency < 4) {
3883 Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));
3884 } else {
3885 if (L0sLatency < 7) {
3886 Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));
3887 } else {
3888 Print (L"%ENo limit%N\n");
3889 }
3890 }
3891 Print (L" Endpoint L1 Acceptable Latency(11:9): ");
3892 if (L1Latency < 7) {
3893 Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));
3894 } else {
3895 Print (L"%ENo limit%N\n");
3896 }
3897 }
3898 Print (
3899 L" Role-based Error Reporting(15): %E%d%N\n",
3900 PCIE_CAP_ERR_REPORTING (PcieDeviceCap)
3901 );
3902 //
3903 // Only valid for Upstream Port:
3904 // a) Captured Slot Power Limit Value
3905 // b) Captured Slot Power Scale
3906 //
3907 if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {
3908 Print (
3909 L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",
3910 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap)
3911 );
3912 Print (
3913 L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",
3914 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]
3915 );
3916 }
3917 //
3918 // Function Level Reset Capability is only valid for Endpoint
3919 //
3920 if (IS_PCIE_ENDPOINT (DevicePortType)) {
3921 Print (
3922 L" Function Level Reset Capability(28): %E%d%N\n",
3923 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap)
3924 );
3925 }
3926 return EFI_SUCCESS;
3927 }
3928
3929 /**
3930 Print out information of the device control information.
3931
3932 @param[in] PciExpressCap The pointer to the structure about the device.
3933
3934 @retval EFI_SUCCESS The operation was successful.
3935 **/
3936 EFI_STATUS
3937 ExplainPcieDeviceControl (
3938 IN PCIE_CAP_STURCTURE *PciExpressCap
3939 )
3940 {
3941 UINT16 PcieCapReg;
3942 UINT16 PcieDeviceControl;
3943
3944 PcieCapReg = PciExpressCap->PcieCapReg;
3945 PcieDeviceControl = PciExpressCap->DeviceControl;
3946 Print (
3947 L" Correctable Error Reporting Enable(0): %E%d%N\n",
3948 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)
3949 );
3950 Print (
3951 L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",
3952 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)
3953 );
3954 Print (
3955 L" Fatal Error Reporting Enable(2): %E%d%N\n",
3956 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)
3957 );
3958 Print (
3959 L" Unsupported Request Reporting Enable(3): %E%d%N\n",
3960 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)
3961 );
3962 Print (
3963 L" Enable Relaxed Ordering(4): %E%d%N\n",
3964 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)
3965 );
3966 Print (L" Max_Payload_Size(7:5): ");
3967 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {
3968 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));
3969 } else {
3970 Print (L"%EUnknown%N\n");
3971 }
3972 Print (
3973 L" Extended Tag Field Enable(8): %E%d%N\n",
3974 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl)
3975 );
3976 Print (
3977 L" Phantom Functions Enable(9): %E%d%N\n",
3978 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl)
3979 );
3980 Print (
3981 L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",
3982 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl)
3983 );
3984 Print (
3985 L" Enable No Snoop(11): %E%d%N\n",
3986 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl)
3987 );
3988 Print (L" Max_Read_Request_Size(14:12): ");
3989 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {
3990 Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));
3991 } else {
3992 Print (L"%EUnknown%N\n");
3993 }
3994 //
3995 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
3996 //
3997 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {
3998 Print (
3999 L" Bridge Configuration Retry Enable(15): %E%d%N\n",
4000 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl)
4001 );
4002 }
4003 return EFI_SUCCESS;
4004 }
4005
4006 /**
4007 Print out information of the device status information.
4008
4009 @param[in] PciExpressCap The pointer to the structure about the device.
4010
4011 @retval EFI_SUCCESS The operation was successful.
4012 **/
4013 EFI_STATUS
4014 ExplainPcieDeviceStatus (
4015 IN PCIE_CAP_STURCTURE *PciExpressCap
4016 )
4017 {
4018 UINT16 PcieDeviceStatus;
4019
4020 PcieDeviceStatus = PciExpressCap->DeviceStatus;
4021 Print (
4022 L" Correctable Error Detected(0): %E%d%N\n",
4023 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus)
4024 );
4025 Print (
4026 L" Non-Fatal Error Detected(1): %E%d%N\n",
4027 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus)
4028 );
4029 Print (
4030 L" Fatal Error Detected(2): %E%d%N\n",
4031 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus)
4032 );
4033 Print (
4034 L" Unsupported Request Detected(3): %E%d%N\n",
4035 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus)
4036 );
4037 Print (
4038 L" AUX Power Detected(4): %E%d%N\n",
4039 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus)
4040 );
4041 Print (
4042 L" Transactions Pending(5): %E%d%N\n",
4043 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus)
4044 );
4045 return EFI_SUCCESS;
4046 }
4047
4048 /**
4049 Print out information of the device link information.
4050
4051 @param[in] PciExpressCap The pointer to the structure about the device.
4052
4053 @retval EFI_SUCCESS The operation was successful.
4054 **/
4055 EFI_STATUS
4056 ExplainPcieLinkCap (
4057 IN PCIE_CAP_STURCTURE *PciExpressCap
4058 )
4059 {
4060 UINT32 PcieLinkCap;
4061 CHAR16 *SupLinkSpeeds;
4062 CHAR16 *AspmValue;
4063
4064 PcieLinkCap = PciExpressCap->LinkCap;
4065 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {
4066 case 1:
4067 SupLinkSpeeds = L"2.5 GT/s";
4068 break;
4069 case 2:
4070 SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";
4071 break;
4072 default:
4073 SupLinkSpeeds = L"Unknown";
4074 break;
4075 }
4076 Print (
4077 L" Supported Link Speeds(3:0): %E%s supported%N\n",
4078 SupLinkSpeeds
4079 );
4080 Print (
4081 L" Maximum Link Width(9:4): %Ex%d%N\n",
4082 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)
4083 );
4084 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {
4085 case 1:
4086 AspmValue = L"L0s Entry";
4087 break;
4088 case 3:
4089 AspmValue = L"L0s and L1";
4090 break;
4091 default:
4092 AspmValue = L"Reserved";
4093 break;
4094 }
4095 Print (
4096 L" Active State Power Management Support(11:10): %E%s Supported%N\n",
4097 AspmValue
4098 );
4099 Print (
4100 L" L0s Exit Latency(14:12): %E%s%N\n",
4101 L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]
4102 );
4103 Print (
4104 L" L1 Exit Latency(17:15): %E%s%N\n",
4105 L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]
4106 );
4107 Print (
4108 L" Clock Power Management(18): %E%d%N\n",
4109 PCIE_CAP_CLOCK_PM (PcieLinkCap)
4110 );
4111 Print (
4112 L" Surprise Down Error Reporting Capable(19): %E%d%N\n",
4113 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap)
4114 );
4115 Print (
4116 L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",
4117 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap)
4118 );
4119 Print (
4120 L" Link Bandwidth Notification Capability(21): %E%d%N\n",
4121 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap)
4122 );
4123 Print (
4124 L" Port Number(31:24): %E0x%02x%N\n",
4125 PCIE_CAP_PORT_NUMBER (PcieLinkCap)
4126 );
4127 return EFI_SUCCESS;
4128 }
4129
4130 /**
4131 Print out information of the device link control information.
4132
4133 @param[in] PciExpressCap The pointer to the structure about the device.
4134
4135 @retval EFI_SUCCESS The operation was successful.
4136 **/
4137 EFI_STATUS
4138 ExplainPcieLinkControl (
4139 IN PCIE_CAP_STURCTURE *PciExpressCap
4140 )
4141 {
4142 UINT16 PcieLinkControl;
4143 UINT8 DevicePortType;
4144
4145 PcieLinkControl = PciExpressCap->LinkControl;
4146 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);
4147 Print (
4148 L" Active State Power Management Control(1:0): %E%s%N\n",
4149 ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]
4150 );
4151 //
4152 // RCB is not applicable to switches
4153 //
4154 if (!IS_PCIE_SWITCH(DevicePortType)) {
4155 Print (
4156 L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",
4157 1 << (PCIE_CAP_RCB (PcieLinkControl) + 6)
4158 );
4159 }
4160 //
4161 // Link Disable is reserved on
4162 // a) Endpoints
4163 // b) PCI Express to PCI/PCI-X bridges
4164 // c) Upstream Ports of Switches
4165 //
4166 if (!IS_PCIE_ENDPOINT (DevicePortType) &&
4167 DevicePortType != PCIE_SWITCH_UPSTREAM_PORT &&
4168 DevicePortType != PCIE_PCIE_TO_PCIX_BRIDGE) {
4169 Print (
4170 L" Link Disable(4): %E%d%N\n",
4171 PCIE_CAP_LINK_DISABLE (PcieLinkControl)
4172 );
4173 }
4174 Print (
4175 L" Common Clock Configuration(6): %E%d%N\n",
4176 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl)
4177 );
4178 Print (
4179 L" Extended Synch(7): %E%d%N\n",
4180 PCIE_CAP_EXT_SYNC (PcieLinkControl)
4181 );
4182 Print (
4183 L" Enable Clock Power Management(8): %E%d%N\n",
4184 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl)
4185 );
4186 Print (
4187 L" Hardware Autonomous Width Disable(9): %E%d%N\n",
4188 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl)
4189 );
4190 Print (
4191 L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",
4192 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl)
4193 );
4194 Print (
4195 L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",
4196 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl)
4197 );
4198 return EFI_SUCCESS;
4199 }
4200
4201 /**
4202 Print out information of the device link status information.
4203
4204 @param[in] PciExpressCap The pointer to the structure about the device.
4205
4206 @retval EFI_SUCCESS The operation was successful.
4207 **/
4208 EFI_STATUS
4209 ExplainPcieLinkStatus (
4210 IN PCIE_CAP_STURCTURE *PciExpressCap
4211 )
4212 {
4213 UINT16 PcieLinkStatus;
4214 CHAR16 *SupLinkSpeeds;
4215
4216 PcieLinkStatus = PciExpressCap->LinkStatus;
4217 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {
4218 case 1:
4219 SupLinkSpeeds = L"2.5 GT/s";
4220 break;
4221 case 2:
4222 SupLinkSpeeds = L"5.0 GT/s";
4223 break;
4224 default:
4225 SupLinkSpeeds = L"Reserved";
4226 break;
4227 }
4228 Print (
4229 L" Current Link Speed(3:0): %E%s%N\n",
4230 SupLinkSpeeds
4231 );
4232 Print (
4233 L" Negotiated Link Width(9:4): %Ex%d%N\n",
4234 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus)
4235 );
4236 Print (
4237 L" Link Training(11): %E%d%N\n",
4238 PCIE_CAP_LINK_TRAINING (PcieLinkStatus)
4239 );
4240 Print (
4241 L" Slot Clock Configuration(12): %E%d%N\n",
4242 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus)
4243 );
4244 Print (
4245 L" Data Link Layer Link Active(13): %E%d%N\n",
4246 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus)
4247 );
4248 Print (
4249 L" Link Bandwidth Management Status(14): %E%d%N\n",
4250 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus)
4251 );
4252 Print (
4253 L" Link Autonomous Bandwidth Status(15): %E%d%N\n",
4254 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus)
4255 );
4256 return EFI_SUCCESS;
4257 }
4258
4259 /**
4260 Print out information of the device slot information.
4261
4262 @param[in] PciExpressCap The pointer to the structure about the device.
4263
4264 @retval EFI_SUCCESS The operation was successful.
4265 **/
4266 EFI_STATUS
4267 ExplainPcieSlotCap (
4268 IN PCIE_CAP_STURCTURE *PciExpressCap
4269 )
4270 {
4271 UINT32 PcieSlotCap;
4272
4273 PcieSlotCap = PciExpressCap->SlotCap;
4274
4275 Print (
4276 L" Attention Button Present(0): %E%d%N\n",
4277 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap)
4278 );
4279 Print (
4280 L" Power Controller Present(1): %E%d%N\n",
4281 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap)
4282 );
4283 Print (
4284 L" MRL Sensor Present(2): %E%d%N\n",
4285 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap)
4286 );
4287 Print (
4288 L" Attention Indicator Present(3): %E%d%N\n",
4289 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap)
4290 );
4291 Print (
4292 L" Power Indicator Present(4): %E%d%N\n",
4293 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap)
4294 );
4295 Print (
4296 L" Hot-Plug Surprise(5): %E%d%N\n",
4297 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap)
4298 );
4299 Print (
4300 L" Hot-Plug Capable(6): %E%d%N\n",
4301 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap)
4302 );
4303 Print (
4304 L" Slot Power Limit Value(14:7): %E0x%02x%N\n",
4305 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap)
4306 );
4307 Print (
4308 L" Slot Power Limit Scale(16:15): %E%s%N\n",
4309 SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]
4310 );
4311 Print (
4312 L" Electromechanical Interlock Present(17): %E%d%N\n",
4313 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap)
4314 );
4315 Print (
4316 L" No Command Completed Support(18): %E%d%N\n",
4317 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap)
4318 );
4319 Print (
4320 L" Physical Slot Number(31:19): %E%d%N\n",
4321 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap)
4322 );
4323
4324 return EFI_SUCCESS;
4325 }
4326
4327 /**
4328 Print out information of the device slot control information.
4329
4330 @param[in] PciExpressCap The pointer to the structure about the device.
4331
4332 @retval EFI_SUCCESS The operation was successful.
4333 **/
4334 EFI_STATUS
4335 ExplainPcieSlotControl (
4336 IN PCIE_CAP_STURCTURE *PciExpressCap
4337 )
4338 {
4339 UINT16 PcieSlotControl;
4340
4341 PcieSlotControl = PciExpressCap->SlotControl;
4342 Print (
4343 L" Attention Button Pressed Enable(0): %E%d%N\n",
4344 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl)
4345 );
4346 Print (
4347 L" Power Fault Detected Enable(1): %E%d%N\n",
4348 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl)
4349 );
4350 Print (
4351 L" MRL Sensor Changed Enable(2): %E%d%N\n",
4352 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)
4353 );
4354 Print (
4355 L" Presence Detect Changed Enable(3): %E%d%N\n",
4356 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)
4357 );
4358 Print (
4359 L" Command Completed Interrupt Enable(4): %E%d%N\n",
4360 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl)
4361 );
4362 Print (
4363 L" Hot-Plug Interrupt Enable(5): %E%d%N\n",
4364 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl)
4365 );
4366 Print (
4367 L" Attention Indicator Control(7:6): %E%s%N\n",
4368 IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]
4369 );
4370 Print (
4371 L" Power Indicator Control(9:8): %E%s%N\n",
4372 IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]
4373 );
4374 Print (L" Power Controller Control(10): %EPower ");
4375 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {
4376 Print (L"Off%N\n");
4377 } else {
4378 Print (L"On%N\n");
4379 }
4380 Print (
4381 L" Electromechanical Interlock Control(11): %E%d%N\n",
4382 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl)
4383 );
4384 Print (
4385 L" Data Link Layer State Changed Enable(12): %E%d%N\n",
4386 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)
4387 );
4388 return EFI_SUCCESS;
4389 }
4390
4391 /**
4392 Print out information of the device slot status information.
4393
4394 @param[in] PciExpressCap The pointer to the structure about the device.
4395
4396 @retval EFI_SUCCESS The operation was successful.
4397 **/
4398 EFI_STATUS
4399 ExplainPcieSlotStatus (
4400 IN PCIE_CAP_STURCTURE *PciExpressCap
4401 )
4402 {
4403 UINT16 PcieSlotStatus;
4404
4405 PcieSlotStatus = PciExpressCap->SlotStatus;
4406
4407 Print (
4408 L" Attention Button Pressed(0): %E%d%N\n",
4409 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus)
4410 );
4411 Print (
4412 L" Power Fault Detected(1): %E%d%N\n",
4413 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus)
4414 );
4415 Print (
4416 L" MRL Sensor Changed(2): %E%d%N\n",
4417 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus)
4418 );
4419 Print (
4420 L" Presence Detect Changed(3): %E%d%N\n",
4421 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus)
4422 );
4423 Print (
4424 L" Command Completed(4): %E%d%N\n",
4425 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus)
4426 );
4427 Print (L" MRL Sensor State(5): %EMRL ");
4428 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {
4429 Print (L" Opened%N\n");
4430 } else {
4431 Print (L" Closed%N\n");
4432 }
4433 Print (L" Presence Detect State(6): ");
4434 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {
4435 Print (L"%ECard Present in slot%N\n");
4436 } else {
4437 Print (L"%ESlot Empty%N\n");
4438 }
4439 Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4440 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {
4441 Print (L"Engaged%N\n");
4442 } else {
4443 Print (L"Disengaged%N\n");
4444 }
4445 Print (
4446 L" Data Link Layer State Changed(8): %E%d%N\n",
4447 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus)
4448 );
4449 return EFI_SUCCESS;
4450 }
4451
4452 /**
4453 Print out information of the device root information.
4454
4455 @param[in] PciExpressCap The pointer to the structure about the device.
4456
4457 @retval EFI_SUCCESS The operation was successful.
4458 **/
4459 EFI_STATUS
4460 ExplainPcieRootControl (
4461 IN PCIE_CAP_STURCTURE *PciExpressCap
4462 )
4463 {
4464 UINT16 PcieRootControl;
4465
4466 PcieRootControl = PciExpressCap->RootControl;
4467
4468 Print (
4469 L" System Error on Correctable Error Enable(0): %E%d%N\n",
4470 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl)
4471 );
4472 Print (
4473 L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",
4474 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl)
4475 );
4476 Print (
4477 L" System Error on Fatal Error Enable(2): %E%d%N\n",
4478 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl)
4479 );
4480 Print (
4481 L" PME Interrupt Enable(3): %E%d%N\n",
4482 PCIE_CAP_PME_INT_ENABLE (PcieRootControl)
4483 );
4484 Print (
4485 L" CRS Software Visibility Enable(4): %E%d%N\n",
4486 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl)
4487 );
4488
4489 return EFI_SUCCESS;
4490 }
4491
4492 /**
4493 Print out information of the device root capability information.
4494
4495 @param[in] PciExpressCap The pointer to the structure about the device.
4496
4497 @retval EFI_SUCCESS The operation was successful.
4498 **/
4499 EFI_STATUS
4500 ExplainPcieRootCap (
4501 IN PCIE_CAP_STURCTURE *PciExpressCap
4502 )
4503 {
4504 UINT16 PcieRootCap;
4505
4506 PcieRootCap = PciExpressCap->RsvdP;
4507
4508 Print (
4509 L" CRS Software Visibility(0): %E%d%N\n",
4510 PCIE_CAP_CRS_SW_VIS (PcieRootCap)
4511 );
4512
4513 return EFI_SUCCESS;
4514 }
4515
4516 /**
4517 Print out information of the device root status information.
4518
4519 @param[in] PciExpressCap The pointer to the structure about the device.
4520
4521 @retval EFI_SUCCESS The operation was successful.
4522 **/
4523 EFI_STATUS
4524 ExplainPcieRootStatus (
4525 IN PCIE_CAP_STURCTURE *PciExpressCap
4526 )
4527 {
4528 UINT32 PcieRootStatus;
4529
4530 PcieRootStatus = PciExpressCap->RootStatus;
4531
4532 Print (
4533 L" PME Requester ID(15:0): %E0x%04x%N\n",
4534 PCIE_CAP_PME_REQ_ID (PcieRootStatus)
4535 );
4536 Print (
4537 L" PME Status(16): %E%d%N\n",
4538 PCIE_CAP_PME_STATUS (PcieRootStatus)
4539 );
4540 Print (
4541 L" PME Pending(17): %E%d%N\n",
4542 PCIE_CAP_PME_PENDING (PcieRootStatus)
4543 );
4544 return EFI_SUCCESS;
4545 }
4546
4547 /**
4548 Display Pcie device structure.
4549
4550 @param[in] IoDev The pointer to the root pci protocol.
4551 @param[in] Address The Address to start at.
4552 @param[in] CapabilityPtr The offset from the address to start.
4553 **/
4554 EFI_STATUS
4555 PciExplainPciExpress (
4556 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
4557 IN UINT64 Address,
4558 IN UINT8 CapabilityPtr
4559 )
4560 {
4561
4562 PCIE_CAP_STURCTURE PciExpressCap;
4563 EFI_STATUS Status;
4564 UINT64 CapRegAddress;
4565 UINT8 Bus;
4566 UINT8 Dev;
4567 UINT8 Func;
4568 UINT8 *ExRegBuffer;
4569 UINTN ExtendRegSize;
4570 UINT64 Pciex_Address;
4571 UINT8 DevicePortType;
4572 UINTN Index;
4573 UINT8 *RegAddr;
4574 UINTN RegValue;
4575
4576 CapRegAddress = Address + CapabilityPtr;
4577 IoDev->Pci.Read (
4578 IoDev,
4579 EfiPciWidthUint32,
4580 CapRegAddress,
4581 sizeof (PciExpressCap) / sizeof (UINT32),
4582 &PciExpressCap
4583 );
4584
4585 DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);
4586
4587 Print (L"\nPci Express device capability structure:\n");
4588
4589 for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {
4590 if (ShellGetExecutionBreakFlag()) {
4591 goto Done;
4592 }
4593 RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;
4594 switch (PcieExplainList[Index].Width) {
4595 case FieldWidthUINT8:
4596 RegValue = *(UINT8 *) RegAddr;
4597 break;
4598 case FieldWidthUINT16:
4599 RegValue = *(UINT16 *) RegAddr;
4600 break;
4601 case FieldWidthUINT32:
4602 RegValue = *(UINT32 *) RegAddr;
4603 break;
4604 default:
4605 RegValue = 0;
4606 break;
4607 }
4608 ShellPrintHiiEx(-1, -1, NULL,
4609 PcieExplainList[Index].Token,
4610 gShellDebug1HiiHandle,
4611 PcieExplainList[Index].Offset,
4612 RegValue
4613 );
4614 if (PcieExplainList[Index].Func == NULL) {
4615 continue;
4616 }
4617 switch (PcieExplainList[Index].Type) {
4618 case PcieExplainTypeLink:
4619 //
4620 // Link registers should not be used by
4621 // a) Root Complex Integrated Endpoint
4622 // b) Root Complex Event Collector
4623 //
4624 if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||
4625 DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {
4626 continue;
4627 }
4628 break;
4629 case PcieExplainTypeSlot:
4630 //
4631 // Slot registers are only valid for
4632 // a) Root Port of PCI Express Root Complex
4633 // b) Downstream Port of PCI Express Switch
4634 // and when SlotImplemented bit is set in PCIE cap register.
4635 //
4636 if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&
4637 DevicePortType != PCIE_SWITCH_DOWNSTREAM_PORT) ||
4638 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {
4639 continue;
4640 }
4641 break;
4642 case PcieExplainTypeRoot:
4643 //
4644 // Root registers are only valid for
4645 // Root Port of PCI Express Root Complex
4646 //
4647 if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {
4648 continue;
4649 }
4650 break;
4651 default:
4652 break;
4653 }
4654 PcieExplainList[Index].Func (&PciExpressCap);
4655 }
4656
4657 Bus = (UINT8) (RShiftU64 (Address, 24));
4658 Dev = (UINT8) (RShiftU64 (Address, 16));
4659 Func = (UINT8) (RShiftU64 (Address, 8));
4660
4661 Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);
4662
4663 ExtendRegSize = 0x1000 - 0x100;
4664
4665 ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);
4666
4667 //
4668 // PciRootBridgeIo protocol should support pci express extend space IO
4669 // (Begins at offset 0x100)
4670 //
4671 Status = IoDev->Pci.Read (
4672 IoDev,
4673 EfiPciWidthUint32,
4674 Pciex_Address,
4675 (ExtendRegSize) / sizeof (UINT32),
4676 (VOID *) (ExRegBuffer)
4677 );
4678 if (EFI_ERROR (Status)) {
4679 FreePool ((VOID *) ExRegBuffer);
4680 return EFI_UNSUPPORTED;
4681 }
4682 //
4683 // Start outputing PciEx extend space( 0xFF-0xFFF)
4684 //
4685 Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");
4686
4687 if (ExRegBuffer != NULL) {
4688 DumpHex (
4689 2,
4690 0x100,
4691 ExtendRegSize,
4692 (VOID *) (ExRegBuffer)
4693 );
4694
4695 FreePool ((VOID *) ExRegBuffer);
4696 }
4697
4698 Done:
4699 return EFI_SUCCESS;
4700 }
EFI Development Kit II mirror for PVE