2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2021, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "UefiShellDebug1CommandsLib.h"
12 #include <Protocol/PciRootBridgeIo.h>
13 #include <Library/ShellLib.h>
14 #include <IndustryStandard/Pci.h>
15 #include <IndustryStandard/Acpi.h>
19 // Printable strings for Pci class code
22 CHAR16
*BaseClass
; // Pointer to the PCI base class string
23 CHAR16
*SubClass
; // Pointer to the PCI sub class string
24 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
28 // a structure holding a single entry, which also points to its lower level
31 typedef struct PCI_CLASS_ENTRY_TAG
{
32 UINT8 Code
; // Class, subclass or I/F code
33 CHAR16
*DescText
; // Description string
34 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
38 // Declarations of entries which contain printable strings for class codes
39 // in PCI configuration space
41 PCI_CLASS_ENTRY PCIBlankEntry
[];
42 PCI_CLASS_ENTRY PCISubClass_00
[];
43 PCI_CLASS_ENTRY PCISubClass_01
[];
44 PCI_CLASS_ENTRY PCISubClass_02
[];
45 PCI_CLASS_ENTRY PCISubClass_03
[];
46 PCI_CLASS_ENTRY PCISubClass_04
[];
47 PCI_CLASS_ENTRY PCISubClass_05
[];
48 PCI_CLASS_ENTRY PCISubClass_06
[];
49 PCI_CLASS_ENTRY PCISubClass_07
[];
50 PCI_CLASS_ENTRY PCISubClass_08
[];
51 PCI_CLASS_ENTRY PCISubClass_09
[];
52 PCI_CLASS_ENTRY PCISubClass_0a
[];
53 PCI_CLASS_ENTRY PCISubClass_0b
[];
54 PCI_CLASS_ENTRY PCISubClass_0c
[];
55 PCI_CLASS_ENTRY PCISubClass_0d
[];
56 PCI_CLASS_ENTRY PCISubClass_0e
[];
57 PCI_CLASS_ENTRY PCISubClass_0f
[];
58 PCI_CLASS_ENTRY PCISubClass_10
[];
59 PCI_CLASS_ENTRY PCISubClass_11
[];
60 PCI_CLASS_ENTRY PCISubClass_12
[];
61 PCI_CLASS_ENTRY PCISubClass_13
[];
62 PCI_CLASS_ENTRY PCIPIFClass_0100
[];
63 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
64 PCI_CLASS_ENTRY PCIPIFClass_0105
[];
65 PCI_CLASS_ENTRY PCIPIFClass_0106
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0107
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0108
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0109
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0609
[];
72 PCI_CLASS_ENTRY PCIPIFClass_060b
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
80 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
81 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
82 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
83 PCI_CLASS_ENTRY PCIPIFClass_0c07
[];
84 PCI_CLASS_ENTRY PCIPIFClass_0d01
[];
85 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
88 // Base class strings entries
90 PCI_CLASS_ENTRY gClassStringList
[] = {
98 L
"Mass Storage Controller",
103 L
"Network Controller",
108 L
"Display Controller",
113 L
"Multimedia Device",
118 L
"Memory Controller",
128 L
"Simple Communications Controllers",
133 L
"Base System Peripherals",
153 L
"Serial Bus Controllers",
158 L
"Wireless Controllers",
163 L
"Intelligent IO Controllers",
168 L
"Satellite Communications Controllers",
173 L
"Encryption/Decryption Controllers",
178 L
"Data Acquisition & Signal Processing Controllers",
183 L
"Processing Accelerators",
188 L
"Non-Essential Instrumentation",
193 L
"Device does not fit in any defined classes",
199 /* null string ends the list */ NULL
204 // Subclass strings entries
206 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
215 /* null string ends the list */ NULL
219 PCI_CLASS_ENTRY PCISubClass_00
[] = {
222 L
"All devices other than VGA",
227 L
"VGA-compatible devices",
233 /* null string ends the list */ NULL
237 PCI_CLASS_ENTRY PCISubClass_01
[] = {
250 L
"Floppy disk controller",
265 L
"ATA controller with ADMA interface",
270 L
"Serial ATA controller",
275 L
"Serial Attached SCSI (SAS) controller ",
280 L
"Non-volatile memory subsystem",
285 L
"Universal Flash Storage (UFS) controller ",
290 L
"Other mass storage controller",
296 /* null string ends the list */ NULL
300 PCI_CLASS_ENTRY PCISubClass_02
[] = {
303 L
"Ethernet controller",
308 L
"Token ring controller",
328 L
"WorldFip controller",
333 L
"PICMG 2.14 Multi Computing",
338 L
"InfiniBand controller",
343 L
"Other network controller",
349 /* null string ends the list */ NULL
353 PCI_CLASS_ENTRY PCISubClass_03
[] = {
356 L
"VGA/8514 controller",
371 L
"Other display controller",
377 /* null string ends the list */ PCIBlankEntry
381 PCI_CLASS_ENTRY PCISubClass_04
[] = {
394 L
"Computer Telephony device",
399 L
"Mixed mode device",
404 L
"Other multimedia device",
410 /* null string ends the list */ NULL
414 PCI_CLASS_ENTRY PCISubClass_05
[] = {
417 L
"RAM memory controller",
422 L
"Flash memory controller",
427 L
"Other memory controller",
433 /* null string ends the list */ NULL
437 PCI_CLASS_ENTRY PCISubClass_06
[] = {
455 L
"PCI/Micro Channel bridge",
465 L
"PCI/PCMCIA bridge",
485 L
"Semi-transparent PCI-to-PCI bridge",
490 L
"InfiniBand-to-PCI host bridge",
495 L
"Advanced Switching to PCI host bridge",
500 L
"Other bridge type",
506 /* null string ends the list */ NULL
510 PCI_CLASS_ENTRY PCISubClass_07
[] = {
513 L
"Serial controller",
523 L
"Multiport serial controller",
533 L
"GPIB (IEEE 488.1/2) controller",
543 L
"Other communication device",
549 /* null string ends the list */ NULL
553 PCI_CLASS_ENTRY PCISubClass_08
[] = {
576 L
"Generic PCI Hot-Plug controller",
581 L
"SD Host controller",
591 L
"Root Complex Event Collector",
596 L
"Other system peripheral",
602 /* null string ends the list */ NULL
606 PCI_CLASS_ENTRY PCISubClass_09
[] = {
609 L
"Keyboard controller",
624 L
"Scanner controller",
629 L
"Gameport controller",
634 L
"Other input controller",
640 /* null string ends the list */ NULL
644 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
647 L
"Generic docking station",
652 L
"Other type of docking station",
658 /* null string ends the list */ NULL
662 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
706 /* null string ends the list */ NULL
710 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
738 L
"System Management Bus",
753 L
"SERCOS Interface Standard (IEC 61491)",
769 /* null string ends the list */ NULL
773 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
776 L
"iRDA compatible controller",
801 L
"Ethernet (802.11a - 5 GHz)",
806 L
"Ethernet (802.11b - 2.4 GHz)",
811 L
"Other type of wireless controller",
817 /* null string ends the list */ NULL
821 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
830 /* null string ends the list */ NULL
834 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
857 L
"Other satellite communication controller",
863 /* null string ends the list */ NULL
867 PCI_CLASS_ENTRY PCISubClass_10
[] = {
870 L
"Network & computing Encrypt/Decrypt",
875 L
"Entertainment Encrypt/Decrypt",
880 L
"Other Encrypt/Decrypt",
886 /* null string ends the list */ NULL
890 PCI_CLASS_ENTRY PCISubClass_11
[] = {
898 L
"Performance Counters",
903 L
"Communications synchronization plus time and frequency test/measurement ",
913 L
"Other DAQ & SP controllers",
919 /* null string ends the list */ NULL
923 PCI_CLASS_ENTRY PCISubClass_12
[] = {
926 L
"Processing Accelerator",
932 /* null string ends the list */ NULL
936 PCI_CLASS_ENTRY PCISubClass_13
[] = {
939 L
"Non-Essential Instrumentation Function",
945 /* null string ends the list */ NULL
950 // Programming Interface entries
952 PCI_CLASS_ENTRY PCIPIFClass_0100
[] = {
960 L
"SCSI storage device SOP using PQI",
965 L
"SCSI controller SOP using PQI",
970 L
"SCSI storage device and controller SOP using PQI",
975 L
"SCSI storage device SOP using NVMe",
981 /* null string ends the list */ NULL
985 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
1013 L
"OM-primary, OM-secondary",
1018 L
"PI-primary, OM-secondary",
1023 L
"OM/PI-primary, OM-secondary",
1033 L
"OM-primary, PI-secondary",
1038 L
"PI-primary, PI-secondary",
1043 L
"OM/PI-primary, PI-secondary",
1053 L
"OM-primary, OM/PI-secondary",
1058 L
"PI-primary, OM/PI-secondary",
1063 L
"OM/PI-primary, OM/PI-secondary",
1073 L
"Master, OM-primary",
1078 L
"Master, PI-primary",
1083 L
"Master, OM/PI-primary",
1088 L
"Master, OM-secondary",
1093 L
"Master, OM-primary, OM-secondary",
1098 L
"Master, PI-primary, OM-secondary",
1103 L
"Master, OM/PI-primary, OM-secondary",
1108 L
"Master, OM-secondary",
1113 L
"Master, OM-primary, PI-secondary",
1118 L
"Master, PI-primary, PI-secondary",
1123 L
"Master, OM/PI-primary, PI-secondary",
1128 L
"Master, OM-secondary",
1133 L
"Master, OM-primary, OM/PI-secondary",
1138 L
"Master, PI-primary, OM/PI-secondary",
1143 L
"Master, OM/PI-primary, OM/PI-secondary",
1149 /* null string ends the list */ NULL
1153 PCI_CLASS_ENTRY PCIPIFClass_0105
[] = {
1161 L
"Continuous operation",
1167 /* null string ends the list */ NULL
1171 PCI_CLASS_ENTRY PCIPIFClass_0106
[] = {
1184 L
"Serial Storage Bus",
1190 /* null string ends the list */ NULL
1194 PCI_CLASS_ENTRY PCIPIFClass_0107
[] = {
1208 /* null string ends the list */ NULL
1212 PCI_CLASS_ENTRY PCIPIFClass_0108
[] = {
1231 /* null string ends the list */ NULL
1235 PCI_CLASS_ENTRY PCIPIFClass_0109
[] = {
1249 /* null string ends the list */ NULL
1253 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
1267 /* null string ends the list */ NULL
1271 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
1279 L
"Subtractive decode",
1285 /* null string ends the list */ NULL
1289 PCI_CLASS_ENTRY PCIPIFClass_0609
[] = {
1292 L
"Primary PCI bus side facing the system host processor",
1297 L
"Secondary PCI bus side facing the system host processor",
1303 /* null string ends the list */ NULL
1307 PCI_CLASS_ENTRY PCIPIFClass_060b
[] = {
1315 L
"ASI-SIG Defined Portal",
1321 /* null string ends the list */ NULL
1325 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
1328 L
"Generic XT-compatible",
1333 L
"16450-compatible",
1338 L
"16550-compatible",
1343 L
"16650-compatible",
1348 L
"16750-compatible",
1353 L
"16850-compatible",
1358 L
"16950-compatible",
1364 /* null string ends the list */ NULL
1368 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1381 L
"ECP 1.X-compliant",
1391 L
"IEEE 1284 target (not a controller)",
1397 /* null string ends the list */ NULL
1401 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1409 L
"Hayes-compatible 16450",
1414 L
"Hayes-compatible 16550",
1419 L
"Hayes-compatible 16650",
1424 L
"Hayes-compatible 16750",
1430 /* null string ends the list */ NULL
1434 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1457 L
"IO(x) APIC interrupt controller",
1463 /* null string ends the list */ NULL
1467 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1486 /* null string ends the list */ NULL
1490 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1509 /* null string ends the list */ NULL
1513 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1532 /* null string ends the list */ NULL
1536 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1550 /* null string ends the list */ NULL
1554 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1562 L
"Using 1394 OpenHCI spec",
1568 /* null string ends the list */ NULL
1572 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1595 L
"No specific programming interface",
1600 L
"(Not Host Controller)",
1606 /* null string ends the list */ NULL
1610 PCI_CLASS_ENTRY PCIPIFClass_0c07
[] = {
1618 L
"Keyboard Controller Style",
1629 /* null string ends the list */ NULL
1633 PCI_CLASS_ENTRY PCIPIFClass_0d01
[] = {
1636 L
"Consumer IR controller",
1641 L
"UWB Radio controller",
1647 /* null string ends the list */ NULL
1651 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1654 L
"Message FIFO at offset 40h",
1665 /* null string ends the list */ NULL
1670 Generates printable Unicode strings that represent PCI device class,
1671 subclass and programmed I/F based on a value passed to the function.
1673 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1674 PCI device. The encodings are:
1675 bits 23:16 - Base Class Code
1676 bits 15:8 - Sub-Class Code
1677 bits 7:0 - Programming Interface
1678 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1679 printable class strings corresponding to ClassCode. The
1680 caller must not modify the strings that are pointed by
1681 the fields in ClassStrings.
1684 PciGetClassStrings (
1685 IN UINT32 ClassCode
,
1686 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1691 PCI_CLASS_ENTRY
*CurrentClass
;
1694 // Assume no strings found
1696 ClassStrings
->BaseClass
= L
"UNDEFINED";
1697 ClassStrings
->SubClass
= L
"UNDEFINED";
1698 ClassStrings
->PIFClass
= L
"UNDEFINED";
1700 CurrentClass
= gClassStringList
;
1701 Code
= (UINT8
)(ClassCode
>> 16);
1705 // Go through all entries of the base class, until the entry with a matching
1706 // base class code is found. If reaches an entry with a null description
1707 // text, the last entry is met, which means no text for the base class was
1708 // found, so no more action is needed.
1710 while (Code
!= CurrentClass
[Index
].Code
) {
1711 if (NULL
== CurrentClass
[Index
].DescText
) {
1719 // A base class was found. Assign description, and check if this class has
1720 // sub-class defined. If sub-class defined, no more action is needed,
1721 // otherwise, continue to find description for the sub-class code.
1723 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1724 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1729 // find Subclass entry
1731 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1732 Code
= (UINT8
)(ClassCode
>> 8);
1736 // Go through all entries of the sub-class, until the entry with a matching
1737 // sub-class code is found. If reaches an entry with a null description
1738 // text, the last entry is met, which means no text for the sub-class was
1739 // found, so no more action is needed.
1741 while (Code
!= CurrentClass
[Index
].Code
) {
1742 if (NULL
== CurrentClass
[Index
].DescText
) {
1750 // A class was found for the sub-class code. Assign description, and check if
1751 // this sub-class has programming interface defined. If no, no more action is
1752 // needed, otherwise, continue to find description for the programming
1755 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1756 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1761 // Find programming interface entry
1763 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1764 Code
= (UINT8
)ClassCode
;
1768 // Go through all entries of the I/F entries, until the entry with a
1769 // matching I/F code is found. If reaches an entry with a null description
1770 // text, the last entry is met, which means no text was found, so no more
1771 // action is needed.
1773 while (Code
!= CurrentClass
[Index
].Code
) {
1774 if (NULL
== CurrentClass
[Index
].DescText
) {
1782 // A class was found for the I/F code. Assign description, done!
1784 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1789 Print strings that represent PCI device class, subclass and programmed I/F.
1791 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1792 configuration space.
1793 @param[in] IncludePIF If the printed string should include the programming I/F part
1797 IN UINT8
*ClassCodePtr
,
1798 IN BOOLEAN IncludePIF
1802 PCI_CLASS_STRINGS ClassStrings
;
1805 ClassCode
|= (UINT32
)ClassCodePtr
[0];
1806 ClassCode
|= (UINT32
)(ClassCodePtr
[1] << 8);
1807 ClassCode
|= (UINT32
)(ClassCodePtr
[2] << 16);
1810 // Get name from class code
1812 PciGetClassStrings (ClassCode
, &ClassStrings
);
1816 // Print base class, sub class, and programming inferface name
1822 ClassStrings
.BaseClass
,
1823 ClassStrings
.SubClass
,
1824 ClassStrings
.PIFClass
1828 // Only print base class and sub class name
1834 ClassStrings
.BaseClass
,
1835 ClassStrings
.SubClass
1841 This function finds out the protocol which is in charge of the given
1842 segment, and its bus range covers the current bus number. It lookes
1843 each instances of RootBridgeIoProtocol handle, until the one meets the
1846 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1847 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1848 @param[in] Segment Segment number of device we are dealing with.
1849 @param[in] Bus Bus number of device we are dealing with.
1850 @param[out] IoDev Handle used to access configuration space of PCI device.
1852 @retval EFI_SUCCESS The command completed successfully.
1853 @retval EFI_INVALID_PARAMETER Invalid parameter.
1857 PciFindProtocolInterface (
1858 IN EFI_HANDLE
*HandleBuf
,
1859 IN UINTN HandleCount
,
1862 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1866 This function gets the protocol interface from the given handle, and
1867 obtains its address space descriptors.
1869 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1870 @param[out] IoDev Handle used to access configuration space of PCI device.
1871 @param[out] Descriptors Points to the address space descriptors.
1873 @retval EFI_SUCCESS The command completed successfully
1876 PciGetProtocolAndResource (
1877 IN EFI_HANDLE Handle
,
1878 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1879 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1883 This function get the next bus range of given address space descriptors.
1884 It also moves the pointer backward a node, to get prepared to be called
1887 @param[in, out] Descriptors Points to current position of a serial of address space
1889 @param[out] MinBus The lower range of bus number.
1890 @param[out] MaxBus The upper range of bus number.
1891 @param[out] IsEnd Meet end of the serial of descriptors.
1893 @retval EFI_SUCCESS The command completed successfully.
1896 PciGetNextBusRange (
1897 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1904 Explain the data in PCI configuration space. The part which is common for
1905 PCI device and bridge is interpreted in this function. It calls other
1906 functions to interpret data unique for device or bridge.
1908 @param[in] ConfigSpace Data in PCI configuration space.
1909 @param[in] Address Address used to access configuration space of this PCI device.
1910 @param[in] IoDev Handle used to access configuration space of PCI device.
1914 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1916 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1920 Explain the device specific part of data in PCI configuration space.
1922 @param[in] Device Data in PCI configuration space.
1923 @param[in] Address Address used to access configuration space of this PCI device.
1924 @param[in] IoDev Handle used to access configuration space of PCI device.
1926 @retval EFI_SUCCESS The command completed successfully.
1929 PciExplainDeviceData (
1930 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
1932 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1936 Explain the bridge specific part of data in PCI configuration space.
1938 @param[in] Bridge Bridge specific data region in PCI configuration space.
1939 @param[in] Address Address used to access configuration space of this PCI device.
1940 @param[in] IoDev Handle used to access configuration space of PCI device.
1942 @retval EFI_SUCCESS The command completed successfully.
1945 PciExplainBridgeData (
1946 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
1948 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1952 Explain the Base Address Register(Bar) in PCI configuration space.
1954 @param[in] Bar Points to the Base Address Register intended to interpret.
1955 @param[in] Command Points to the register Command.
1956 @param[in] Address Address used to access configuration space of this PCI device.
1957 @param[in] IoDev Handle used to access configuration space of PCI device.
1958 @param[in, out] Index The Index.
1960 @retval EFI_SUCCESS The command completed successfully.
1967 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1972 Explain the cardbus specific part of data in PCI configuration space.
1974 @param[in] CardBus CardBus specific region of PCI configuration space.
1975 @param[in] Address Address used to access configuration space of this PCI device.
1976 @param[in] IoDev Handle used to access configuration space of PCI device.
1978 @retval EFI_SUCCESS The command completed successfully.
1981 PciExplainCardBusData (
1982 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
1984 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1988 Explain each meaningful bit of register Status. The definition of Status is
1989 slightly different depending on the PCI header type.
1991 @param[in] Status Points to the content of register Status.
1992 @param[in] MainStatus Indicates if this register is main status(not secondary
1994 @param[in] HeaderType Header type of this PCI device.
1996 @retval EFI_SUCCESS The command completed successfully.
2001 IN BOOLEAN MainStatus
,
2002 IN PCI_HEADER_TYPE HeaderType
2006 Explain each meaningful bit of register Command.
2008 @param[in] Command Points to the content of register Command.
2010 @retval EFI_SUCCESS The command completed successfully.
2018 Explain each meaningful bit of register Bridge Control.
2020 @param[in] BridgeControl Points to the content of register Bridge Control.
2021 @param[in] HeaderType The headertype.
2023 @retval EFI_SUCCESS The command completed successfully.
2026 PciExplainBridgeControl (
2027 IN UINT16
*BridgeControl
,
2028 IN PCI_HEADER_TYPE HeaderType
2032 Locate capability register block per capability ID.
2034 @param[in] ConfigSpace Data in PCI configuration space.
2035 @param[in] CapabilityId The capability ID.
2037 @return The offset of the register block per capability ID.
2040 LocatePciCapability (
2041 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2042 IN UINT8 CapabilityId
2046 Display Pcie device structure.
2048 @param[in] PciExpressCap PCI Express capability buffer.
2049 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
2050 @param[in] ExtendedConfigSize PCI Express extended configuration size.
2051 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
2054 PciExplainPciExpress (
2055 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
,
2056 IN UINT8
*ExtendedConfigSpace
,
2057 IN UINTN ExtendedConfigSize
,
2058 IN CONST UINT16 ExtendedCapability
2062 Print out information of the capability information.
2064 @param[in] PciExpressCap The pointer to the structure about the device.
2066 @retval EFI_SUCCESS The operation was successful.
2070 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2074 Print out information of the device capability information.
2076 @param[in] PciExpressCap The pointer to the structure about the device.
2078 @retval EFI_SUCCESS The operation was successful.
2081 ExplainPcieDeviceCap (
2082 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2086 Print out information of the device control information.
2088 @param[in] PciExpressCap The pointer to the structure about the device.
2090 @retval EFI_SUCCESS The operation was successful.
2093 ExplainPcieDeviceControl (
2094 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2098 Print out information of the device status information.
2100 @param[in] PciExpressCap The pointer to the structure about the device.
2102 @retval EFI_SUCCESS The operation was successful.
2105 ExplainPcieDeviceStatus (
2106 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2110 Print out information of the device link information.
2112 @param[in] PciExpressCap The pointer to the structure about the device.
2114 @retval EFI_SUCCESS The operation was successful.
2117 ExplainPcieLinkCap (
2118 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2122 Print out information of the device link control information.
2124 @param[in] PciExpressCap The pointer to the structure about the device.
2126 @retval EFI_SUCCESS The operation was successful.
2129 ExplainPcieLinkControl (
2130 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2134 Print out information of the device link status information.
2136 @param[in] PciExpressCap The pointer to the structure about the device.
2138 @retval EFI_SUCCESS The operation was successful.
2141 ExplainPcieLinkStatus (
2142 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2146 Print out information of the device slot information.
2148 @param[in] PciExpressCap The pointer to the structure about the device.
2150 @retval EFI_SUCCESS The operation was successful.
2153 ExplainPcieSlotCap (
2154 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2158 Print out information of the device slot control information.
2160 @param[in] PciExpressCap The pointer to the structure about the device.
2162 @retval EFI_SUCCESS The operation was successful.
2165 ExplainPcieSlotControl (
2166 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2170 Print out information of the device slot status information.
2172 @param[in] PciExpressCap The pointer to the structure about the device.
2174 @retval EFI_SUCCESS The operation was successful.
2177 ExplainPcieSlotStatus (
2178 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2182 Print out information of the device root information.
2184 @param[in] PciExpressCap The pointer to the structure about the device.
2186 @retval EFI_SUCCESS The operation was successful.
2189 ExplainPcieRootControl (
2190 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2194 Print out information of the device root capability information.
2196 @param[in] PciExpressCap The pointer to the structure about the device.
2198 @retval EFI_SUCCESS The operation was successful.
2201 ExplainPcieRootCap (
2202 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2206 Print out information of the device root status information.
2208 @param[in] PciExpressCap The pointer to the structure about the device.
2210 @retval EFI_SUCCESS The operation was successful.
2213 ExplainPcieRootStatus (
2214 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2217 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (
2218 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2225 } PCIE_CAPREG_FIELD_WIDTH
;
2228 PcieExplainTypeCommon
,
2229 PcieExplainTypeDevice
,
2230 PcieExplainTypeLink
,
2231 PcieExplainTypeSlot
,
2232 PcieExplainTypeRoot
,
2234 } PCIE_EXPLAIN_TYPE
;
2239 PCIE_CAPREG_FIELD_WIDTH Width
;
2240 PCIE_EXPLAIN_FUNCTION Func
;
2241 PCIE_EXPLAIN_TYPE Type
;
2242 } PCIE_EXPLAIN_STRUCT
;
2244 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
2246 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
2250 PcieExplainTypeCommon
2253 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
2257 PcieExplainTypeCommon
2260 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
2264 PcieExplainTypeCommon
2267 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
2270 ExplainPcieDeviceCap
,
2271 PcieExplainTypeDevice
2274 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
2277 ExplainPcieDeviceControl
,
2278 PcieExplainTypeDevice
2281 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
2284 ExplainPcieDeviceStatus
,
2285 PcieExplainTypeDevice
2288 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
2295 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
2298 ExplainPcieLinkControl
,
2302 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
2305 ExplainPcieLinkStatus
,
2309 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
2316 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
2319 ExplainPcieSlotControl
,
2323 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
2326 ExplainPcieSlotStatus
,
2330 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
2333 ExplainPcieRootControl
,
2337 STRING_TOKEN (STR_PCIEX_RSVDP
),
2344 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
2347 ExplainPcieRootStatus
,
2353 (PCIE_CAPREG_FIELD_WIDTH
)0,
2362 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
2363 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
2364 { L
"-s", TypeValue
},
2365 { L
"-i", TypeFlag
},
2366 { L
"-ec", TypeValue
},
2370 CHAR16
*DevicePortTypeTable
[] = {
2371 L
"PCI Express Endpoint",
2372 L
"Legacy PCI Express Endpoint",
2375 L
"Root Port of PCI Express Root Complex",
2376 L
"Upstream Port of PCI Express Switch",
2377 L
"Downstream Port of PCI Express Switch",
2378 L
"PCI Express to PCI/PCI-X Bridge",
2379 L
"PCI/PCI-X to PCI Express Bridge",
2380 L
"Root Complex Integrated Endpoint",
2381 L
"Root Complex Event Collector"
2384 CHAR16
*L0sLatencyStrTable
[] = {
2386 L
"64ns to less than 128ns",
2387 L
"128ns to less than 256ns",
2388 L
"256ns to less than 512ns",
2389 L
"512ns to less than 1us",
2390 L
"1us to less than 2us",
2395 CHAR16
*L1LatencyStrTable
[] = {
2397 L
"1us to less than 2us",
2398 L
"2us to less than 4us",
2399 L
"4us to less than 8us",
2400 L
"8us to less than 16us",
2401 L
"16us to less than 32us",
2406 CHAR16
*ASPMCtrlStrTable
[] = {
2408 L
"L0s Entry Enabled",
2409 L
"L1 Entry Enabled",
2410 L
"L0s and L1 Entry Enabled"
2413 CHAR16
*SlotPwrLmtScaleTable
[] = {
2420 CHAR16
*IndicatorTable
[] = {
2428 Function for 'pci' command.
2430 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2431 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2435 ShellCommandRunPci (
2436 IN EFI_HANDLE ImageHandle
,
2437 IN EFI_SYSTEM_TABLE
*SystemTable
2445 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2447 PCI_DEVICE_INDEPENDENT_REGION PciHeader
;
2448 PCI_CONFIG_SPACE ConfigSpace
;
2452 BOOLEAN ExplainData
;
2456 UINTN HandleBufSize
;
2457 EFI_HANDLE
*HandleBuf
;
2459 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2463 LIST_ENTRY
*Package
;
2464 CHAR16
*ProblemParam
;
2465 SHELL_STATUS ShellStatus
;
2468 UINT16 ExtendedCapability
;
2469 UINT8 PcieCapabilityPtr
;
2470 UINT8
*ExtendedConfigSpace
;
2471 UINTN ExtendedConfigSize
;
2473 ShellStatus
= SHELL_SUCCESS
;
2474 Status
= EFI_SUCCESS
;
2481 // initialize the shell lib (we must be in non-auto-init...)
2483 Status
= ShellInitialize ();
2484 ASSERT_EFI_ERROR (Status
);
2486 Status
= CommandInit ();
2487 ASSERT_EFI_ERROR (Status
);
2490 // parse the command line
2492 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2493 if (EFI_ERROR (Status
)) {
2494 if ((Status
== EFI_VOLUME_CORRUPTED
) && (ProblemParam
!= NULL
)) {
2495 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, L
"pci", ProblemParam
);
2496 FreePool (ProblemParam
);
2497 ShellStatus
= SHELL_INVALID_PARAMETER
;
2502 if (ShellCommandLineGetCount (Package
) == 2) {
2503 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
, L
"pci");
2504 ShellStatus
= SHELL_INVALID_PARAMETER
;
2508 if (ShellCommandLineGetCount (Package
) > 4) {
2509 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
, L
"pci");
2510 ShellStatus
= SHELL_INVALID_PARAMETER
;
2514 if (ShellCommandLineGetFlag (Package
, L
"-ec") && (ShellCommandLineGetValue (Package
, L
"-ec") == NULL
)) {
2515 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-ec");
2516 ShellStatus
= SHELL_INVALID_PARAMETER
;
2520 if (ShellCommandLineGetFlag (Package
, L
"-s") && (ShellCommandLineGetValue (Package
, L
"-s") == NULL
)) {
2521 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-s");
2522 ShellStatus
= SHELL_INVALID_PARAMETER
;
2527 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2528 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2529 // space for handles and call it again.
2531 HandleBufSize
= sizeof (EFI_HANDLE
);
2532 HandleBuf
= (EFI_HANDLE
*)AllocateZeroPool (HandleBufSize
);
2533 if (HandleBuf
== NULL
) {
2534 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2535 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2539 Status
= gBS
->LocateHandle (
2541 &gEfiPciRootBridgeIoProtocolGuid
,
2547 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2548 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2549 if (HandleBuf
== NULL
) {
2550 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2551 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2555 Status
= gBS
->LocateHandle (
2557 &gEfiPciRootBridgeIoProtocolGuid
,
2564 if (EFI_ERROR (Status
)) {
2565 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
, L
"pci");
2566 ShellStatus
= SHELL_NOT_FOUND
;
2570 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2572 // Argument Count == 1(no other argument): enumerate all pci functions
2574 if (ShellCommandLineGetCount (Package
) == 1) {
2575 gST
->ConOut
->QueryMode (
2577 gST
->ConOut
->Mode
->Mode
,
2584 if ((ScreenSize
& 1) == 1) {
2591 // For each handle, which decides a segment and a bus number range,
2592 // enumerate all devices on it.
2594 for (Index
= 0; Index
< HandleCount
; Index
++) {
2595 Status
= PciGetProtocolAndResource (
2600 if (EFI_ERROR (Status
)) {
2601 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, L
"pci");
2602 ShellStatus
= SHELL_NOT_FOUND
;
2607 // No document say it's impossible for a RootBridgeIo protocol handle
2608 // to have more than one address space descriptors, so find out every
2609 // bus range and for each of them do device enumeration.
2612 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2614 if (EFI_ERROR (Status
)) {
2615 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, L
"pci");
2616 ShellStatus
= SHELL_NOT_FOUND
;
2624 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2626 // For each devices, enumerate all functions it contains
2628 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2630 // For each function, read its configuration space and print summary
2632 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2633 if (ShellGetExecutionBreakFlag ()) {
2634 ShellStatus
= SHELL_ABORTED
;
2638 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2648 // If VendorId = 0xffff, there does not exist a device at this
2649 // location. For each device, if there is any function on it,
2650 // there must be 1 function at Function 0. So if Func = 0, there
2651 // will be no more functions in the same device, so we can break
2652 // loop to deal with the next device.
2654 if ((PciHeader
.VendorId
== 0xffff) && (Func
== 0)) {
2658 if (PciHeader
.VendorId
!= 0xffff) {
2660 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2668 sizeof (PciHeader
) / sizeof (UINT32
),
2676 STRING_TOKEN (STR_PCI_LINE_P1
),
2677 gShellDebug1HiiHandle
,
2678 IoDev
->SegmentNumber
,
2684 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2689 STRING_TOKEN (STR_PCI_LINE_P2
),
2690 gShellDebug1HiiHandle
,
2693 PciHeader
.ClassCode
[0]
2697 if ((ScreenCount
>= ScreenSize
) && (ScreenSize
!= 0)) {
2699 // If ScreenSize == 0 we have the console redirected so don't
2706 // If this is not a multi-function device, we can leave the loop
2707 // to deal with the next device.
2709 if ((Func
== 0) && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2718 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2719 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2720 // devices on all bus, we can leave loop.
2722 if (Descriptors
== NULL
) {
2728 Status
= EFI_SUCCESS
;
2732 ExplainData
= FALSE
;
2737 ExtendedCapability
= 0xFFFF;
2738 if (ShellCommandLineGetFlag (Package
, L
"-i")) {
2742 Temp
= ShellCommandLineGetValue (Package
, L
"-s");
2745 // Input converted to hexadecimal number.
2747 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2748 Segment
= (UINT16
)RetVal
;
2750 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2751 ShellStatus
= SHELL_INVALID_PARAMETER
;
2757 // The first Argument(except "-i") is assumed to be Bus number, second
2758 // to be Device number, and third to be Func number.
2760 Temp
= ShellCommandLineGetRawValue (Package
, 1);
2763 // Input converted to hexadecimal number.
2765 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2766 Bus
= (UINT16
)RetVal
;
2768 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2769 ShellStatus
= SHELL_INVALID_PARAMETER
;
2773 if (Bus
> PCI_MAX_BUS
) {
2774 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2775 ShellStatus
= SHELL_INVALID_PARAMETER
;
2780 Temp
= ShellCommandLineGetRawValue (Package
, 2);
2783 // Input converted to hexadecimal number.
2785 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2786 Device
= (UINT16
)RetVal
;
2788 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2789 ShellStatus
= SHELL_INVALID_PARAMETER
;
2793 if (Device
> PCI_MAX_DEVICE
) {
2794 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2795 ShellStatus
= SHELL_INVALID_PARAMETER
;
2800 Temp
= ShellCommandLineGetRawValue (Package
, 3);
2803 // Input converted to hexadecimal number.
2805 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2806 Func
= (UINT16
)RetVal
;
2808 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2809 ShellStatus
= SHELL_INVALID_PARAMETER
;
2813 if (Func
> PCI_MAX_FUNC
) {
2814 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2815 ShellStatus
= SHELL_INVALID_PARAMETER
;
2820 Temp
= ShellCommandLineGetValue (Package
, L
"-ec");
2823 // Input converted to hexadecimal number.
2825 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2826 ExtendedCapability
= (UINT16
)RetVal
;
2828 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2829 ShellStatus
= SHELL_INVALID_PARAMETER
;
2835 // Find the protocol interface who's in charge of current segment, and its
2836 // bus range covers the current bus
2838 Status
= PciFindProtocolInterface (
2846 if (EFI_ERROR (Status
)) {
2851 STRING_TOKEN (STR_PCI_NO_FIND
),
2852 gShellDebug1HiiHandle
,
2857 ShellStatus
= SHELL_NOT_FOUND
;
2861 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2862 Status
= IoDev
->Pci
.Read (
2866 sizeof (ConfigSpace
),
2870 if (EFI_ERROR (Status
)) {
2871 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, L
"pci");
2872 ShellStatus
= SHELL_ACCESS_DENIED
;
2876 mConfigSpace
= &ConfigSpace
;
2881 STRING_TOKEN (STR_PCI_INFO
),
2882 gShellDebug1HiiHandle
,
2894 // Dump standard header of configuration space
2896 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2898 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2899 ShellPrintEx (-1, -1, L
"\r\n");
2902 // Dump device dependent Part of configuration space
2907 sizeof (ConfigSpace
) - SizeOfHeader
,
2911 ExtendedConfigSpace
= NULL
;
2912 ExtendedConfigSize
= 0;
2913 PcieCapabilityPtr
= LocatePciCapability (&ConfigSpace
, EFI_PCI_CAPABILITY_ID_PCIEXP
);
2914 if (PcieCapabilityPtr
!= 0) {
2915 ExtendedConfigSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
2916 ExtendedConfigSpace
= AllocatePool (ExtendedConfigSize
);
2917 if (ExtendedConfigSpace
!= NULL
) {
2918 Status
= IoDev
->Pci
.Read (
2921 EFI_PCI_ADDRESS (Bus
, Device
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
),
2922 ExtendedConfigSize
/ sizeof (UINT32
),
2925 if (EFI_ERROR (Status
)) {
2926 SHELL_FREE_NON_NULL (ExtendedConfigSpace
);
2931 if ((ExtendedConfigSpace
!= NULL
) && !ShellGetExecutionBreakFlag ()) {
2933 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
2935 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
2939 EFI_PCIE_CAPABILITY_BASE_OFFSET
,
2946 // If "-i" appears in command line, interpret data in configuration space
2949 PciExplainPci (&ConfigSpace
, Address
, IoDev
);
2950 if ((ExtendedConfigSpace
!= NULL
) && !ShellGetExecutionBreakFlag ()) {
2951 PciExplainPciExpress (
2952 (PCI_CAPABILITY_PCIEXP
*)((UINT8
*)&ConfigSpace
+ PcieCapabilityPtr
),
2953 ExtendedConfigSpace
,
2962 if (HandleBuf
!= NULL
) {
2963 FreePool (HandleBuf
);
2966 if (Package
!= NULL
) {
2967 ShellCommandLineFreeVarList (Package
);
2970 mConfigSpace
= NULL
;
2975 This function finds out the protocol which is in charge of the given
2976 segment, and its bus range covers the current bus number. It lookes
2977 each instances of RootBridgeIoProtocol handle, until the one meets the
2980 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2981 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2982 @param[in] Segment Segment number of device we are dealing with.
2983 @param[in] Bus Bus number of device we are dealing with.
2984 @param[out] IoDev Handle used to access configuration space of PCI device.
2986 @retval EFI_SUCCESS The command completed successfully.
2987 @retval EFI_INVALID_PARAMETER Invalid parameter.
2991 PciFindProtocolInterface (
2992 IN EFI_HANDLE
*HandleBuf
,
2993 IN UINTN HandleCount
,
2996 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
3001 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
3007 // Go through all handles, until the one meets the criteria is found
3009 for (Index
= 0; Index
< HandleCount
; Index
++) {
3010 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
3011 if (EFI_ERROR (Status
)) {
3016 // When Descriptors == NULL, the Configuration() is not implemented,
3017 // so we only check the Segment number
3019 if ((Descriptors
== NULL
) && (Segment
== (*IoDev
)->SegmentNumber
)) {
3023 if ((*IoDev
)->SegmentNumber
!= Segment
) {
3028 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
3029 if (EFI_ERROR (Status
)) {
3037 if ((MinBus
<= Bus
) && (MaxBus
>= Bus
)) {
3043 return EFI_NOT_FOUND
;
3047 This function gets the protocol interface from the given handle, and
3048 obtains its address space descriptors.
3050 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
3051 @param[out] IoDev Handle used to access configuration space of PCI device.
3052 @param[out] Descriptors Points to the address space descriptors.
3054 @retval EFI_SUCCESS The command completed successfully
3057 PciGetProtocolAndResource (
3058 IN EFI_HANDLE Handle
,
3059 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
3060 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
3066 // Get inferface from protocol
3068 Status
= gBS
->HandleProtocol (
3070 &gEfiPciRootBridgeIoProtocolGuid
,
3074 if (EFI_ERROR (Status
)) {
3079 // Call Configuration() to get address space descriptors
3081 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
3082 if (Status
== EFI_UNSUPPORTED
) {
3083 *Descriptors
= NULL
;
3091 This function get the next bus range of given address space descriptors.
3092 It also moves the pointer backward a node, to get prepared to be called
3095 @param[in, out] Descriptors Points to current position of a serial of address space
3097 @param[out] MinBus The lower range of bus number.
3098 @param[out] MaxBus The upper range of bus number.
3099 @param[out] IsEnd Meet end of the serial of descriptors.
3101 @retval EFI_SUCCESS The command completed successfully.
3104 PciGetNextBusRange (
3105 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
3114 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3115 // range is 0~PCI_MAX_BUS
3117 if ((*Descriptors
) == NULL
) {
3119 *MaxBus
= PCI_MAX_BUS
;
3124 // *Descriptors points to one or more address space descriptors, which
3125 // ends with a end tagged descriptor. Examine each of the descriptors,
3126 // if a bus typed one is found and its bus range covers bus, this handle
3127 // is the handle we are looking for.
3130 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
3131 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
3132 *MinBus
= (UINT16
)(*Descriptors
)->AddrRangeMin
;
3133 *MaxBus
= (UINT16
)(*Descriptors
)->AddrRangeMax
;
3135 return (EFI_SUCCESS
);
3141 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
3149 Explain the data in PCI configuration space. The part which is common for
3150 PCI device and bridge is interpreted in this function. It calls other
3151 functions to interpret data unique for device or bridge.
3153 @param[in] ConfigSpace Data in PCI configuration space.
3154 @param[in] Address Address used to access configuration space of this PCI device.
3155 @param[in] IoDev Handle used to access configuration space of PCI device.
3159 IN PCI_CONFIG_SPACE
*ConfigSpace
,
3161 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3164 PCI_DEVICE_INDEPENDENT_REGION
*Common
;
3165 PCI_HEADER_TYPE HeaderType
;
3167 Common
= &(ConfigSpace
->Common
);
3169 ShellPrintEx (-1, -1, L
"\r\n");
3172 // Print Vendor Id and Device Id
3178 STRING_TOKEN (STR_PCI_LINE_VID_DID
),
3179 gShellDebug1HiiHandle
,
3180 INDEX_OF (&(Common
->VendorId
)),
3182 INDEX_OF (&(Common
->DeviceId
)),
3187 // Print register Command
3189 PciExplainCommand (&(Common
->Command
));
3192 // Print register Status
3194 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
3197 // Print register Revision ID
3199 ShellPrintEx (-1, -1, L
"\r\n");
3204 STRING_TOKEN (STR_PCI_LINE_RID
),
3205 gShellDebug1HiiHandle
,
3206 INDEX_OF (&(Common
->RevisionID
)),
3211 // Print register BIST
3213 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->BIST
)));
3214 if ((Common
->BIST
& BIT7
) != 0) {
3215 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->BIST
);
3217 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
3221 // Print register Cache Line Size
3227 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
3228 gShellDebug1HiiHandle
,
3229 INDEX_OF (&(Common
->CacheLineSize
)),
3230 Common
->CacheLineSize
3234 // Print register Latency Timer
3240 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
3241 gShellDebug1HiiHandle
,
3242 INDEX_OF (&(Common
->LatencyTimer
)),
3243 Common
->LatencyTimer
3247 // Print register Header Type
3253 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
3254 gShellDebug1HiiHandle
,
3255 INDEX_OF (&(Common
->HeaderType
)),
3259 if ((Common
->HeaderType
& BIT7
) != 0) {
3260 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
3262 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
3265 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
)(Common
->HeaderType
& 0x7f);
3266 switch (HeaderType
) {
3268 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
3272 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
3275 case PciCardBusBridge
:
3276 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
3280 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
3281 HeaderType
= PciUndefined
;
3285 // Print register Class Code
3287 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
3288 PciPrintClassCode ((UINT8
*)Common
->ClassCode
, TRUE
);
3289 ShellPrintEx (-1, -1, L
"\r\n");
3293 Explain the device specific part of data in PCI configuration space.
3295 @param[in] Device Data in PCI configuration space.
3296 @param[in] Address Address used to access configuration space of this PCI device.
3297 @param[in] IoDev Handle used to access configuration space of PCI device.
3299 @retval EFI_SUCCESS The command completed successfully.
3302 PciExplainDeviceData (
3303 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
3305 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3314 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3315 // exist. If these no Bar for this function, print "none", otherwise
3316 // list detail information about this Bar.
3318 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
3321 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
3322 for (Index
= 0; Index
< BarCount
; Index
++) {
3323 if (Device
->Bar
[Index
] == 0) {
3329 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
3330 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3333 Status
= PciExplainBar (
3334 &(Device
->Bar
[Index
]),
3335 &(mConfigSpace
->Common
.Command
),
3341 if (EFI_ERROR (Status
)) {
3347 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3349 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3353 // Print register Expansion ROM Base Address
3355 if ((Device
->ExpansionRomBar
& BIT0
) == 0) {
3356 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ExpansionRomBar
)));
3362 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
3363 gShellDebug1HiiHandle
,
3364 INDEX_OF (&(Device
->ExpansionRomBar
)),
3365 Device
->ExpansionRomBar
3370 // Print register Cardbus CIS ptr
3376 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
3377 gShellDebug1HiiHandle
,
3378 INDEX_OF (&(Device
->CISPtr
)),
3383 // Print register Sub-vendor ID and subsystem ID
3389 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
3390 gShellDebug1HiiHandle
,
3391 INDEX_OF (&(Device
->SubsystemVendorID
)),
3392 Device
->SubsystemVendorID
3399 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
3400 gShellDebug1HiiHandle
,
3401 INDEX_OF (&(Device
->SubsystemID
)),
3406 // Print register Capabilities Ptr
3412 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
3413 gShellDebug1HiiHandle
,
3414 INDEX_OF (&(Device
->CapabilityPtr
)),
3415 Device
->CapabilityPtr
3419 // Print register Interrupt Line and interrupt pin
3425 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
3426 gShellDebug1HiiHandle
,
3427 INDEX_OF (&(Device
->InterruptLine
)),
3428 Device
->InterruptLine
3435 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3436 gShellDebug1HiiHandle
,
3437 INDEX_OF (&(Device
->InterruptPin
)),
3438 Device
->InterruptPin
3442 // Print register Min_Gnt and Max_Lat
3448 STRING_TOKEN (STR_PCI2_MIN_GNT
),
3449 gShellDebug1HiiHandle
,
3450 INDEX_OF (&(Device
->MinGnt
)),
3458 STRING_TOKEN (STR_PCI2_MAX_LAT
),
3459 gShellDebug1HiiHandle
,
3460 INDEX_OF (&(Device
->MaxLat
)),
3468 Explain the bridge specific part of data in PCI configuration space.
3470 @param[in] Bridge Bridge specific data region in PCI configuration space.
3471 @param[in] Address Address used to access configuration space of this PCI device.
3472 @param[in] IoDev Handle used to access configuration space of PCI device.
3474 @retval EFI_SUCCESS The command completed successfully.
3477 PciExplainBridgeData (
3478 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
3480 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3490 // Print Base Address Registers. When Bar = 0, this Bar does not
3491 // exist. If these no Bar for this function, print "none", otherwise
3492 // list detail information about this Bar.
3494 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3497 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3499 for (Index
= 0; Index
< BarCount
; Index
++) {
3500 if (Bridge
->Bar
[Index
] == 0) {
3506 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3507 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3510 Status
= PciExplainBar (
3511 &(Bridge
->Bar
[Index
]),
3512 &(mConfigSpace
->Common
.Command
),
3518 if (EFI_ERROR (Status
)) {
3524 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3526 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3530 // Expansion register ROM Base Address
3532 if ((Bridge
->ExpansionRomBAR
& BIT0
) == 0) {
3533 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ExpansionRomBAR
)));
3539 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3540 gShellDebug1HiiHandle
,
3541 INDEX_OF (&(Bridge
->ExpansionRomBAR
)),
3542 Bridge
->ExpansionRomBAR
3547 // Print Bus Numbers(Primary, Secondary, and Subordinate
3553 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3554 gShellDebug1HiiHandle
,
3555 INDEX_OF (&(Bridge
->PrimaryBus
)),
3556 INDEX_OF (&(Bridge
->SecondaryBus
)),
3557 INDEX_OF (&(Bridge
->SubordinateBus
))
3560 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3562 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3563 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3564 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3567 // Print register Secondary Latency Timer
3573 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3574 gShellDebug1HiiHandle
,
3575 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3576 Bridge
->SecondaryLatencyTimer
3580 // Print register Secondary Status
3582 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3585 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3586 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3587 // base and limit address are listed.
3589 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3590 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3595 IoAddress32
= (Bridge
->IoBaseUpper16
<< 16 | Bridge
->IoBase
<< 8);
3596 IoAddress32
&= 0xfffff000;
3601 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3602 gShellDebug1HiiHandle
,
3603 INDEX_OF (&(Bridge
->IoBase
)),
3607 IoAddress32
= (Bridge
->IoLimitUpper16
<< 16 | Bridge
->IoLimit
<< 8);
3608 IoAddress32
|= 0x00000fff;
3609 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3612 // Memory Base & Limit
3618 STRING_TOKEN (STR_PCI2_MEMORY
),
3619 gShellDebug1HiiHandle
,
3620 INDEX_OF (&(Bridge
->MemoryBase
)),
3621 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3628 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3629 gShellDebug1HiiHandle
,
3630 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3634 // Pre-fetch-able Memory Base & Limit
3640 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3641 gShellDebug1HiiHandle
,
3642 INDEX_OF (&(Bridge
->PrefetchableMemoryBase
)),
3643 Bridge
->PrefetchableBaseUpper32
,
3644 (Bridge
->PrefetchableMemoryBase
<< 16) & 0xfff00000
3651 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3652 gShellDebug1HiiHandle
,
3653 Bridge
->PrefetchableLimitUpper32
,
3654 (Bridge
->PrefetchableMemoryLimit
<< 16) | 0x000fffff
3658 // Print register Capabilities Pointer
3664 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3665 gShellDebug1HiiHandle
,
3666 INDEX_OF (&(Bridge
->CapabilityPtr
)),
3667 Bridge
->CapabilityPtr
3671 // Print register Bridge Control
3673 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3676 // Print register Interrupt Line & PIN
3682 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3683 gShellDebug1HiiHandle
,
3684 INDEX_OF (&(Bridge
->InterruptLine
)),
3685 Bridge
->InterruptLine
3692 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3693 gShellDebug1HiiHandle
,
3694 INDEX_OF (&(Bridge
->InterruptPin
)),
3695 Bridge
->InterruptPin
3702 Explain the Base Address Register(Bar) in PCI configuration space.
3704 @param[in] Bar Points to the Base Address Register intended to interpret.
3705 @param[in] Command Points to the register Command.
3706 @param[in] Address Address used to access configuration space of this PCI device.
3707 @param[in] IoDev Handle used to access configuration space of PCI device.
3708 @param[in, out] Index The Index.
3710 @retval EFI_SUCCESS The command completed successfully.
3717 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3738 // According the bar type, list detail about this bar, for example: 32 or
3739 // 64 bits; pre-fetchable or not.
3741 if ((*Bar
& BIT0
) == 0) {
3743 // This bar is of memory type
3747 if (((*Bar
& BIT1
) == 0) && ((*Bar
& BIT2
) == 0)) {
3748 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3749 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3750 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3751 } else if (((*Bar
& BIT1
) == 0) && ((*Bar
& BIT2
) != 0)) {
3753 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3754 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
)RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3755 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
)(Bar64
& 0xfffffffffffffff0ULL
));
3756 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3757 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3764 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3765 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3768 if ((*Bar
& BIT3
) == 0) {
3769 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3771 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3775 // This bar is of io type
3778 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3779 ShellPrintEx (-1, -1, L
"I/O ");
3783 // Get BAR length(or the amount of resource this bar demands for). To get
3784 // Bar length, first we should temporarily disable I/O and memory access
3785 // of this function(by set bits in the register Command), then write all
3786 // "1"s to this bar. The bar value read back is the amount of resource
3787 // this bar demands for.
3790 // Disable io & mem access
3792 OldCommand
= *Command
;
3793 NewCommand
= (UINT16
)(OldCommand
& 0xfffc);
3794 RegAddress
= Address
| INDEX_OF (Command
);
3795 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3797 RegAddress
= Address
| INDEX_OF (Bar
);
3800 // Read after write the BAR to get the size
3804 NewBar32
= 0xffffffff;
3806 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3807 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3808 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3811 NewBar32
= NewBar32
& 0xfffffff0;
3812 NewBar32
= (~NewBar32
) + 1;
3814 NewBar32
= NewBar32
& 0xfffffffc;
3815 NewBar32
= (~NewBar32
) + 1;
3816 NewBar32
= NewBar32
& 0x0000ffff;
3820 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3821 NewBar64
= 0xffffffffffffffffULL
;
3823 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3824 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3825 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3828 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3829 NewBar64
= (~NewBar64
) + 1;
3831 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3832 NewBar64
= (~NewBar64
) + 1;
3833 NewBar64
= NewBar64
& 0x000000000000ffff;
3838 // Enable io & mem access
3840 RegAddress
= Address
| INDEX_OF (Command
);
3841 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3845 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3846 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3848 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
)RShiftU64 (NewBar64
, 32));
3849 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
)NewBar64
);
3850 ShellPrintEx (-1, -1, L
" ");
3855 STRING_TOKEN (STR_PCI2_RSHIFT
),
3856 gShellDebug1HiiHandle
,
3857 (UINT32
)RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3859 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
)(NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3862 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3863 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3870 Explain the cardbus specific part of data in PCI configuration space.
3872 @param[in] CardBus CardBus specific region of PCI configuration space.
3873 @param[in] Address Address used to access configuration space of this PCI device.
3874 @param[in] IoDev Handle used to access configuration space of PCI device.
3876 @retval EFI_SUCCESS The command completed successfully.
3879 PciExplainCardBusData (
3880 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
3882 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3886 PCI_CARDBUS_DATA
*CardBusData
;
3892 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3893 gShellDebug1HiiHandle
,
3894 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3895 CardBus
->CardBusSocketReg
3899 // Print Secondary Status
3901 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3904 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3905 // Subordinate bus number
3911 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3912 gShellDebug1HiiHandle
,
3913 INDEX_OF (&(CardBus
->PciBusNumber
)),
3914 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3915 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3918 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3920 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3921 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3922 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3925 // Print CardBus Latency Timer
3931 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3932 gShellDebug1HiiHandle
,
3933 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3934 CardBus
->CardBusLatencyTimer
3938 // Print Memory/Io ranges this cardbus bridge forwards
3940 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3941 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3947 STRING_TOKEN (STR_PCI2_MEM_3
),
3948 gShellDebug1HiiHandle
,
3949 INDEX_OF (&(CardBus
->MemoryBase0
)),
3950 CardBus
->BridgeControl
& BIT8
? L
" Prefetchable" : L
"Non-Prefetchable",
3951 CardBus
->MemoryBase0
& 0xfffff000,
3952 CardBus
->MemoryLimit0
| 0x00000fff
3959 STRING_TOKEN (STR_PCI2_MEM_3
),
3960 gShellDebug1HiiHandle
,
3961 INDEX_OF (&(CardBus
->MemoryBase1
)),
3962 CardBus
->BridgeControl
& BIT9
? L
" Prefetchable" : L
"Non-Prefetchable",
3963 CardBus
->MemoryBase1
& 0xfffff000,
3964 CardBus
->MemoryLimit1
| 0x00000fff
3967 Io32Bit
= (BOOLEAN
)(CardBus
->IoBase0
& BIT0
);
3972 STRING_TOKEN (STR_PCI2_IO_2
),
3973 gShellDebug1HiiHandle
,
3974 INDEX_OF (&(CardBus
->IoBase0
)),
3975 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3976 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3977 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3980 Io32Bit
= (BOOLEAN
)(CardBus
->IoBase1
& BIT0
);
3985 STRING_TOKEN (STR_PCI2_IO_2
),
3986 gShellDebug1HiiHandle
,
3987 INDEX_OF (&(CardBus
->IoBase1
)),
3988 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3989 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3990 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3994 // Print register Interrupt Line & PIN
4000 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
4001 gShellDebug1HiiHandle
,
4002 INDEX_OF (&(CardBus
->InterruptLine
)),
4003 CardBus
->InterruptLine
,
4004 INDEX_OF (&(CardBus
->InterruptPin
)),
4005 CardBus
->InterruptPin
4009 // Print register Bridge Control
4011 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
4014 // Print some registers in data region of PCI configuration space for cardbus
4015 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
4018 CardBusData
= (PCI_CARDBUS_DATA
*)((UINT8
*)CardBus
+ sizeof (PCI_CARDBUS_CONTROL_REGISTER
));
4024 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
4025 gShellDebug1HiiHandle
,
4026 INDEX_OF (&(CardBusData
->SubVendorId
)),
4027 CardBusData
->SubVendorId
,
4028 INDEX_OF (&(CardBusData
->SubSystemId
)),
4029 CardBusData
->SubSystemId
4036 STRING_TOKEN (STR_PCI2_OPTIONAL
),
4037 gShellDebug1HiiHandle
,
4038 INDEX_OF (&(CardBusData
->LegacyBase
)),
4039 CardBusData
->LegacyBase
4046 Explain each meaningful bit of register Status. The definition of Status is
4047 slightly different depending on the PCI header type.
4049 @param[in] Status Points to the content of register Status.
4050 @param[in] MainStatus Indicates if this register is main status(not secondary
4052 @param[in] HeaderType Header type of this PCI device.
4054 @retval EFI_SUCCESS The command completed successfully.
4059 IN BOOLEAN MainStatus
,
4060 IN PCI_HEADER_TYPE HeaderType
4064 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
4066 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
4069 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& BIT4
) != 0);
4072 // Bit 5 is meaningless for CardBus Bridge
4074 if (HeaderType
== PciCardBusBridge
) {
4075 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
4077 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
4080 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& BIT7
) != 0);
4082 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& BIT8
) != 0);
4084 // Bit 9 and bit 10 together decides the DEVSEL timing
4086 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
4087 if (((*Status
& BIT9
) == 0) && ((*Status
& BIT10
) == 0)) {
4088 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
4089 } else if (((*Status
& BIT9
) != 0) && ((*Status
& BIT10
) == 0)) {
4090 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
4091 } else if (((*Status
& BIT9
) == 0) && ((*Status
& BIT10
) != 0)) {
4092 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
4094 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
4101 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
4102 gShellDebug1HiiHandle
,
4103 (*Status
& BIT11
) != 0
4110 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
4111 gShellDebug1HiiHandle
,
4112 (*Status
& BIT12
) != 0
4119 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
4120 gShellDebug1HiiHandle
,
4121 (*Status
& BIT13
) != 0
4129 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
4130 gShellDebug1HiiHandle
,
4131 (*Status
& BIT14
) != 0
4138 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
4139 gShellDebug1HiiHandle
,
4140 (*Status
& BIT14
) != 0
4148 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
4149 gShellDebug1HiiHandle
,
4150 (*Status
& BIT15
) != 0
4157 Explain each meaningful bit of register Command.
4159 @param[in] Command Points to the content of register Command.
4161 @retval EFI_SUCCESS The command completed successfully.
4169 // Print the binary value of register Command
4171 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
4174 // Explain register Command bit by bit
4180 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
4181 gShellDebug1HiiHandle
,
4182 (*Command
& BIT0
) != 0
4189 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
4190 gShellDebug1HiiHandle
,
4191 (*Command
& BIT1
) != 0
4198 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
4199 gShellDebug1HiiHandle
,
4200 (*Command
& BIT2
) != 0
4207 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
4208 gShellDebug1HiiHandle
,
4209 (*Command
& BIT3
) != 0
4216 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
4217 gShellDebug1HiiHandle
,
4218 (*Command
& BIT4
) != 0
4225 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
4226 gShellDebug1HiiHandle
,
4227 (*Command
& BIT5
) != 0
4234 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
4235 gShellDebug1HiiHandle
,
4236 (*Command
& BIT6
) != 0
4243 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
4244 gShellDebug1HiiHandle
,
4245 (*Command
& BIT7
) != 0
4252 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
4253 gShellDebug1HiiHandle
,
4254 (*Command
& BIT8
) != 0
4261 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
4262 gShellDebug1HiiHandle
,
4263 (*Command
& BIT9
) != 0
4270 Explain each meaningful bit of register Bridge Control.
4272 @param[in] BridgeControl Points to the content of register Bridge Control.
4273 @param[in] HeaderType The headertype.
4275 @retval EFI_SUCCESS The command completed successfully.
4278 PciExplainBridgeControl (
4279 IN UINT16
*BridgeControl
,
4280 IN PCI_HEADER_TYPE HeaderType
4287 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
4288 gShellDebug1HiiHandle
,
4289 INDEX_OF (BridgeControl
),
4297 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
4298 gShellDebug1HiiHandle
,
4299 (*BridgeControl
& BIT0
) != 0
4305 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
4306 gShellDebug1HiiHandle
,
4307 (*BridgeControl
& BIT1
) != 0
4313 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
4314 gShellDebug1HiiHandle
,
4315 (*BridgeControl
& BIT2
) != 0
4321 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
4322 gShellDebug1HiiHandle
,
4323 (*BridgeControl
& BIT3
) != 0
4329 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
4330 gShellDebug1HiiHandle
,
4331 (*BridgeControl
& BIT5
) != 0
4335 // Register Bridge Control has some slight differences between P2P bridge
4336 // and Cardbus bridge from bit 6 to bit 11.
4338 if (HeaderType
== PciP2pBridge
) {
4343 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
4344 gShellDebug1HiiHandle
,
4345 (*BridgeControl
& BIT6
) != 0
4351 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
4352 gShellDebug1HiiHandle
,
4353 (*BridgeControl
& BIT7
) != 0
4359 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
4360 gShellDebug1HiiHandle
,
4361 (*BridgeControl
& BIT8
) != 0 ? L
"2^10" : L
"2^15"
4367 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
4368 gShellDebug1HiiHandle
,
4369 (*BridgeControl
& BIT9
) != 0 ? L
"2^10" : L
"2^15"
4375 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
4376 gShellDebug1HiiHandle
,
4377 (*BridgeControl
& BIT10
) != 0
4383 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
4384 gShellDebug1HiiHandle
,
4385 (*BridgeControl
& BIT11
) != 0
4392 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
4393 gShellDebug1HiiHandle
,
4394 (*BridgeControl
& BIT6
) != 0
4400 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
4401 gShellDebug1HiiHandle
,
4402 (*BridgeControl
& BIT7
) != 0
4408 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
4409 gShellDebug1HiiHandle
,
4410 (*BridgeControl
& BIT10
) != 0
4418 Locate capability register block per capability ID.
4420 @param[in] ConfigSpace Data in PCI configuration space.
4421 @param[in] CapabilityId The capability ID.
4423 @return The offset of the register block per capability ID,
4424 or 0 if the register block cannot be found.
4427 LocatePciCapability (
4428 IN PCI_CONFIG_SPACE
*ConfigSpace
,
4429 IN UINT8 CapabilityId
4432 UINT8 CapabilityPtr
;
4433 EFI_PCI_CAPABILITY_HDR
*CapabilityEntry
;
4436 // To check the cpability of this device supports
4438 if ((ConfigSpace
->Common
.Status
& EFI_PCI_STATUS_CAPABILITY
) == 0) {
4442 switch ((PCI_HEADER_TYPE
)(ConfigSpace
->Common
.HeaderType
& 0x7f)) {
4444 CapabilityPtr
= ConfigSpace
->NonCommon
.Device
.CapabilityPtr
;
4447 CapabilityPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilityPtr
;
4449 case PciCardBusBridge
:
4450 CapabilityPtr
= ConfigSpace
->NonCommon
.CardBus
.Cap_Ptr
;
4456 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
4457 CapabilityEntry
= (EFI_PCI_CAPABILITY_HDR
*)((UINT8
*)ConfigSpace
+ CapabilityPtr
);
4458 if (CapabilityEntry
->CapabilityID
== CapabilityId
) {
4459 return CapabilityPtr
;
4463 // Certain PCI device may incorrectly have capability pointing to itself,
4464 // break to avoid dead loop.
4466 if (CapabilityPtr
== CapabilityEntry
->NextItemPtr
) {
4470 CapabilityPtr
= CapabilityEntry
->NextItemPtr
;
4477 Print out information of the capability information.
4479 @param[in] PciExpressCap The pointer to the structure about the device.
4481 @retval EFI_SUCCESS The operation was successful.
4485 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4488 CHAR16
*DevicePortType
;
4493 L
" Capability Version(3:0): %E0x%04x%N\r\n",
4494 PciExpressCap
->Capability
.Bits
.Version
4496 if (PciExpressCap
->Capability
.Bits
.DevicePortType
< ARRAY_SIZE (DevicePortTypeTable
)) {
4497 DevicePortType
= DevicePortTypeTable
[PciExpressCap
->Capability
.Bits
.DevicePortType
];
4499 DevicePortType
= L
"Unknown Type";
4505 L
" Device/PortType(7:4): %E%s%N\r\n",
4509 // 'Slot Implemented' is only valid for:
4510 // a) Root Port of PCI Express Root Complex, or
4511 // b) Downstream Port of PCI Express Switch
4513 if ((PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_PORT
) ||
4514 (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
))
4519 L
" Slot Implemented(8): %E%d%N\r\n",
4520 PciExpressCap
->Capability
.Bits
.SlotImplemented
4527 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4528 PciExpressCap
->Capability
.Bits
.InterruptMessageNumber
4534 Print out information of the device capability information.
4536 @param[in] PciExpressCap The pointer to the structure about the device.
4538 @retval EFI_SUCCESS The operation was successful.
4541 ExplainPcieDeviceCap (
4542 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4545 UINT8 DevicePortType
;
4549 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4550 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
4551 if (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
< 6) {
4552 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
+ 7));
4554 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4560 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
4561 PciExpressCap
->DeviceCapability
.Bits
.PhantomFunctions
4566 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4567 PciExpressCap
->DeviceCapability
.Bits
.ExtendedTagField
? 8 : 5
4570 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4572 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4573 L0sLatency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL0sAcceptableLatency
;
4574 L1Latency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL1AcceptableLatency
;
4575 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
4576 if (L0sLatency
< 4) {
4577 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
4579 if (L0sLatency
< 7) {
4580 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
4582 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4586 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
4587 if (L1Latency
< 7) {
4588 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
4590 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4597 L
" Role-based Error Reporting(15): %E%d%N\r\n",
4598 PciExpressCap
->DeviceCapability
.Bits
.RoleBasedErrorReporting
4601 // Only valid for Upstream Port:
4602 // a) Captured Slot Power Limit Value
4603 // b) Captured Slot Power Scale
4605 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
) {
4609 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4610 PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitValue
4615 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4616 SlotPwrLmtScaleTable
[PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitScale
]
4621 // Function Level Reset Capability is only valid for Endpoint
4623 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4627 L
" Function Level Reset Capability(28): %E%d%N\r\n",
4628 PciExpressCap
->DeviceCapability
.Bits
.FunctionLevelReset
4636 Print out information of the device control information.
4638 @param[in] PciExpressCap The pointer to the structure about the device.
4640 @retval EFI_SUCCESS The operation was successful.
4643 ExplainPcieDeviceControl (
4644 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4650 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4651 PciExpressCap
->DeviceControl
.Bits
.CorrectableError
4656 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4657 PciExpressCap
->DeviceControl
.Bits
.NonFatalError
4662 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4663 PciExpressCap
->DeviceControl
.Bits
.FatalError
4668 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4669 PciExpressCap
->DeviceControl
.Bits
.UnsupportedRequest
4674 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4675 PciExpressCap
->DeviceControl
.Bits
.RelaxedOrdering
4677 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4678 if (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
< 6) {
4679 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
+ 7));
4681 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4687 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4688 PciExpressCap
->DeviceControl
.Bits
.ExtendedTagField
4693 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4694 PciExpressCap
->DeviceControl
.Bits
.PhantomFunctions
4699 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4700 PciExpressCap
->DeviceControl
.Bits
.AuxPower
4705 L
" Enable No Snoop(11): %E%d%N\r\n",
4706 PciExpressCap
->DeviceControl
.Bits
.NoSnoop
4708 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4709 if (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
< 6) {
4710 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
+ 7));
4712 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4716 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4718 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4722 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4723 PciExpressCap
->DeviceControl
.Bits
.BridgeConfigurationRetryOrFunctionLevelReset
4731 Print out information of the device status information.
4733 @param[in] PciExpressCap The pointer to the structure about the device.
4735 @retval EFI_SUCCESS The operation was successful.
4738 ExplainPcieDeviceStatus (
4739 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4745 L
" Correctable Error Detected(0): %E%d%N\r\n",
4746 PciExpressCap
->DeviceStatus
.Bits
.CorrectableError
4751 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4752 PciExpressCap
->DeviceStatus
.Bits
.NonFatalError
4757 L
" Fatal Error Detected(2): %E%d%N\r\n",
4758 PciExpressCap
->DeviceStatus
.Bits
.FatalError
4763 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4764 PciExpressCap
->DeviceStatus
.Bits
.UnsupportedRequest
4769 L
" AUX Power Detected(4): %E%d%N\r\n",
4770 PciExpressCap
->DeviceStatus
.Bits
.AuxPower
4775 L
" Transactions Pending(5): %E%d%N\r\n",
4776 PciExpressCap
->DeviceStatus
.Bits
.TransactionsPending
4782 Print out information of the device link information.
4784 @param[in] PciExpressCap The pointer to the structure about the device.
4786 @retval EFI_SUCCESS The operation was successful.
4789 ExplainPcieLinkCap (
4790 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4793 CHAR16
*MaxLinkSpeed
;
4796 switch (PciExpressCap
->LinkCapability
.Bits
.MaxLinkSpeed
) {
4798 MaxLinkSpeed
= L
"2.5 GT/s";
4801 MaxLinkSpeed
= L
"5.0 GT/s";
4804 MaxLinkSpeed
= L
"8.0 GT/s";
4807 MaxLinkSpeed
= L
"16.0 GT/s";
4810 MaxLinkSpeed
= L
"32.0 GT/s";
4813 MaxLinkSpeed
= L
"Reserved";
4820 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4826 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4827 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
4829 switch (PciExpressCap
->LinkCapability
.Bits
.Aspm
) {
4840 AspmValue
= L
"L0s and L1";
4843 AspmValue
= L
"Reserved";
4850 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4856 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4857 L0sLatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L0sExitLatency
]
4862 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4863 L1LatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L1ExitLatency
]
4868 L
" Clock Power Management(18): %E%d%N\r\n",
4869 PciExpressCap
->LinkCapability
.Bits
.ClockPowerManagement
4874 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4875 PciExpressCap
->LinkCapability
.Bits
.SurpriseDownError
4880 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4881 PciExpressCap
->LinkCapability
.Bits
.DataLinkLayerLinkActive
4886 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4887 PciExpressCap
->LinkCapability
.Bits
.LinkBandwidthNotification
4892 L
" Port Number(31:24): %E0x%02x%N\r\n",
4893 PciExpressCap
->LinkCapability
.Bits
.PortNumber
4899 Print out information of the device link control information.
4901 @param[in] PciExpressCap The pointer to the structure about the device.
4903 @retval EFI_SUCCESS The operation was successful.
4906 ExplainPcieLinkControl (
4907 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4910 UINT8 DevicePortType
;
4912 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4916 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4917 ASPMCtrlStrTable
[PciExpressCap
->LinkControl
.Bits
.AspmControl
]
4920 // RCB is not applicable to switches
4922 if (!IS_PCIE_SWITCH (DevicePortType
)) {
4926 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4927 1 << (PciExpressCap
->LinkControl
.Bits
.ReadCompletionBoundary
+ 6)
4932 // Link Disable is reserved on
4934 // b) PCI Express to PCI/PCI-X bridges
4935 // c) Upstream Ports of Switches
4937 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4938 (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
) &&
4939 (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
))
4944 L
" Link Disable(4): %E%d%N\r\n",
4945 PciExpressCap
->LinkControl
.Bits
.LinkDisable
4952 L
" Common Clock Configuration(6): %E%d%N\r\n",
4953 PciExpressCap
->LinkControl
.Bits
.CommonClockConfiguration
4958 L
" Extended Synch(7): %E%d%N\r\n",
4959 PciExpressCap
->LinkControl
.Bits
.ExtendedSynch
4964 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4965 PciExpressCap
->LinkControl
.Bits
.ClockPowerManagement
4970 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4971 PciExpressCap
->LinkControl
.Bits
.HardwareAutonomousWidthDisable
4976 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4977 PciExpressCap
->LinkControl
.Bits
.LinkBandwidthManagementInterrupt
4982 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4983 PciExpressCap
->LinkControl
.Bits
.LinkAutonomousBandwidthInterrupt
4989 Print out information of the device link status information.
4991 @param[in] PciExpressCap The pointer to the structure about the device.
4993 @retval EFI_SUCCESS The operation was successful.
4996 ExplainPcieLinkStatus (
4997 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5000 CHAR16
*CurLinkSpeed
;
5002 switch (PciExpressCap
->LinkStatus
.Bits
.CurrentLinkSpeed
) {
5004 CurLinkSpeed
= L
"2.5 GT/s";
5007 CurLinkSpeed
= L
"5.0 GT/s";
5010 CurLinkSpeed
= L
"8.0 GT/s";
5013 CurLinkSpeed
= L
"16.0 GT/s";
5016 CurLinkSpeed
= L
"32.0 GT/s";
5019 CurLinkSpeed
= L
"Reserved";
5026 L
" Current Link Speed(3:0): %E%s%N\r\n",
5032 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
5033 PciExpressCap
->LinkStatus
.Bits
.NegotiatedLinkWidth
5038 L
" Link Training(11): %E%d%N\r\n",
5039 PciExpressCap
->LinkStatus
.Bits
.LinkTraining
5044 L
" Slot Clock Configuration(12): %E%d%N\r\n",
5045 PciExpressCap
->LinkStatus
.Bits
.SlotClockConfiguration
5050 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
5051 PciExpressCap
->LinkStatus
.Bits
.DataLinkLayerLinkActive
5056 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
5057 PciExpressCap
->LinkStatus
.Bits
.LinkBandwidthManagement
5062 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
5063 PciExpressCap
->LinkStatus
.Bits
.LinkAutonomousBandwidth
5069 Print out information of the device slot information.
5071 @param[in] PciExpressCap The pointer to the structure about the device.
5073 @retval EFI_SUCCESS The operation was successful.
5076 ExplainPcieSlotCap (
5077 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5083 L
" Attention Button Present(0): %E%d%N\r\n",
5084 PciExpressCap
->SlotCapability
.Bits
.AttentionButton
5089 L
" Power Controller Present(1): %E%d%N\r\n",
5090 PciExpressCap
->SlotCapability
.Bits
.PowerController
5095 L
" MRL Sensor Present(2): %E%d%N\r\n",
5096 PciExpressCap
->SlotCapability
.Bits
.MrlSensor
5101 L
" Attention Indicator Present(3): %E%d%N\r\n",
5102 PciExpressCap
->SlotCapability
.Bits
.AttentionIndicator
5107 L
" Power Indicator Present(4): %E%d%N\r\n",
5108 PciExpressCap
->SlotCapability
.Bits
.PowerIndicator
5113 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
5114 PciExpressCap
->SlotCapability
.Bits
.HotPlugSurprise
5119 L
" Hot-Plug Capable(6): %E%d%N\r\n",
5120 PciExpressCap
->SlotCapability
.Bits
.HotPlugCapable
5125 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
5126 PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitValue
5131 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
5132 SlotPwrLmtScaleTable
[PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitScale
]
5137 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
5138 PciExpressCap
->SlotCapability
.Bits
.ElectromechanicalInterlock
5143 L
" No Command Completed Support(18): %E%d%N\r\n",
5144 PciExpressCap
->SlotCapability
.Bits
.NoCommandCompleted
5149 L
" Physical Slot Number(31:19): %E%d%N\r\n",
5150 PciExpressCap
->SlotCapability
.Bits
.PhysicalSlotNumber
5157 Print out information of the device slot control information.
5159 @param[in] PciExpressCap The pointer to the structure about the device.
5161 @retval EFI_SUCCESS The operation was successful.
5164 ExplainPcieSlotControl (
5165 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5171 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
5172 PciExpressCap
->SlotControl
.Bits
.AttentionButtonPressed
5177 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
5178 PciExpressCap
->SlotControl
.Bits
.PowerFaultDetected
5183 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
5184 PciExpressCap
->SlotControl
.Bits
.MrlSensorChanged
5189 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
5190 PciExpressCap
->SlotControl
.Bits
.PresenceDetectChanged
5195 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
5196 PciExpressCap
->SlotControl
.Bits
.CommandCompletedInterrupt
5201 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
5202 PciExpressCap
->SlotControl
.Bits
.HotPlugInterrupt
5207 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
5209 PciExpressCap
->SlotControl
.Bits
.AttentionIndicator
]
5214 L
" Power Indicator Control(9:8): %E%s%N\r\n",
5215 IndicatorTable
[PciExpressCap
->SlotControl
.Bits
.PowerIndicator
]
5217 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
5219 PciExpressCap
->SlotControl
.Bits
.PowerController
)
5221 ShellPrintEx (-1, -1, L
"Off%N\r\n");
5223 ShellPrintEx (-1, -1, L
"On%N\r\n");
5229 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
5230 PciExpressCap
->SlotControl
.Bits
.ElectromechanicalInterlock
5235 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
5236 PciExpressCap
->SlotControl
.Bits
.DataLinkLayerStateChanged
5242 Print out information of the device slot status information.
5244 @param[in] PciExpressCap The pointer to the structure about the device.
5246 @retval EFI_SUCCESS The operation was successful.
5249 ExplainPcieSlotStatus (
5250 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5256 L
" Attention Button Pressed(0): %E%d%N\r\n",
5257 PciExpressCap
->SlotStatus
.Bits
.AttentionButtonPressed
5262 L
" Power Fault Detected(1): %E%d%N\r\n",
5263 PciExpressCap
->SlotStatus
.Bits
.PowerFaultDetected
5268 L
" MRL Sensor Changed(2): %E%d%N\r\n",
5269 PciExpressCap
->SlotStatus
.Bits
.MrlSensorChanged
5274 L
" Presence Detect Changed(3): %E%d%N\r\n",
5275 PciExpressCap
->SlotStatus
.Bits
.PresenceDetectChanged
5280 L
" Command Completed(4): %E%d%N\r\n",
5281 PciExpressCap
->SlotStatus
.Bits
.CommandCompleted
5283 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
5285 PciExpressCap
->SlotStatus
.Bits
.MrlSensor
)
5287 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
5289 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
5292 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
5294 PciExpressCap
->SlotStatus
.Bits
.PresenceDetect
)
5296 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
5298 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
5301 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
5303 PciExpressCap
->SlotStatus
.Bits
.ElectromechanicalInterlock
)
5305 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
5307 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
5313 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
5314 PciExpressCap
->SlotStatus
.Bits
.DataLinkLayerStateChanged
5320 Print out information of the device root information.
5322 @param[in] PciExpressCap The pointer to the structure about the device.
5324 @retval EFI_SUCCESS The operation was successful.
5327 ExplainPcieRootControl (
5328 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5334 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
5335 PciExpressCap
->RootControl
.Bits
.SystemErrorOnCorrectableError
5340 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
5341 PciExpressCap
->RootControl
.Bits
.SystemErrorOnNonFatalError
5346 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
5347 PciExpressCap
->RootControl
.Bits
.SystemErrorOnFatalError
5352 L
" PME Interrupt Enable(3): %E%d%N\r\n",
5353 PciExpressCap
->RootControl
.Bits
.PmeInterrupt
5358 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
5359 PciExpressCap
->RootControl
.Bits
.CrsSoftwareVisibility
5366 Print out information of the device root capability information.
5368 @param[in] PciExpressCap The pointer to the structure about the device.
5370 @retval EFI_SUCCESS The operation was successful.
5373 ExplainPcieRootCap (
5374 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5380 L
" CRS Software Visibility(0): %E%d%N\r\n",
5381 PciExpressCap
->RootCapability
.Bits
.CrsSoftwareVisibility
5388 Print out information of the device root status information.
5390 @param[in] PciExpressCap The pointer to the structure about the device.
5392 @retval EFI_SUCCESS The operation was successful.
5395 ExplainPcieRootStatus (
5396 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
5402 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
5403 PciExpressCap
->RootStatus
.Bits
.PmeRequesterId
5408 L
" PME Status(16): %E%d%N\r\n",
5409 PciExpressCap
->RootStatus
.Bits
.PmeStatus
5414 L
" PME Pending(17): %E%d%N\r\n",
5415 PciExpressCap
->RootStatus
.Bits
.PmePending
5421 Function to interpret and print out the link control structure
5423 @param[in] HeaderAddress The Address of this capability header.
5424 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5427 PrintInterpretedExtendedCompatibilityLinkControl (
5428 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5429 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5432 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
5434 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
5440 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
5441 gShellDebug1HiiHandle
,
5442 Header
->RootComplexLinkCapabilities
,
5443 Header
->RootComplexLinkControl
,
5444 Header
->RootComplexLinkStatus
5448 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5449 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
5450 (VOID
*)(HeaderAddress
)
5452 return (EFI_SUCCESS
);
5456 Function to interpret and print out the power budgeting structure
5458 @param[in] HeaderAddress The Address of this capability header.
5459 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5462 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5463 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5464 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5467 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
5469 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
5475 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
5476 gShellDebug1HiiHandle
,
5479 Header
->PowerBudgetCapability
5483 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5484 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
5485 (VOID
*)(HeaderAddress
)
5487 return (EFI_SUCCESS
);
5491 Function to interpret and print out the ACS structure
5493 @param[in] HeaderAddress The Address of this capability header.
5494 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5497 PrintInterpretedExtendedCompatibilityAcs (
5498 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5499 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5502 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
5506 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
5513 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
5514 gShellDebug1HiiHandle
,
5515 Header
->AcsCapability
,
5518 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL (Header
)) {
5519 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE (Header
);
5520 if (VectorSize
== 0) {
5524 for (LoopCounter
= 0; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
5529 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
5530 gShellDebug1HiiHandle
,
5532 Header
->EgressControlVectorArray
[LoopCounter
]
5539 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5540 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
5541 (VOID
*)(HeaderAddress
)
5543 return (EFI_SUCCESS
);
5547 Function to interpret and print out the latency tolerance reporting structure
5549 @param[in] HeaderAddress The Address of this capability header.
5550 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5553 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5554 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5555 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5558 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
5560 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
5566 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
5567 gShellDebug1HiiHandle
,
5568 Header
->MaxSnoopLatency
,
5569 Header
->MaxNoSnoopLatency
5573 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5574 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
5575 (VOID
*)(HeaderAddress
)
5577 return (EFI_SUCCESS
);
5581 Function to interpret and print out the serial number structure
5583 @param[in] HeaderAddress The Address of this capability header.
5584 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5587 PrintInterpretedExtendedCompatibilitySerialNumber (
5588 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5589 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5592 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
5594 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
5600 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
5601 gShellDebug1HiiHandle
,
5602 Header
->SerialNumber
5606 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5607 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
5608 (VOID
*)(HeaderAddress
)
5610 return (EFI_SUCCESS
);
5614 Function to interpret and print out the RCRB structure
5616 @param[in] HeaderAddress The Address of this capability header.
5617 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5620 PrintInterpretedExtendedCompatibilityRcrb (
5621 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5622 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5625 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
5627 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
5633 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
5634 gShellDebug1HiiHandle
,
5637 Header
->RcrbCapabilities
,
5642 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5643 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
5644 (VOID
*)(HeaderAddress
)
5646 return (EFI_SUCCESS
);
5650 Function to interpret and print out the vendor specific structure
5652 @param[in] HeaderAddress The Address of this capability header.
5653 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5656 PrintInterpretedExtendedCompatibilityVendorSpecific (
5657 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5658 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5661 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
5663 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
5669 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
5670 gShellDebug1HiiHandle
,
5671 Header
->VendorSpecificHeader
5675 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5676 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE (Header
),
5677 (VOID
*)(HeaderAddress
)
5679 return (EFI_SUCCESS
);
5683 Function to interpret and print out the Event Collector Endpoint Association structure
5685 @param[in] HeaderAddress The Address of this capability header.
5686 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5689 PrintInterpretedExtendedCompatibilityECEA (
5690 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5691 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5694 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
5696 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
5702 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
5703 gShellDebug1HiiHandle
,
5704 Header
->AssociationBitmap
5708 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5709 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
5710 (VOID
*)(HeaderAddress
)
5712 return (EFI_SUCCESS
);
5716 Function to interpret and print out the ARI structure
5718 @param[in] HeaderAddress The Address of this capability header.
5719 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5722 PrintInterpretedExtendedCompatibilityAri (
5723 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5724 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5727 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
5729 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
5735 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
5736 gShellDebug1HiiHandle
,
5737 Header
->AriCapability
,
5742 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5743 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
5744 (VOID
*)(HeaderAddress
)
5746 return (EFI_SUCCESS
);
5750 Function to interpret and print out the DPA structure
5752 @param[in] HeaderAddress The Address of this capability header.
5753 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5756 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5757 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5758 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5761 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
5764 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
5770 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
5771 gShellDebug1HiiHandle
,
5772 Header
->DpaCapability
,
5773 Header
->DpaLatencyIndicator
,
5777 for (LinkCount
= 0; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header
) + 1; LinkCount
++) {
5782 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
5783 gShellDebug1HiiHandle
,
5785 Header
->DpaPowerAllocationArray
[LinkCount
]
5791 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5792 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX (Header
),
5793 (VOID
*)(HeaderAddress
)
5795 return (EFI_SUCCESS
);
5799 Function to interpret and print out the link declaration structure
5801 @param[in] HeaderAddress The Address of this capability header.
5802 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5805 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5806 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5807 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5810 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
5813 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
5819 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
5820 gShellDebug1HiiHandle
,
5821 Header
->ElementSelfDescription
5824 for (LinkCount
= 0; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header
); LinkCount
++) {
5829 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
5830 gShellDebug1HiiHandle
,
5832 Header
->LinkEntry
[LinkCount
]
5838 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5839 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT (Header
)-1)*sizeof (UINT32
),
5840 (VOID
*)(HeaderAddress
)
5842 return (EFI_SUCCESS
);
5846 Function to interpret and print out the Advanced Error Reporting structure
5848 @param[in] HeaderAddress The Address of this capability header.
5849 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5852 PrintInterpretedExtendedCompatibilityAer (
5853 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5854 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5857 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5859 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5865 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5866 gShellDebug1HiiHandle
,
5867 Header
->UncorrectableErrorStatus
,
5868 Header
->UncorrectableErrorMask
,
5869 Header
->UncorrectableErrorSeverity
,
5870 Header
->CorrectableErrorStatus
,
5871 Header
->CorrectableErrorMask
,
5872 Header
->AdvancedErrorCapabilitiesAndControl
,
5873 Header
->HeaderLog
[0],
5874 Header
->HeaderLog
[1],
5875 Header
->HeaderLog
[2],
5876 Header
->HeaderLog
[3],
5877 Header
->RootErrorCommand
,
5878 Header
->RootErrorStatus
,
5879 Header
->ErrorSourceIdentification
,
5880 Header
->CorrectableErrorSourceIdentification
,
5881 Header
->TlpPrefixLog
[0],
5882 Header
->TlpPrefixLog
[1],
5883 Header
->TlpPrefixLog
[2],
5884 Header
->TlpPrefixLog
[3]
5888 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5889 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5890 (VOID
*)(HeaderAddress
)
5892 return (EFI_SUCCESS
);
5896 Function to interpret and print out the multicast structure
5898 @param[in] HeaderAddress The Address of this capability header.
5899 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5900 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5903 PrintInterpretedExtendedCompatibilityMulticast (
5904 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5905 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5906 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5909 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5911 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5917 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5918 gShellDebug1HiiHandle
,
5919 Header
->MultiCastCapability
,
5920 Header
->MulticastControl
,
5921 Header
->McBaseAddress
,
5922 Header
->McReceiveAddress
,
5924 Header
->McBlockUntranslated
,
5925 Header
->McOverlayBar
5930 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5931 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5932 (VOID
*)(HeaderAddress
)
5935 return (EFI_SUCCESS
);
5939 Function to interpret and print out the virtual channel and multi virtual channel structure
5941 @param[in] HeaderAddress The Address of this capability header.
5942 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5945 PrintInterpretedExtendedCompatibilityVirtualChannel (
5946 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5947 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5950 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5951 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5954 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5960 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5961 gShellDebug1HiiHandle
,
5962 Header
->ExtendedVcCount
,
5963 Header
->PortVcCapability1
,
5964 Header
->PortVcCapability2
,
5965 Header
->VcArbTableOffset
,
5966 Header
->PortVcControl
,
5967 Header
->PortVcStatus
5969 for (ItemCount
= 0; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5970 CapabilityItem
= &Header
->Capability
[ItemCount
];
5975 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5976 gShellDebug1HiiHandle
,
5978 CapabilityItem
->VcResourceCapability
,
5979 CapabilityItem
->PortArbTableOffset
,
5980 CapabilityItem
->VcResourceControl
,
5981 CapabilityItem
->VcResourceStatus
5987 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5988 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
)
5989 + Header
->ExtendedVcCount
* sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
),
5990 (VOID
*)(HeaderAddress
)
5993 return (EFI_SUCCESS
);
5997 Function to interpret and print out the resizeable bar structure
5999 @param[in] HeaderAddress The Address of this capability header.
6000 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6003 PrintInterpretedExtendedCompatibilityResizeableBar (
6004 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
6005 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
6008 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
6011 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
6013 for (ItemCount
= 0; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS (Header
); ItemCount
++) {
6018 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
6019 gShellDebug1HiiHandle
,
6021 Header
->Capability
[ItemCount
].ResizableBarCapability
.Uint32
,
6022 Header
->Capability
[ItemCount
].ResizableBarControl
.Uint32
6028 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
6029 (UINT32
)GET_NUMBER_RESIZABLE_BARS (Header
) * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
6030 (VOID
*)(HeaderAddress
)
6033 return (EFI_SUCCESS
);
6037 Function to interpret and print out the TPH structure
6039 @param[in] HeaderAddress The Address of this capability header.
6040 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6043 PrintInterpretedExtendedCompatibilityTph (
6044 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
6045 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
6048 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
6050 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
6056 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
6057 gShellDebug1HiiHandle
,
6058 Header
->TphRequesterCapability
,
6059 Header
->TphRequesterControl
6063 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
6064 GET_TPH_TABLE_SIZE (Header
),
6065 (VOID
*)Header
->TphStTable
6070 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
6071 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE (Header
) - sizeof (UINT16
),
6072 (VOID
*)(HeaderAddress
)
6075 return (EFI_SUCCESS
);
6079 Function to interpret and print out the secondary PCIe capability structure
6081 @param[in] HeaderAddress The Address of this capability header.
6082 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6083 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
6086 PrintInterpretedExtendedCompatibilitySecondary (
6087 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
6088 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
6089 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCap
6092 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
6094 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
6100 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
6101 gShellDebug1HiiHandle
,
6102 Header
->LinkControl3
.Uint32
,
6103 Header
->LaneErrorStatus
6107 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
6108 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
6109 (VOID
*)Header
->EqualizationControl
6114 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
6115 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
) - sizeof (Header
->EqualizationControl
)
6116 + PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
6117 (VOID
*)(HeaderAddress
)
6120 return (EFI_SUCCESS
);
6124 Display Pcie extended capability details
6126 @param[in] HeadersBaseAddress The address of all the extended capability headers.
6127 @param[in] HeaderAddress The address of this capability header.
6128 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
6131 PrintPciExtendedCapabilityDetails (
6132 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
6133 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
6134 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
6137 switch (HeaderAddress
->CapabilityId
) {
6138 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
6139 return PrintInterpretedExtendedCompatibilityAer (HeaderAddress
, HeadersBaseAddress
);
6140 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
6141 return PrintInterpretedExtendedCompatibilityLinkControl (HeaderAddress
, HeadersBaseAddress
);
6142 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
6143 return PrintInterpretedExtendedCompatibilityLinkDeclaration (HeaderAddress
, HeadersBaseAddress
);
6144 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
6145 return PrintInterpretedExtendedCompatibilitySerialNumber (HeaderAddress
, HeadersBaseAddress
);
6146 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
6147 return PrintInterpretedExtendedCompatibilityPowerBudgeting (HeaderAddress
, HeadersBaseAddress
);
6148 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
6149 return PrintInterpretedExtendedCompatibilityAcs (HeaderAddress
, HeadersBaseAddress
);
6150 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
6151 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (HeaderAddress
, HeadersBaseAddress
);
6152 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
6153 return PrintInterpretedExtendedCompatibilityAri (HeaderAddress
, HeadersBaseAddress
);
6154 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
6155 return PrintInterpretedExtendedCompatibilityRcrb (HeaderAddress
, HeadersBaseAddress
);
6156 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
6157 return PrintInterpretedExtendedCompatibilityVendorSpecific (HeaderAddress
, HeadersBaseAddress
);
6158 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
6159 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (HeaderAddress
, HeadersBaseAddress
);
6160 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
6161 return PrintInterpretedExtendedCompatibilityECEA (HeaderAddress
, HeadersBaseAddress
);
6162 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
6163 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
6164 return PrintInterpretedExtendedCompatibilityVirtualChannel (HeaderAddress
, HeadersBaseAddress
);
6165 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
6167 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
6169 return PrintInterpretedExtendedCompatibilityMulticast (HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
6170 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
6171 return PrintInterpretedExtendedCompatibilityResizeableBar (HeaderAddress
, HeadersBaseAddress
);
6172 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
6173 return PrintInterpretedExtendedCompatibilityTph (HeaderAddress
, HeadersBaseAddress
);
6174 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
6175 return PrintInterpretedExtendedCompatibilitySecondary (HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
6180 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
6181 HeaderAddress
->CapabilityId
6188 Display Pcie device structure.
6190 @param[in] PciExpressCap PCI Express capability buffer.
6191 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
6192 @param[in] ExtendedConfigSize PCI Express extended configuration size.
6193 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
6196 PciExplainPciExpress (
6197 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
,
6198 IN UINT8
*ExtendedConfigSpace
,
6199 IN UINTN ExtendedConfigSize
,
6200 IN CONST UINT16 ExtendedCapability
6203 UINT8 DevicePortType
;
6207 PCI_EXP_EXT_HDR
*ExtHdr
;
6209 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
6211 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
6213 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
6214 if (ShellGetExecutionBreakFlag ()) {
6218 RegAddr
= (UINT8
*)PciExpressCap
+ PcieExplainList
[Index
].Offset
;
6219 switch (PcieExplainList
[Index
].Width
) {
6220 case FieldWidthUINT8
:
6221 RegValue
= *(UINT8
*)RegAddr
;
6223 case FieldWidthUINT16
:
6224 RegValue
= *(UINT16
*)RegAddr
;
6226 case FieldWidthUINT32
:
6227 RegValue
= *(UINT32
*)RegAddr
;
6238 PcieExplainList
[Index
].Token
,
6239 gShellDebug1HiiHandle
,
6240 PcieExplainList
[Index
].Offset
,
6243 if (PcieExplainList
[Index
].Func
== NULL
) {
6247 switch (PcieExplainList
[Index
].Type
) {
6248 case PcieExplainTypeLink
:
6250 // Link registers should not be used by
6251 // a) Root Complex Integrated Endpoint
6252 // b) Root Complex Event Collector
6254 if ((DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT
) ||
6255 (DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR
))
6261 case PcieExplainTypeSlot
:
6263 // Slot registers are only valid for
6264 // a) Root Port of PCI Express Root Complex
6265 // b) Downstream Port of PCI Express Switch
6266 // and when SlotImplemented bit is set in PCIE cap register.
6268 if (((DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
) &&
6269 (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
)) ||
6270 !PciExpressCap
->Capability
.Bits
.SlotImplemented
)
6276 case PcieExplainTypeRoot
:
6278 // Root registers are only valid for
6279 // Root Port of PCI Express Root Complex
6281 if (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
) {
6290 PcieExplainList
[Index
].Func (PciExpressCap
);
6293 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExtendedConfigSpace
;
6294 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0 && ExtHdr
->CapabilityId
!= 0xFFFF) {
6296 // Process this item
6298 if ((ExtendedCapability
== 0xFFFF) || (ExtendedCapability
== ExtHdr
->CapabilityId
)) {
6302 PrintPciExtendedCapabilityDetails ((PCI_EXP_EXT_HDR
*)ExtendedConfigSpace
, ExtHdr
, PciExpressCap
);
6306 // Advance to the next item if it exists
6308 if ((ExtHdr
->NextCapabilityOffset
!= 0) &&
6309 (ExtHdr
->NextCapabilityOffset
<= (UINT32
)(ExtendedConfigSize
+ EFI_PCIE_CAPABILITY_BASE_OFFSET
- sizeof (PCI_EXP_EXT_HDR
))))
6311 ExtHdr
= (PCI_EXP_EXT_HDR
*)(ExtendedConfigSpace
+ ExtHdr
->NextCapabilityOffset
- EFI_PCIE_CAPABILITY_BASE_OFFSET
);