UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
[mirror_edk2.git] / UefiCpuPkg / CpuDxe / CpuPageTable.c
1 /** @file
2 Page table management support.
3
4 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include <Base.h>
18 #include <Uefi.h>
19 #include <Library/BaseLib.h>
20 #include <Library/CpuLib.h>
21 #include <Library/BaseMemoryLib.h>
22 #include <Library/MemoryAllocationLib.h>
23 #include <Library/DebugLib.h>
24 #include <Library/UefiBootServicesTableLib.h>
25 #include <Protocol/MpService.h>
26 #include "CpuPageTable.h"
27
28 ///
29 /// Page Table Entry
30 ///
31 #define IA32_PG_P BIT0
32 #define IA32_PG_RW BIT1
33 #define IA32_PG_U BIT2
34 #define IA32_PG_WT BIT3
35 #define IA32_PG_CD BIT4
36 #define IA32_PG_A BIT5
37 #define IA32_PG_D BIT6
38 #define IA32_PG_PS BIT7
39 #define IA32_PG_PAT_2M BIT12
40 #define IA32_PG_PAT_4K IA32_PG_PS
41 #define IA32_PG_PMNT BIT62
42 #define IA32_PG_NX BIT63
43
44 #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)
45 //
46 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
47 // X64 PAE PDPTE does not have such restriction
48 //
49 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)
50
51 #define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)
52
53 #define PAGING_4K_MASK 0xFFF
54 #define PAGING_2M_MASK 0x1FFFFF
55 #define PAGING_1G_MASK 0x3FFFFFFF
56
57 #define PAGING_PAE_INDEX_MASK 0x1FF
58
59 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
60 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
61 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
62
63 typedef enum {
64 PageNone,
65 Page4K,
66 Page2M,
67 Page1G,
68 } PAGE_ATTRIBUTE;
69
70 typedef struct {
71 PAGE_ATTRIBUTE Attribute;
72 UINT64 Length;
73 UINT64 AddressMask;
74 } PAGE_ATTRIBUTE_TABLE;
75
76 typedef enum {
77 PageActionAssign,
78 PageActionSet,
79 PageActionClear,
80 } PAGE_ACTION;
81
82 PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
83 {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},
84 {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},
85 {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
86 };
87
88 /**
89 Enable write protection function for AP.
90
91 @param[in,out] Buffer The pointer to private data buffer.
92 **/
93 VOID
94 EFIAPI
95 SyncCpuEnableWriteProtection (
96 IN OUT VOID *Buffer
97 )
98 {
99 AsmWriteCr0 (AsmReadCr0 () | BIT16);
100 }
101
102 /**
103 CpuFlushTlb function for AP.
104
105 @param[in,out] Buffer The pointer to private data buffer.
106 **/
107 VOID
108 EFIAPI
109 SyncCpuFlushTlb (
110 IN OUT VOID *Buffer
111 )
112 {
113 CpuFlushTlb();
114 }
115
116 /**
117 Sync memory page attributes for AP.
118
119 @param[in] Procedure A pointer to the function to be run on enabled APs of
120 the system.
121 **/
122 VOID
123 SyncMemoryPageAttributesAp (
124 IN EFI_AP_PROCEDURE Procedure
125 )
126 {
127 EFI_STATUS Status;
128 EFI_MP_SERVICES_PROTOCOL *MpService;
129
130 Status = gBS->LocateProtocol (
131 &gEfiMpServiceProtocolGuid,
132 NULL,
133 (VOID **)&MpService
134 );
135 //
136 // Synchronize the update with all APs
137 //
138 if (!EFI_ERROR (Status)) {
139 Status = MpService->StartupAllAPs (
140 MpService, // This
141 Procedure, // Procedure
142 FALSE, // SingleThread
143 NULL, // WaitEvent
144 0, // TimeoutInMicrosecsond
145 NULL, // ProcedureArgument
146 NULL // FailedCpuList
147 );
148 ASSERT (Status == EFI_SUCCESS || Status == EFI_NOT_STARTED || Status == EFI_NOT_READY);
149 }
150 }
151
152 /**
153 Return current paging context.
154
155 @param[in,out] PagingContext The paging context.
156 **/
157 VOID
158 GetCurrentPagingContext (
159 IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext
160 )
161 {
162 UINT32 RegEax;
163 UINT32 RegEdx;
164
165 ZeroMem(PagingContext, sizeof(*PagingContext));
166 if (sizeof(UINTN) == sizeof(UINT64)) {
167 PagingContext->MachineType = IMAGE_FILE_MACHINE_X64;
168 } else {
169 PagingContext->MachineType = IMAGE_FILE_MACHINE_I386;
170 }
171 if ((AsmReadCr0 () & BIT31) != 0) {
172 PagingContext->ContextData.X64.PageTableBase = (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
173 if ((AsmReadCr0 () & BIT16) == 0) {
174 AsmWriteCr0 (AsmReadCr0 () | BIT16);
175 SyncMemoryPageAttributesAp (SyncCpuEnableWriteProtection);
176 }
177 } else {
178 PagingContext->ContextData.X64.PageTableBase = 0;
179 }
180
181 if ((AsmReadCr4 () & BIT4) != 0) {
182 PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;
183 }
184 if ((AsmReadCr4 () & BIT5) != 0) {
185 PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;
186 }
187 if ((AsmReadCr0 () & BIT16) != 0) {
188 PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
189 }
190
191 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
192 if (RegEax > 0x80000000) {
193 AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
194 if ((RegEdx & BIT20) != 0) {
195 // XD supported
196 if ((AsmReadMsr64 (0x000001A0) & BIT34) == 0) {
197 // XD enabled
198 if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
199 // XD activated
200 PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
201 }
202 }
203 }
204 if ((RegEdx & BIT26) != 0) {
205 PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SUPPORT;
206 }
207 }
208 }
209
210 /**
211 Return length according to page attributes.
212
213 @param[in] PageAttributes The page attribute of the page entry.
214
215 @return The length of page entry.
216 **/
217 UINTN
218 PageAttributeToLength (
219 IN PAGE_ATTRIBUTE PageAttribute
220 )
221 {
222 UINTN Index;
223 for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
224 if (PageAttribute == mPageAttributeTable[Index].Attribute) {
225 return (UINTN)mPageAttributeTable[Index].Length;
226 }
227 }
228 return 0;
229 }
230
231 /**
232 Return address mask according to page attributes.
233
234 @param[in] PageAttributes The page attribute of the page entry.
235
236 @return The address mask of page entry.
237 **/
238 UINTN
239 PageAttributeToMask (
240 IN PAGE_ATTRIBUTE PageAttribute
241 )
242 {
243 UINTN Index;
244 for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
245 if (PageAttribute == mPageAttributeTable[Index].Attribute) {
246 return (UINTN)mPageAttributeTable[Index].AddressMask;
247 }
248 }
249 return 0;
250 }
251
252 /**
253 Return page table entry to match the address.
254
255 @param[in] PagingContext The paging context.
256 @param[in] Address The address to be checked.
257 @param[out] PageAttributes The page attribute of the page entry.
258
259 @return The page entry.
260 **/
261 VOID *
262 GetPageTableEntry (
263 IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext,
264 IN PHYSICAL_ADDRESS Address,
265 OUT PAGE_ATTRIBUTE *PageAttribute
266 )
267 {
268 UINTN Index1;
269 UINTN Index2;
270 UINTN Index3;
271 UINTN Index4;
272 UINT64 *L1PageTable;
273 UINT64 *L2PageTable;
274 UINT64 *L3PageTable;
275 UINT64 *L4PageTable;
276 UINT64 AddressEncMask;
277
278 ASSERT (PagingContext != NULL);
279
280 Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;
281 Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;
282 Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
283 Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
284
285 // Make sure AddressEncMask is contained to smallest supported address field.
286 //
287 AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
288
289 if (PagingContext->MachineType == IMAGE_FILE_MACHINE_X64) {
290 L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
291 if (L4PageTable[Index4] == 0) {
292 *PageAttribute = PageNone;
293 return NULL;
294 }
295
296 L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);
297 } else {
298 ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);
299 L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;
300 }
301 if (L3PageTable[Index3] == 0) {
302 *PageAttribute = PageNone;
303 return NULL;
304 }
305 if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
306 // 1G
307 *PageAttribute = Page1G;
308 return &L3PageTable[Index3];
309 }
310
311 L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);
312 if (L2PageTable[Index2] == 0) {
313 *PageAttribute = PageNone;
314 return NULL;
315 }
316 if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
317 // 2M
318 *PageAttribute = Page2M;
319 return &L2PageTable[Index2];
320 }
321
322 // 4k
323 L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);
324 if ((L1PageTable[Index1] == 0) && (Address != 0)) {
325 *PageAttribute = PageNone;
326 return NULL;
327 }
328 *PageAttribute = Page4K;
329 return &L1PageTable[Index1];
330 }
331
332 /**
333 Return memory attributes of page entry.
334
335 @param[in] PageEntry The page entry.
336
337 @return Memory attributes of page entry.
338 **/
339 UINT64
340 GetAttributesFromPageEntry (
341 IN UINT64 *PageEntry
342 )
343 {
344 UINT64 Attributes;
345 Attributes = 0;
346 if ((*PageEntry & IA32_PG_P) == 0) {
347 Attributes |= EFI_MEMORY_RP;
348 }
349 if ((*PageEntry & IA32_PG_RW) == 0) {
350 Attributes |= EFI_MEMORY_RO;
351 }
352 if ((*PageEntry & IA32_PG_NX) != 0) {
353 Attributes |= EFI_MEMORY_XP;
354 }
355 return Attributes;
356 }
357
358 /**
359 Modify memory attributes of page entry.
360
361 @param[in] PagingContext The paging context.
362 @param[in] PageEntry The page entry.
363 @param[in] Attributes The bit mask of attributes to modify for the memory region.
364 @param[in] PageAction The page action.
365 @param[out] IsModified TRUE means page table modified. FALSE means page table not modified.
366 **/
367 VOID
368 ConvertPageEntryAttribute (
369 IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext,
370 IN UINT64 *PageEntry,
371 IN UINT64 Attributes,
372 IN PAGE_ACTION PageAction,
373 OUT BOOLEAN *IsModified
374 )
375 {
376 UINT64 CurrentPageEntry;
377 UINT64 NewPageEntry;
378
379 CurrentPageEntry = *PageEntry;
380 NewPageEntry = CurrentPageEntry;
381 if ((Attributes & EFI_MEMORY_RP) != 0) {
382 switch (PageAction) {
383 case PageActionAssign:
384 case PageActionSet:
385 NewPageEntry &= ~(UINT64)IA32_PG_P;
386 break;
387 case PageActionClear:
388 NewPageEntry |= IA32_PG_P;
389 break;
390 }
391 } else {
392 switch (PageAction) {
393 case PageActionAssign:
394 NewPageEntry |= IA32_PG_P;
395 break;
396 case PageActionSet:
397 case PageActionClear:
398 break;
399 }
400 }
401 if ((Attributes & EFI_MEMORY_RO) != 0) {
402 switch (PageAction) {
403 case PageActionAssign:
404 case PageActionSet:
405 NewPageEntry &= ~(UINT64)IA32_PG_RW;
406 break;
407 case PageActionClear:
408 NewPageEntry |= IA32_PG_RW;
409 break;
410 }
411 } else {
412 switch (PageAction) {
413 case PageActionAssign:
414 NewPageEntry |= IA32_PG_RW;
415 break;
416 case PageActionSet:
417 case PageActionClear:
418 break;
419 }
420 }
421 if ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED) != 0) {
422 if ((Attributes & EFI_MEMORY_XP) != 0) {
423 switch (PageAction) {
424 case PageActionAssign:
425 case PageActionSet:
426 NewPageEntry |= IA32_PG_NX;
427 break;
428 case PageActionClear:
429 NewPageEntry &= ~IA32_PG_NX;
430 break;
431 }
432 } else {
433 switch (PageAction) {
434 case PageActionAssign:
435 NewPageEntry &= ~IA32_PG_NX;
436 break;
437 case PageActionSet:
438 case PageActionClear:
439 break;
440 }
441 }
442 }
443 *PageEntry = NewPageEntry;
444 if (CurrentPageEntry != NewPageEntry) {
445 *IsModified = TRUE;
446 DEBUG ((DEBUG_INFO, "ConvertPageEntryAttribute 0x%lx", CurrentPageEntry));
447 DEBUG ((DEBUG_INFO, "->0x%lx\n", NewPageEntry));
448 } else {
449 *IsModified = FALSE;
450 }
451 }
452
453 /**
454 This function returns if there is need to split page entry.
455
456 @param[in] BaseAddress The base address to be checked.
457 @param[in] Length The length to be checked.
458 @param[in] PageEntry The page entry to be checked.
459 @param[in] PageAttribute The page attribute of the page entry.
460
461 @retval SplitAttributes on if there is need to split page entry.
462 **/
463 PAGE_ATTRIBUTE
464 NeedSplitPage (
465 IN PHYSICAL_ADDRESS BaseAddress,
466 IN UINT64 Length,
467 IN UINT64 *PageEntry,
468 IN PAGE_ATTRIBUTE PageAttribute
469 )
470 {
471 UINT64 PageEntryLength;
472
473 PageEntryLength = PageAttributeToLength (PageAttribute);
474
475 if (((BaseAddress & (PageEntryLength - 1)) == 0) && (Length >= PageEntryLength)) {
476 return PageNone;
477 }
478
479 if (((BaseAddress & PAGING_2M_MASK) != 0) || (Length < SIZE_2MB)) {
480 return Page4K;
481 }
482
483 return Page2M;
484 }
485
486 /**
487 This function splits one page entry to small page entries.
488
489 @param[in] PageEntry The page entry to be splitted.
490 @param[in] PageAttribute The page attribute of the page entry.
491 @param[in] SplitAttribute How to split the page entry.
492 @param[in] AllocatePagesFunc If page split is needed, this function is used to allocate more pages.
493
494 @retval RETURN_SUCCESS The page entry is splitted.
495 @retval RETURN_UNSUPPORTED The page entry does not support to be splitted.
496 @retval RETURN_OUT_OF_RESOURCES No resource to split page entry.
497 **/
498 RETURN_STATUS
499 SplitPage (
500 IN UINT64 *PageEntry,
501 IN PAGE_ATTRIBUTE PageAttribute,
502 IN PAGE_ATTRIBUTE SplitAttribute,
503 IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc
504 )
505 {
506 UINT64 BaseAddress;
507 UINT64 *NewPageEntry;
508 UINTN Index;
509 UINT64 AddressEncMask;
510
511 ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);
512
513 ASSERT (AllocatePagesFunc != NULL);
514
515 // Make sure AddressEncMask is contained to smallest supported address field.
516 //
517 AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
518
519 if (PageAttribute == Page2M) {
520 //
521 // Split 2M to 4K
522 //
523 ASSERT (SplitAttribute == Page4K);
524 if (SplitAttribute == Page4K) {
525 NewPageEntry = AllocatePagesFunc (1);
526 DEBUG ((DEBUG_INFO, "Split - 0x%x\n", NewPageEntry));
527 if (NewPageEntry == NULL) {
528 return RETURN_OUT_OF_RESOURCES;
529 }
530 BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64;
531 for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
532 NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
533 }
534 (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
535 return RETURN_SUCCESS;
536 } else {
537 return RETURN_UNSUPPORTED;
538 }
539 } else if (PageAttribute == Page1G) {
540 //
541 // Split 1G to 2M
542 // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
543 //
544 ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
545 if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {
546 NewPageEntry = AllocatePagesFunc (1);
547 DEBUG ((DEBUG_INFO, "Split - 0x%x\n", NewPageEntry));
548 if (NewPageEntry == NULL) {
549 return RETURN_OUT_OF_RESOURCES;
550 }
551 BaseAddress = *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MASK_64;
552 for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
553 NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
554 }
555 (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
556 return RETURN_SUCCESS;
557 } else {
558 return RETURN_UNSUPPORTED;
559 }
560 } else {
561 return RETURN_UNSUPPORTED;
562 }
563 }
564
565 /**
566 This function modifies the page attributes for the memory region specified by BaseAddress and
567 Length from their current attributes to the attributes specified by Attributes.
568
569 Caller should make sure BaseAddress and Length is at page boundary.
570
571 @param[in] PagingContext The paging context. NULL means get page table from current CPU context.
572 @param[in] BaseAddress The physical address that is the start address of a memory region.
573 @param[in] Length The size in bytes of the memory region.
574 @param[in] Attributes The bit mask of attributes to modify for the memory region.
575 @param[in] PageAction The page action.
576 @param[in] AllocatePagesFunc If page split is needed, this function is used to allocate more pages.
577 NULL mean page split is unsupported.
578 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.
579 @param[out] IsModified TRUE means page table modified. FALSE means page table not modified.
580
581 @retval RETURN_SUCCESS The attributes were modified for the memory region.
582 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by
583 BaseAddress and Length cannot be modified.
584 @retval RETURN_INVALID_PARAMETER Length is zero.
585 Attributes specified an illegal combination of attributes that
586 cannot be set together.
587 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
588 the memory resource range.
589 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the memory
590 resource range specified by BaseAddress and Length.
591 The bit mask of attributes is not support for the memory resource
592 range specified by BaseAddress and Length.
593 **/
594 RETURN_STATUS
595 ConvertMemoryPageAttributes (
596 IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL,
597 IN PHYSICAL_ADDRESS BaseAddress,
598 IN UINT64 Length,
599 IN UINT64 Attributes,
600 IN PAGE_ACTION PageAction,
601 IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL,
602 OUT BOOLEAN *IsSplitted, OPTIONAL
603 OUT BOOLEAN *IsModified OPTIONAL
604 )
605 {
606 PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext;
607 UINT64 *PageEntry;
608 PAGE_ATTRIBUTE PageAttribute;
609 UINTN PageEntryLength;
610 PAGE_ATTRIBUTE SplitAttribute;
611 RETURN_STATUS Status;
612 BOOLEAN IsEntryModified;
613
614 if ((BaseAddress & (SIZE_4KB - 1)) != 0) {
615 DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress));
616 return EFI_UNSUPPORTED;
617 }
618 if ((Length & (SIZE_4KB - 1)) != 0) {
619 DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length));
620 return EFI_UNSUPPORTED;
621 }
622 if (Length == 0) {
623 DEBUG ((DEBUG_ERROR, "Length is 0!\n"));
624 return RETURN_INVALID_PARAMETER;
625 }
626
627 if ((Attributes & ~(EFI_MEMORY_RP | EFI_MEMORY_RO | EFI_MEMORY_XP)) != 0) {
628 DEBUG ((DEBUG_ERROR, "Attributes(0x%lx) has unsupported bit\n", Attributes));
629 return EFI_UNSUPPORTED;
630 }
631
632 if (PagingContext == NULL) {
633 GetCurrentPagingContext (&CurrentPagingContext);
634 } else {
635 CopyMem (&CurrentPagingContext, PagingContext, sizeof(CurrentPagingContext));
636 }
637 switch(CurrentPagingContext.MachineType) {
638 case IMAGE_FILE_MACHINE_I386:
639 if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {
640 DEBUG ((DEBUG_ERROR, "PageTable is 0!\n"));
641 if (Attributes == 0) {
642 return EFI_SUCCESS;
643 } else {
644 return EFI_UNSUPPORTED;
645 }
646 }
647 if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) {
648 DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n"));
649 return EFI_UNSUPPORTED;
650 }
651 break;
652 case IMAGE_FILE_MACHINE_X64:
653 ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0);
654 break;
655 default:
656 ASSERT(FALSE);
657 return EFI_UNSUPPORTED;
658 break;
659 }
660
661 // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));
662
663 if (IsSplitted != NULL) {
664 *IsSplitted = FALSE;
665 }
666 if (IsModified != NULL) {
667 *IsModified = FALSE;
668 }
669
670 //
671 // Below logic is to check 2M/4K page to make sure we donot waist memory.
672 //
673 while (Length != 0) {
674 PageEntry = GetPageTableEntry (&CurrentPagingContext, BaseAddress, &PageAttribute);
675 if (PageEntry == NULL) {
676 return RETURN_UNSUPPORTED;
677 }
678 PageEntryLength = PageAttributeToLength (PageAttribute);
679 SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
680 if (SplitAttribute == PageNone) {
681 ConvertPageEntryAttribute (&CurrentPagingContext, PageEntry, Attributes, PageAction, &IsEntryModified);
682 if (IsEntryModified) {
683 if (IsModified != NULL) {
684 *IsModified = TRUE;
685 }
686 }
687 //
688 // Convert success, move to next
689 //
690 BaseAddress += PageEntryLength;
691 Length -= PageEntryLength;
692 } else {
693 if (AllocatePagesFunc == NULL) {
694 return RETURN_UNSUPPORTED;
695 }
696 Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc);
697 if (RETURN_ERROR (Status)) {
698 return RETURN_UNSUPPORTED;
699 }
700 if (IsSplitted != NULL) {
701 *IsSplitted = TRUE;
702 }
703 if (IsModified != NULL) {
704 *IsModified = TRUE;
705 }
706 //
707 // Just split current page
708 // Convert success in next around
709 //
710 }
711 }
712
713 return RETURN_SUCCESS;
714 }
715
716 /**
717 This function assigns the page attributes for the memory region specified by BaseAddress and
718 Length from their current attributes to the attributes specified by Attributes.
719
720 Caller should make sure BaseAddress and Length is at page boundary.
721
722 Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.
723
724 @param[in] PagingContext The paging context. NULL means get page table from current CPU context.
725 @param[in] BaseAddress The physical address that is the start address of a memory region.
726 @param[in] Length The size in bytes of the memory region.
727 @param[in] Attributes The bit mask of attributes to set for the memory region.
728 @param[in] AllocatePagesFunc If page split is needed, this function is used to allocate more pages.
729 NULL mean page split is unsupported.
730
731 @retval RETURN_SUCCESS The attributes were cleared for the memory region.
732 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by
733 BaseAddress and Length cannot be modified.
734 @retval RETURN_INVALID_PARAMETER Length is zero.
735 Attributes specified an illegal combination of attributes that
736 cannot be set together.
737 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
738 the memory resource range.
739 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the memory
740 resource range specified by BaseAddress and Length.
741 The bit mask of attributes is not support for the memory resource
742 range specified by BaseAddress and Length.
743 **/
744 RETURN_STATUS
745 EFIAPI
746 AssignMemoryPageAttributes (
747 IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL,
748 IN PHYSICAL_ADDRESS BaseAddress,
749 IN UINT64 Length,
750 IN UINT64 Attributes,
751 IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL
752 )
753 {
754 RETURN_STATUS Status;
755 BOOLEAN IsModified;
756 BOOLEAN IsSplitted;
757
758 // DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes));
759 Status = ConvertMemoryPageAttributes (PagingContext, BaseAddress, Length, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModified);
760 if (!EFI_ERROR(Status)) {
761 if ((PagingContext == NULL) && IsModified) {
762 //
763 // Flush TLB as last step
764 //
765 CpuFlushTlb();
766 SyncMemoryPageAttributesAp (SyncCpuFlushTlb);
767 }
768 }
769
770 return Status;
771 }
772
773 /**
774 Initialize the Page Table lib.
775 **/
776 VOID
777 InitializePageTableLib (
778 VOID
779 )
780 {
781 PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext;
782
783 GetCurrentPagingContext (&CurrentPagingContext);
784 DEBUG ((DEBUG_INFO, "CurrentPagingContext:\n", CurrentPagingContext.MachineType));
785 DEBUG ((DEBUG_INFO, " MachineType - 0x%x\n", CurrentPagingContext.MachineType));
786 DEBUG ((DEBUG_INFO, " PageTableBase - 0x%x\n", CurrentPagingContext.ContextData.X64.PageTableBase));
787 DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", CurrentPagingContext.ContextData.X64.Attributes));
788
789 return ;
790 }
791