BaseTools: Update sign tool to make MonotonicCount *after* Payload
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Cpuid.h
1 /** @file
2 CPUID leaf definitions.
3
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
8
9 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials are licensed and made available under
11 the terms and conditions of the BSD License which accompanies this distribution.
12 The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
20 December 2015, CPUID instruction.
21
22 **/
23
24 #ifndef __CPUID_H__
25 #define __CPUID_H__
26
27 /**
28 CPUID Signature Information
29
30 @param EAX CPUID_SIGNATURE (0x00)
31
32 @retval EAX Returns the highest value the CPUID instruction recognizes for
33 returning basic processor information. The value is returned is
34 processor specific.
35 @retval EBX First 4 characters of a vendor identification string.
36 @retval ECX Last 4 characters of a vendor identification string.
37 @retval EDX Middle 4 characters of a vendor identification string.
38
39 <b>Example usage</b>
40 @code
41 UINT32 Eax;
42 UINT32 Ebx;
43 UINT32 Ecx;
44 UINT32 Edx;
45
46 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
47 @endcode
48 **/
49 #define CPUID_SIGNATURE 0x00
50
51 ///
52 /// @{ CPUID signature values returned by Intel processors
53 ///
54 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
55 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
56 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
57 ///
58 /// @}
59 ///
60
61
62 /**
63 CPUID Version Information
64
65 @param EAX CPUID_VERSION_INFO (0x01)
66
67 @retval EAX Returns Model, Family, Stepping Information described by the
68 type CPUID_VERSION_INFO_EAX.
69 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
70 the type CPUID_VERSION_INFO_EBX.
71 @retval ECX CPU Feature Information described by the type
72 CPUID_VERSION_INFO_ECX.
73 @retval EDX CPU Feature Information described by the type
74 CPUID_VERSION_INFO_EDX.
75
76 <b>Example usage</b>
77 @code
78 CPUID_VERSION_INFO_EAX Eax;
79 CPUID_VERSION_INFO_EBX Ebx;
80 CPUID_VERSION_INFO_ECX Ecx;
81 CPUID_VERSION_INFO_EDX Edx;
82
83 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
84 @endcode
85 **/
86 #define CPUID_VERSION_INFO 0x01
87
88 /**
89 CPUID Version Information returned in EAX for CPUID leaf
90 #CPUID_VERSION_INFO.
91 **/
92 typedef union {
93 ///
94 /// Individual bit fields
95 ///
96 struct {
97 UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID
98 UINT32 Model:4; ///< [Bits 7:4] Model
99 UINT32 FamilyId:4; ///< [Bits 11:8] Family
100 UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type
101 UINT32 Reserved1:2; ///< [Bits 15:14] Reserved
102 UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID
103 UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID
104 UINT32 Reserved2:4; ///< Reserved
105 } Bits;
106 ///
107 /// All bit fields as a 32-bit value
108 ///
109 UINT32 Uint32;
110 } CPUID_VERSION_INFO_EAX;
111
112 ///
113 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
114 ///
115 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
116 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
117 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
118 ///
119 /// @}
120 ///
121
122 /**
123 CPUID Version Information returned in EBX for CPUID leaf
124 #CPUID_VERSION_INFO.
125 **/
126 typedef union {
127 ///
128 /// Individual bit fields
129 ///
130 struct {
131 ///
132 /// [Bits 7:0] Provides an entry into a brand string table that contains
133 /// brand strings for IA-32 processors.
134 ///
135 UINT32 BrandIndex:8;
136 ///
137 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
138 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
139 /// introduced in the Pentium 4 processor.
140 ///
141 UINT32 CacheLineSize:8;
142 ///
143 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
144 /// in this physical package.
145 ///
146 /// @note
147 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
148 /// the number of unique initial APICIDs reserved for addressing different
149 /// logical processors in a physical package. This field is only valid if
150 /// CPUID.1.EDX.HTT[bit 28]= 1.
151 ///
152 UINT32 MaximumAddressableIdsForLogicalProcessors:8;
153 ///
154 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
155 /// processor during power up. This field was introduced in the Pentium 4
156 /// processor.
157 ///
158 UINT32 InitialLocalApicId:8;
159 } Bits;
160 ///
161 /// All bit fields as a 32-bit value
162 ///
163 UINT32 Uint32;
164 } CPUID_VERSION_INFO_EBX;
165
166 /**
167 CPUID Version Information returned in ECX for CPUID leaf
168 #CPUID_VERSION_INFO.
169 **/
170 typedef union {
171 ///
172 /// Individual bit fields
173 ///
174 struct {
175 ///
176 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
177 /// processor supports this technology
178 ///
179 UINT32 SSE3:1;
180 ///
181 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
182 /// instruction. Carryless Multiplication
183 ///
184 UINT32 PCLMULQDQ:1;
185 ///
186 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
187 /// DS area using 64-bit layout.
188 ///
189 UINT32 DTES64:1;
190 ///
191 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
192 /// this feature.
193 ///
194 UINT32 MONITOR:1;
195 ///
196 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
197 /// supports the extensions to the Debug Store feature to allow for branch
198 /// message storage qualified by CPL
199 ///
200 UINT32 DS_CPL:1;
201 ///
202 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
203 /// processor supports this technology.
204 ///
205 UINT32 VMX:1;
206 ///
207 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
208 /// supports this technology
209 ///
210 UINT32 SMX:1;
211 ///
212 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
213 /// that the processor supports this technology
214 ///
215 UINT32 EIST:1;
216 ///
217 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
218 /// supports this technology
219 ///
220 UINT32 TM2:1;
221 ///
222 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
223 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
224 /// extensions are not present in the processor.
225 ///
226 UINT32 SSSE3:1;
227 ///
228 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
229 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
230 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
231 /// Bit 24 (L1 Data Cache Context Mode) for details
232 ///
233 UINT32 CNXT_ID:1;
234 ///
235 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
236 /// MSR for silicon debug
237 ///
238 UINT32 SDBG:1;
239 ///
240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
241 /// Add) extensions using YMM state.
242 ///
243 UINT32 FMA:1;
244 ///
245 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
246 /// is available.
247 ///
248 UINT32 CMPXCHG16B:1;
249 ///
250 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
251 /// supports changing IA32_MISC_ENABLE[Bit 23].
252 ///
253 UINT32 xTPR_Update_Control:1;
254 ///
255 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
256 /// processor supports the performance and debug feature indication MSR
257 /// IA32_PERF_CAPABILITIES.
258 ///
259 UINT32 PDCM:1;
260 UINT32 Reserved:1;
261 ///
262 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
263 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
264 ///
265 UINT32 PCID:1;
266 ///
267 /// [Bit 18] A value of 1 indicates the processor supports the ability to
268 /// prefetch data from a memory mapped device. Direct Cache Access.
269 ///
270 UINT32 DCA:1;
271 ///
272 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
273 ///
274 UINT32 SSE4_1:1;
275 ///
276 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
277 ///
278 UINT32 SSE4_2:1;
279 ///
280 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
281 /// feature.
282 ///
283 UINT32 x2APIC:1;
284 ///
285 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
286 /// instruction.
287 ///
288 UINT32 MOVBE:1;
289 ///
290 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
291 /// instruction.
292 ///
293 UINT32 POPCNT:1;
294 ///
295 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
296 /// supports one-shot operation using a TSC deadline value.
297 ///
298 UINT32 TSC_Deadline:1;
299 ///
300 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
301 /// instruction extensions.
302 ///
303 UINT32 AESNI:1;
304 ///
305 /// [Bit 26] A value of 1 indicates that the processor supports the
306 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
307 /// instructions, and XCR0.
308 ///
309 UINT32 XSAVE:1;
310 ///
311 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
312 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
313 /// processor extended state management using XSAVE/XRSTOR.
314 ///
315 UINT32 OSXSAVE:1;
316 ///
317 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
318 /// extensions.
319 ///
320 UINT32 AVX:1;
321 ///
322 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
323 /// floating-point conversion instructions.
324 ///
325 UINT32 F16C:1;
326 ///
327 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
328 ///
329 UINT32 RDRAND:1;
330 ///
331 /// [Bit 31] Always returns 0.
332 ///
333 UINT32 NotUsed:1;
334 } Bits;
335 ///
336 /// All bit fields as a 32-bit value
337 ///
338 UINT32 Uint32;
339 } CPUID_VERSION_INFO_ECX;
340
341 /**
342 CPUID Version Information returned in EDX for CPUID leaf
343 #CPUID_VERSION_INFO.
344 **/
345 typedef union {
346 ///
347 /// Individual bit fields
348 ///
349 struct {
350 ///
351 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
352 ///
353 UINT32 FPU:1;
354 ///
355 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
356 /// including CR4.VME for controlling the feature, CR4.PVI for protected
357 /// mode virtual interrupts, software interrupt indirection, expansion of
358 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
359 /// EFLAGS.VIP flags.
360 ///
361 UINT32 VME:1;
362 ///
363 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
364 /// CR4.DE for controlling the feature, and optional trapping of accesses to
365 /// DR4 and DR5.
366 ///
367 UINT32 DE:1;
368 ///
369 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
370 /// including CR4.PSE for controlling the feature, the defined dirty bit in
371 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
372 /// PDEs, and PTEs.
373 ///
374 UINT32 PSE:1;
375 ///
376 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
377 /// including CR4.TSD for controlling privilege.
378 ///
379 UINT32 TSC:1;
380 ///
381 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
382 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
383 /// implementation dependent.
384 ///
385 UINT32 MSR:1;
386 ///
387 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
388 /// bits are supported: extended page table entry formats, an extra level in
389 /// the page translation tables is defined, 2-MByte pages are supported
390 /// instead of 4 Mbyte pages if PAE bit is 1.
391 ///
392 UINT32 PAE:1;
393 ///
394 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
395 /// Checks, including CR4.MCE for controlling the feature. This feature does
396 /// not define the model-specific implementations of machine-check error
397 /// logging, reporting, and processor shutdowns. Machine Check exception
398 /// handlers may have to depend on processor version to do model specific
399 /// processing of the exception, or test for the presence of the Machine
400 /// Check feature.
401 ///
402 UINT32 MCE:1;
403 ///
404 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
405 /// instruction is supported (implicitly locked and atomic).
406 ///
407 UINT32 CX8:1;
408 ///
409 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
410 /// Interrupt Controller (APIC), responding to memory mapped commands in the
411 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
412 /// processors permit the APIC to be relocated).
413 ///
414 UINT32 APIC:1;
415 UINT32 Reserved1:1;
416 ///
417 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
418 /// and associated MSRs are supported.
419 ///
420 UINT32 SEP:1;
421 ///
422 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
423 /// MSR contains feature bits that describe what memory types are supported,
424 /// how many variable MTRRs are supported, and whether fixed MTRRs are
425 /// supported.
426 ///
427 UINT32 MTRR:1;
428 ///
429 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
430 /// entries that map a page, indicating TLB entries that are common to
431 /// different processes and need not be flushed. The CR4.PGE bit controls
432 /// this feature.
433 ///
434 UINT32 PGE:1;
435 ///
436 /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,
437 /// which provides a compatible mechanism for error reporting in P6 family,
438 /// Pentium 4, Intel Xeon processors, and future processors, is supported.
439 /// The MCG_CAP MSR contains feature bits describing how many banks of error
440 /// reporting MSRs are supported.
441 ///
442 UINT32 MCA:1;
443 ///
444 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
445 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
446 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
447 ///
448 UINT32 CMOV:1;
449 ///
450 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
451 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
452 /// operating system to specify attributes of memory accessed through a
453 /// linear address on a 4KB granularity.
454 ///
455 UINT32 PAT:1;
456 ///
457 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
458 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
459 /// indicates that upper bits of the physical address of a 4-MByte page are
460 /// encoded in bits 20:13 of the page-directory entry. Such physical
461 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
462 ///
463 UINT32 PSE_36:1;
464 ///
465 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
466 /// processor identification number feature and the feature is enabled.
467 ///
468 UINT32 PSN:1;
469 ///
470 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
471 ///
472 UINT32 CLFSH:1;
473 UINT32 Reserved2:1;
474 ///
475 /// [Bit 21] Debug Store. The processor supports the ability to write debug
476 /// information into a memory resident buffer. This feature is used by the
477 /// branch trace store (BTS) and precise event-based sampling (PEBS)
478 /// facilities.
479 ///
480 UINT32 DS:1;
481 ///
482 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
483 /// processor implements internal MSRs that allow processor temperature to
484 /// be monitored and processor performance to be modulated in predefined
485 /// duty cycles under software control.
486 ///
487 UINT32 ACPI:1;
488 ///
489 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
490 /// technology.
491 ///
492 UINT32 MMX:1;
493 ///
494 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
495 /// instructions are supported for fast save and restore of the floating
496 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
497 /// available for an operating system to indicate that it supports the
498 /// FXSAVE and FXRSTOR instructions.
499 ///
500 UINT32 FXSR:1;
501 ///
502 /// [Bit 25] SSE. The processor supports the SSE extensions.
503 ///
504 UINT32 SSE:1;
505 ///
506 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
507 ///
508 UINT32 SSE2:1;
509 ///
510 /// [Bit 27] Self Snoop. The processor supports the management of
511 /// conflicting memory types by performing a snoop of its own cache
512 /// structure for transactions issued to the bus.
513 ///
514 UINT32 SS:1;
515 ///
516 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
517 /// indicates there is only a single logical processor in the package and
518 /// software should assume only a single APIC ID is reserved. A value of 1
519 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
520 /// addressable IDs for logical processors in this package) is valid for the
521 /// package.
522 ///
523 UINT32 HTT:1;
524 ///
525 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
526 /// automatic thermal control circuitry (TCC).
527 ///
528 UINT32 TM:1;
529 UINT32 Reserved3:1;
530 ///
531 /// [Bit 31] Pending Break Enable. The processor supports the use of the
532 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
533 /// asserted) to signal the processor that an interrupt is pending and that
534 /// the processor should return to normal operation to handle the interrupt.
535 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
536 ///
537 UINT32 PBE:1;
538 } Bits;
539 ///
540 /// All bit fields as a 32-bit value
541 ///
542 UINT32 Uint32;
543 } CPUID_VERSION_INFO_EDX;
544
545
546 /**
547 CPUID Cache and TLB Information
548
549 @param EAX CPUID_CACHE_INFO (0x02)
550
551 @retval EAX Cache and TLB Information described by the type
552 CPUID_CACHE_INFO_CACHE_TLB.
553 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
554 0x01 and must be ignored. Only valid if
555 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
556 @retval EBX Cache and TLB Information described by the type
557 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
558 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
559 @retval ECX Cache and TLB Information described by the type
560 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
561 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
562 @retval EDX Cache and TLB Information described by the type
563 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
564 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
565
566 <b>Example usage</b>
567 @code
568 CPUID_CACHE_INFO_CACHE_TLB Eax;
569 CPUID_CACHE_INFO_CACHE_TLB Ebx;
570 CPUID_CACHE_INFO_CACHE_TLB Ecx;
571 CPUID_CACHE_INFO_CACHE_TLB Edx;
572
573 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
574 @endcode
575
576 <b>Cache Descriptor values</b>
577 <table>
578 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
579 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
580 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
581 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
582 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
583 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
584 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
585 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
586 32 byte line size</td></tr>
587 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
588 32 byte line size</td></tr>
589 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
590 64 byte line size</td></tr>
591 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
592 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
593 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
594 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
595 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
596 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
597 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
598 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
599 2 lines per sector</td></tr>
600 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
601 2 lines per sector</td></tr>
602 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
603 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
604 2 lines per sector</td></tr>
605 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
606 2 lines per sector</td></tr>
607 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
608 64 byte line size</td></tr>
609 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
610 64 byte line size</td></tr>
611 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
612 no 3rd-level cache</td></tr>
613 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
614 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
615 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
616 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
617 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
618 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
621 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
622 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
623 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
624 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
625 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
626 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
627 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
628 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
629 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
630 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
631 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
632 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
633 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
634 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
635 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
636 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
637 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
638 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
639 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
640 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
641 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
642 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
643 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>
644 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
645 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
646 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
647 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
648 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
649 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
650 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
651 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
652 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
653 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
654 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
655 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
656 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
657 2 lines per sector</td></tr>
658 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
659 2 lines per sector</td></tr>
660 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
661 2 lines per sector</td></tr>
662 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
663 2 lines per sector</td></tr>
664 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
665 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
666 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
667 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
668 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
669 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
670 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
671 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
672 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
673 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
674 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
675 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
676 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
677 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
678 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
679 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
680 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
681 128 entries</td></tr>
682 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
683 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
684 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
685 1024 entries</td></tr>
686 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
687 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
688 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
689 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
690 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
691 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
692 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
693 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
701 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
702 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
703 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
704 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
705 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
706 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
707 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
708 use CPUID leaf 4 to query cache parameters</td></tr>
709 </table>
710 **/
711 #define CPUID_CACHE_INFO 0x02
712
713 /**
714 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
715 leaf #CPUID_CACHE_INFO.
716 **/
717 typedef union {
718 ///
719 /// Individual bit fields
720 ///
721 struct {
722 UINT32 Reserved:31;
723 ///
724 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
725 /// if 1, then none of the cache descriptor bytes in the register are valid.
726 ///
727 UINT32 NotValid:1;
728 } Bits;
729 ///
730 /// Array of Cache and TLB descriptor bytes
731 ///
732 UINT8 CacheDescriptor[4];
733 ///
734 /// All bit fields as a 32-bit value
735 ///
736 UINT32 Uint32;
737 } CPUID_CACHE_INFO_CACHE_TLB;
738
739
740 /**
741 CPUID Processor Serial Number
742
743 Processor serial number (PSN) is not supported in the Pentium 4 processor
744 or later. On all models, use the PSN flag (returned using CPUID) to check
745 for PSN support before accessing the feature.
746
747 @param EAX CPUID_SERIAL_NUMBER (0x03)
748
749 @retval EAX Reserved.
750 @retval EBX Reserved.
751 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
752 Pentium III processor only; otherwise, the value in this
753 register is reserved.)
754 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
755 Pentium III processor only; otherwise, the value in this
756 register is reserved.)
757
758 <b>Example usage</b>
759 @code
760 UINT32 Ecx;
761 UINT32 Edx;
762
763 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
764 @endcode
765 **/
766 #define CPUID_SERIAL_NUMBER 0x03
767
768
769 /**
770 CPUID Cache Parameters
771
772 @param EAX CPUID_CACHE_PARAMS (0x04)
773 @param ECX Cache Level. Valid values start at 0. Software can enumerate
774 the deterministic cache parameters for each level of the cache
775 hierarchy starting with an index value of 0, until the
776 parameters report the value associated with the CacheType
777 field in CPUID_CACHE_PARAMS_EAX is 0.
778
779 @retval EAX Returns cache type information described by the type
780 CPUID_CACHE_PARAMS_EAX.
781 @retval EBX Returns cache line and associativity information described by
782 the type CPUID_CACHE_PARAMS_EBX.
783 @retval ECX Returns the number of sets in the cache.
784 @retval EDX Returns cache WINVD/INVD behavior described by the type
785 CPUID_CACHE_PARAMS_EDX.
786
787 <b>Example usage</b>
788 @code
789 UINT32 CacheLevel;
790 CPUID_CACHE_PARAMS_EAX Eax;
791 CPUID_CACHE_PARAMS_EBX Ebx;
792 UINT32 Ecx;
793 CPUID_CACHE_PARAMS_EDX Edx;
794
795 CacheLevel = 0;
796 do {
797 AsmCpuidEx (
798 CPUID_CACHE_PARAMS, CacheLevel,
799 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
800 );
801 CacheLevel++;
802 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
803 @endcode
804 **/
805 #define CPUID_CACHE_PARAMS 0x04
806
807 /**
808 CPUID Cache Parameters Information returned in EAX for CPUID leaf
809 #CPUID_CACHE_PARAMS.
810 **/
811 typedef union {
812 ///
813 /// Individual bit fields
814 ///
815 struct {
816 ///
817 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
818 /// then there is no information for the requested cache level.
819 ///
820 UINT32 CacheType:5;
821 ///
822 /// [Bits 7:5] Cache level (Starts at 1).
823 ///
824 UINT32 CacheLevel:3;
825 ///
826 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
827 ///
828 UINT32 SelfInitializingCache:1;
829 ///
830 /// [Bit 9] Fully Associative cache.
831 ///
832 UINT32 FullyAssociativeCache:1;
833 ///
834 /// [Bits 13:10] Reserved.
835 ///
836 UINT32 Reserved:4;
837 ///
838 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
839 /// sharing this cache.
840 ///
841 /// Add one to the return value to get the result.
842 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
843 /// is the number of unique initial APIC IDs reserved for addressing
844 /// different logical processors sharing this cache.
845 ///
846 UINT32 MaximumAddressableIdsForLogicalProcessors:12;
847 ///
848 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
849 /// the physical package.
850 ///
851 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
852 /// is the number of unique Core_IDs reserved for addressing different
853 /// processor cores in a physical package. Core ID is a subset of bits of
854 /// the initial APIC ID.
855 /// The returned value is constant for valid initial values in ECX. Valid
856 /// ECX values start from 0.
857 ///
858 UINT32 MaximumAddressableIdsForProcessorCores:6;
859 } Bits;
860 ///
861 /// All bit fields as a 32-bit value
862 ///
863 UINT32 Uint32;
864 } CPUID_CACHE_PARAMS_EAX;
865
866 ///
867 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
868 ///
869 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
870 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
871 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
872 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
873 ///
874 /// @}
875 ///
876
877 /**
878 CPUID Cache Parameters Information returned in EBX for CPUID leaf
879 #CPUID_CACHE_PARAMS.
880 **/
881 typedef union {
882 ///
883 /// Individual bit fields
884 ///
885 struct {
886 ///
887 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
888 /// get the result.
889 ///
890 UINT32 LineSize:12;
891 ///
892 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
893 /// get the result.
894 ///
895 UINT32 LinePartitions:10;
896 ///
897 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
898 /// the result.
899 ///
900 UINT32 Ways:10;
901 } Bits;
902 ///
903 /// All bit fields as a 32-bit value
904 ///
905 UINT32 Uint32;
906 } CPUID_CACHE_PARAMS_EBX;
907
908 /**
909 CPUID Cache Parameters Information returned in EDX for CPUID leaf
910 #CPUID_CACHE_PARAMS.
911 **/
912 typedef union {
913 ///
914 /// Individual bit fields
915 ///
916 struct {
917 ///
918 /// [Bit 0] Write-Back Invalidate/Invalidate.
919 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
920 /// caches for threads sharing this cache.
921 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
922 /// non-originating threads sharing this cache.
923 ///
924 UINT32 Invalidate:1;
925 ///
926 /// [Bit 1] Cache Inclusiveness.
927 /// 0 = Cache is not inclusive of lower cache levels.
928 /// 1 = Cache is inclusive of lower cache levels.
929 ///
930 UINT32 CacheInclusiveness:1;
931 ///
932 /// [Bit 2] Complex Cache Indexing.
933 /// 0 = Direct mapped cache.
934 /// 1 = A complex function is used to index the cache, potentially using all
935 /// address bits.
936 ///
937 UINT32 ComplexCacheIndexing:1;
938 UINT32 Reserved:29;
939 } Bits;
940 ///
941 /// All bit fields as a 32-bit value
942 ///
943 UINT32 Uint32;
944 } CPUID_CACHE_PARAMS_EDX;
945
946
947 /**
948 CPUID MONITOR/MWAIT Information
949
950 @param EAX CPUID_MONITOR_MWAIT (0x05)
951
952 @retval EAX Smallest monitor-line size in bytes described by the type
953 CPUID_MONITOR_MWAIT_EAX.
954 @retval EBX Largest monitor-line size in bytes described by the type
955 CPUID_MONITOR_MWAIT_EBX.
956 @retval ECX Enumeration of Monitor-Mwait extensions support described by
957 the type CPUID_MONITOR_MWAIT_ECX.
958 @retval EDX Sub C-states supported described by the type
959 CPUID_MONITOR_MWAIT_EDX.
960
961 <b>Example usage</b>
962 @code
963 CPUID_MONITOR_MWAIT_EAX Eax;
964 CPUID_MONITOR_MWAIT_EBX Ebx;
965 CPUID_MONITOR_MWAIT_ECX Ecx;
966 CPUID_MONITOR_MWAIT_EDX Edx;
967
968 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
969 @endcode
970 **/
971 #define CPUID_MONITOR_MWAIT 0x05
972
973 /**
974 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
975 #CPUID_MONITOR_MWAIT.
976 **/
977 typedef union {
978 ///
979 /// Individual bit fields
980 ///
981 struct {
982 ///
983 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
984 /// monitor granularity).
985 ///
986 UINT32 SmallestMonitorLineSize:16;
987 UINT32 Reserved:16;
988 } Bits;
989 ///
990 /// All bit fields as a 32-bit value
991 ///
992 UINT32 Uint32;
993 } CPUID_MONITOR_MWAIT_EAX;
994
995 /**
996 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
997 #CPUID_MONITOR_MWAIT.
998 **/
999 typedef union {
1000 ///
1001 /// Individual bit fields
1002 ///
1003 struct {
1004 ///
1005 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1006 /// monitor granularity).
1007 ///
1008 UINT32 LargestMonitorLineSize:16;
1009 UINT32 Reserved:16;
1010 } Bits;
1011 ///
1012 /// All bit fields as a 32-bit value
1013 ///
1014 UINT32 Uint32;
1015 } CPUID_MONITOR_MWAIT_EBX;
1016
1017 /**
1018 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1019 #CPUID_MONITOR_MWAIT.
1020 **/
1021 typedef union {
1022 ///
1023 /// Individual bit fields
1024 ///
1025 struct {
1026 ///
1027 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1028 /// and EDX are valid.
1029 ///
1030 UINT32 ExtensionsSupported:1;
1031 ///
1032 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1033 /// interrupts disabled.
1034 ///
1035 UINT32 InterruptAsBreak:1;
1036 UINT32 Reserved:30;
1037 } Bits;
1038 ///
1039 /// All bit fields as a 32-bit value
1040 ///
1041 UINT32 Uint32;
1042 } CPUID_MONITOR_MWAIT_ECX;
1043
1044 /**
1045 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1046 #CPUID_MONITOR_MWAIT.
1047
1048 @note
1049 The definition of C0 through C7 states for MWAIT extension are
1050 processor-specific C-states, not ACPI C-states.
1051 **/
1052 typedef union {
1053 ///
1054 /// Individual bit fields
1055 ///
1056 struct {
1057 ///
1058 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1059 ///
1060 UINT32 C0States:4;
1061 ///
1062 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1063 ///
1064 UINT32 C1States:4;
1065 ///
1066 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1067 ///
1068 UINT32 C2States:4;
1069 ///
1070 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1071 ///
1072 UINT32 C3States:4;
1073 ///
1074 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1075 ///
1076 UINT32 C4States:4;
1077 ///
1078 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1079 ///
1080 UINT32 C5States:4;
1081 ///
1082 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1083 ///
1084 UINT32 C6States:4;
1085 ///
1086 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1087 ///
1088 UINT32 C7States:4;
1089 } Bits;
1090 ///
1091 /// All bit fields as a 32-bit value
1092 ///
1093 UINT32 Uint32;
1094 } CPUID_MONITOR_MWAIT_EDX;
1095
1096
1097 /**
1098 CPUID Thermal and Power Management
1099
1100 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1101
1102 @retval EAX Thermal and power management features described by the type
1103 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1104 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1105 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1106 @retval ECX Performance features described by the type
1107 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1108 @retval EDX Reserved.
1109
1110 <b>Example usage</b>
1111 @code
1112 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1113 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1114 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1115
1116 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1117 @endcode
1118 **/
1119 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1120
1121 /**
1122 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1123 #CPUID_THERMAL_POWER_MANAGEMENT.
1124 **/
1125 typedef union {
1126 ///
1127 /// Individual bit fields
1128 ///
1129 struct {
1130 ///
1131 /// [Bit 0] Digital temperature sensor is supported if set.
1132 ///
1133 UINT32 DigitalTemperatureSensor:1;
1134 ///
1135 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1136 ///
1137 UINT32 TurboBoostTechnology:1;
1138 ///
1139 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1140 ///
1141 UINT32 ARAT:1;
1142 UINT32 Reserved1:1;
1143 ///
1144 /// [Bit 4] Power limit notification controls are supported if set.
1145 ///
1146 UINT32 PLN:1;
1147 ///
1148 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1149 ///
1150 UINT32 ECMD:1;
1151 ///
1152 /// [Bit 6] Package thermal management is supported if set.
1153 ///
1154 UINT32 PTM:1;
1155 ///
1156 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1157 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1158 ///
1159 UINT32 HWP:1;
1160 ///
1161 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1162 ///
1163 UINT32 HWP_Notification:1;
1164 ///
1165 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1166 ///
1167 UINT32 HWP_Activity_Window:1;
1168 ///
1169 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1170 ///
1171 UINT32 HWP_Energy_Performance_Preference:1;
1172 ///
1173 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1174 ///
1175 UINT32 HWP_Package_Level_Request:1;
1176 UINT32 Reserved2:1;
1177 ///
1178 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1179 /// IA32_THREAD_STALL MSRs are supported if set.
1180 ///
1181 UINT32 HDC:1;
1182 UINT32 Reserved3:18;
1183 } Bits;
1184 ///
1185 /// All bit fields as a 32-bit value
1186 ///
1187 UINT32 Uint32;
1188 } CPUID_THERMAL_POWER_MANAGEMENT_EAX;
1189
1190 /**
1191 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1192 #CPUID_THERMAL_POWER_MANAGEMENT.
1193 **/
1194 typedef union {
1195 ///
1196 /// Individual bit fields
1197 ///
1198 struct {
1199 ///
1200 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1201 ///
1202 UINT32 InterruptThresholds:4;
1203 UINT32 Reserved:28;
1204 } Bits;
1205 ///
1206 /// All bit fields as a 32-bit value
1207 ///
1208 UINT32 Uint32;
1209 } CPUID_THERMAL_POWER_MANAGEMENT_EBX;
1210
1211 /**
1212 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1213 #CPUID_THERMAL_POWER_MANAGEMENT.
1214 **/
1215 typedef union {
1216 ///
1217 /// Individual bit fields
1218 ///
1219 struct {
1220 ///
1221 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1222 /// and IA32_APERF). The capability to provide a measure of delivered
1223 /// processor performance (since last reset of the counters), as a percentage
1224 /// of the expected processor performance when running at the TSC frequency.
1225 ///
1226 UINT32 HardwareCoordinationFeedback:1;
1227 UINT32 Reserved1:2;
1228 ///
1229 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1230 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1231 /// (1B0H).
1232 ///
1233 UINT32 PerformanceEnergyBias:1;
1234 UINT32 Reserved2:28;
1235 } Bits;
1236 ///
1237 /// All bit fields as a 32-bit value
1238 ///
1239 UINT32 Uint32;
1240 } CPUID_THERMAL_POWER_MANAGEMENT_ECX;
1241
1242
1243 /**
1244 CPUID Structured Extended Feature Flags Enumeration
1245
1246 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1247 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1248
1249 @note
1250 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1251 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1252
1253 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1254 @retval EBX Structured Extended Feature Flags described by the type
1255 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1256 @retval EBX Structured Extended Feature Flags described by the type
1257 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1258 @retval EDX Reserved.
1259
1260 <b>Example usage</b>
1261 @code
1262 UINT32 Eax;
1263 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1264 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1265 UINT32 SubLeaf;
1266
1267 AsmCpuidEx (
1268 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1269 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1270 &Eax, NULL, NULL, NULL
1271 );
1272 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1273 AsmCpuidEx (
1274 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1275 SubLeaf,
1276 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1277 );
1278 SubLeaf++;
1279 } while (SubLeaf <= Eax);
1280 @endcode
1281 **/
1282 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1283
1284 ///
1285 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1286 ///
1287 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1288
1289 /**
1290 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1291 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1292 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1293 **/
1294 typedef union {
1295 ///
1296 /// Individual bit fields
1297 ///
1298 struct {
1299 ///
1300 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1301 ///
1302 UINT32 FSGSBASE:1;
1303 ///
1304 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1305 ///
1306 UINT32 IA32_TSC_ADJUST:1;
1307 ///
1308 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
1309 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
1310 ///
1311 UINT32 SGX:1;
1312 ///
1313 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1314 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1315 ///
1316 UINT32 BMI1:1;
1317 ///
1318 /// [Bit 4] Hardware Lock Elision
1319 ///
1320 UINT32 HLE:1;
1321 ///
1322 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1323 ///
1324 UINT32 AVX2:1;
1325 ///
1326 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1327 ///
1328 UINT32 FDP_EXCPTN_ONLY:1;
1329 ///
1330 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1331 ///
1332 UINT32 SMEP:1;
1333 ///
1334 /// [Bit 8] If 1 indicates the processor supports the second group of
1335 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1336 /// SARX, SHLX, SHRX)
1337 ///
1338 UINT32 BMI2:1;
1339 ///
1340 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1341 ///
1342 UINT32 EnhancedRepMovsbStosb:1;
1343 ///
1344 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1345 /// manages process-context identifiers.
1346 ///
1347 UINT32 INVPCID:1;
1348 ///
1349 /// [Bit 11] Restricted Transactional Memory
1350 ///
1351 UINT32 RTM:1;
1352 ///
1353 /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)
1354 /// capability if 1.
1355 ///
1356 UINT32 PQM:1;
1357 ///
1358 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1359 ///
1360 UINT32 DeprecateFpuCsDs:1;
1361 ///
1362 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1363 ///
1364 UINT32 MPX:1;
1365 ///
1366 /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)
1367 /// capability if 1.
1368 ///
1369 UINT32 PQE:1;
1370 UINT32 Reserved2:2;
1371 ///
1372 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1373 ///
1374 UINT32 RDSEED:1;
1375 ///
1376 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1377 /// instructions.
1378 ///
1379 UINT32 ADX:1;
1380 ///
1381 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1382 /// instructions) if 1.
1383 ///
1384 UINT32 SMAP:1;
1385 UINT32 Reserved3:2;
1386 ///
1387 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1388 ///
1389 UINT32 CLFLUSHOPT:1;
1390 UINT32 Reserved4:1;
1391 ///
1392 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1393 /// extensions.
1394 ///
1395 UINT32 IntelProcessorTrace:1;
1396 UINT32 Reserved5:6;
1397 } Bits;
1398 ///
1399 /// All bit fields as a 32-bit value
1400 ///
1401 UINT32 Uint32;
1402 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
1403
1404 /**
1405 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1406 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1407 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1408 **/
1409 typedef union {
1410 ///
1411 /// Individual bit fields
1412 ///
1413 struct {
1414 ///
1415 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1416 ///
1417 UINT32 PREFETCHWT1:1;
1418 UINT32 Reserved1:2;
1419 ///
1420 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1421 ///
1422 UINT32 PKU:1;
1423 ///
1424 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1425 /// RDPKRU/WRPKRU instructions).
1426 ///
1427 UINT32 OSPKE:1;
1428 UINT32 Reserved2:27;
1429 } Bits;
1430 ///
1431 /// All bit fields as a 32-bit value
1432 ///
1433 UINT32 Uint32;
1434 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
1435
1436
1437 /**
1438 CPUID Direct Cache Access Information
1439
1440 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1441
1442 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1443 @retval EBX Reserved.
1444 @retval ECX Reserved.
1445 @retval EDX Reserved.
1446
1447 <b>Example usage</b>
1448 @code
1449 UINT32 Eax;
1450
1451 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1452 @endcode
1453 **/
1454 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1455
1456
1457 /**
1458 CPUID Architectural Performance Monitoring
1459
1460 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1461
1462 @retval EAX Architectural Performance Monitoring information described by
1463 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1464 @retval EBX Architectural Performance Monitoring information described by
1465 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1466 @retval ECX Reserved.
1467 @retval EDX Architectural Performance Monitoring information described by
1468 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1469
1470 <b>Example usage</b>
1471 @code
1472 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1473 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1474 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1475
1476 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1477 @endcode
1478 **/
1479 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1480
1481 /**
1482 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1483 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1484 **/
1485 typedef union {
1486 ///
1487 /// Individual bit fields
1488 ///
1489 struct {
1490 ///
1491 /// [Bit 7:0] Version ID of architectural performance monitoring.
1492 ///
1493 UINT32 ArchPerfMonVerID:8;
1494 ///
1495 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1496 /// per logical processor.
1497 ///
1498 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1499 /// block of MSR address space. Each performance event select register is
1500 /// paired with a corresponding performance counter in the 0C1H address
1501 /// block.
1502 ///
1503 UINT32 PerformanceMonitorCounters:8;
1504 ///
1505 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1506 ///
1507 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1508 /// read operation. On write operations, the lower-order 32 bits of the MSR
1509 /// may be written with any value, and the high-order bits are sign-extended
1510 /// from the value of bit 31.
1511 ///
1512 UINT32 PerformanceMonitorCounterWidth:8;
1513 ///
1514 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1515 /// performance monitoring events.
1516 ///
1517 UINT32 EbxBitVectorLength:8;
1518 } Bits;
1519 ///
1520 /// All bit fields as a 32-bit value
1521 ///
1522 UINT32 Uint32;
1523 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
1524
1525 /**
1526 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1527 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1528 **/
1529 typedef union {
1530 ///
1531 /// Individual bit fields
1532 ///
1533 struct {
1534 ///
1535 /// [Bit 0] Core cycle event not available if 1.
1536 ///
1537 UINT32 UnhaltedCoreCycles:1;
1538 ///
1539 /// [Bit 1] Instruction retired event not available if 1.
1540 ///
1541 UINT32 InstructionsRetired:1;
1542 ///
1543 /// [Bit 2] Reference cycles event not available if 1.
1544 ///
1545 UINT32 UnhaltedReferenceCycles:1;
1546 ///
1547 /// [Bit 3] Last-level cache reference event not available if 1.
1548 ///
1549 UINT32 LastLevelCacheReferences:1;
1550 ///
1551 /// [Bit 4] Last-level cache misses event not available if 1.
1552 ///
1553 UINT32 LastLevelCacheMisses:1;
1554 ///
1555 /// [Bit 5] Branch instruction retired event not available if 1.
1556 ///
1557 UINT32 BranchInstructionsRetired:1;
1558 ///
1559 /// [Bit 6] Branch mispredict retired event not available if 1.
1560 ///
1561 UINT32 AllBranchMispredictRetired:1;
1562 UINT32 Reserved:25;
1563 } Bits;
1564 ///
1565 /// All bit fields as a 32-bit value
1566 ///
1567 UINT32 Uint32;
1568 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
1569
1570 /**
1571 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1572 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1573 **/
1574 typedef union {
1575 ///
1576 /// Individual bit fields
1577 ///
1578 struct {
1579 ///
1580 /// [Bits 4:0] Number of fixed-function performance counters
1581 /// (if Version ID > 1).
1582 ///
1583 UINT32 FixedFunctionPerformanceCounters:5;
1584 ///
1585 /// [Bits 12:5] Bit width of fixed-function performance counters
1586 /// (if Version ID > 1).
1587 ///
1588 UINT32 FixedFunctionPerformanceCounterWidth:8;
1589 UINT32 Reserved:19;
1590 } Bits;
1591 ///
1592 /// All bit fields as a 32-bit value
1593 ///
1594 UINT32 Uint32;
1595 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
1596
1597
1598 /**
1599 CPUID Extended Topology Information
1600
1601 @note
1602 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1603 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1604 value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that
1605 return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If
1606 an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1607 other input values with ECX > n also return 0 in ECX[15:8].
1608
1609 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1610 @param ECX Level number
1611
1612 @retval EAX Extended topology information described by the type
1613 CPUID_EXTENDED_TOPOLOGY_EAX.
1614 @retval EBX Extended topology information described by the type
1615 CPUID_EXTENDED_TOPOLOGY_EBX.
1616 @retval ECX Extended topology information described by the type
1617 CPUID_EXTENDED_TOPOLOGY_ECX.
1618 @retval EDX x2APIC ID the current logical processor.
1619
1620 <b>Example usage</b>
1621 @code
1622 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1623 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1624 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1625 UINT32 Edx;
1626 UINT32 LevelNumber;
1627
1628 LevelNumber = 0;
1629 do {
1630 AsmCpuidEx (
1631 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1632 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1633 );
1634 LevelNumber++;
1635 } while (Eax.Bits.ApicIdShift != 0);
1636 @endcode
1637 **/
1638 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1639
1640 /**
1641 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1642 **/
1643 typedef union {
1644 ///
1645 /// Individual bit fields
1646 ///
1647 struct {
1648 ///
1649 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1650 /// topology ID of the next level type. All logical processors with the
1651 /// same next level ID share current level.
1652 ///
1653 /// @note
1654 /// Software should use this field (EAX[4:0]) to enumerate processor
1655 /// topology of the system.
1656 ///
1657 UINT32 ApicIdShift:5;
1658 UINT32 Reserved:27;
1659 } Bits;
1660 ///
1661 /// All bit fields as a 32-bit value
1662 ///
1663 UINT32 Uint32;
1664 } CPUID_EXTENDED_TOPOLOGY_EAX;
1665
1666 /**
1667 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1668 **/
1669 typedef union {
1670 ///
1671 /// Individual bit fields
1672 ///
1673 struct {
1674 ///
1675 /// [Bits 15:0] Number of logical processors at this level type. The number
1676 /// reflects configuration as shipped by Intel.
1677 ///
1678 /// @note
1679 /// Software must not use EBX[15:0] to enumerate processor topology of the
1680 /// system. This value in this field (EBX[15:0]) is only intended for
1681 /// display/diagnostic purposes. The actual number of logical processors
1682 /// available to BIOS/OS/Applications may be different from the value of
1683 /// EBX[15:0], depending on software and platform hardware configurations.
1684 ///
1685 UINT32 LogicalProcessors:16;
1686 UINT32 Reserved:16;
1687 } Bits;
1688 ///
1689 /// All bit fields as a 32-bit value
1690 ///
1691 UINT32 Uint32;
1692 } CPUID_EXTENDED_TOPOLOGY_EBX;
1693
1694 /**
1695 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1696 **/
1697 typedef union {
1698 ///
1699 /// Individual bit fields
1700 ///
1701 struct {
1702 ///
1703 /// [Bits 7:0] Level number. Same value in ECX input.
1704 ///
1705 UINT32 LevelNumber:8;
1706 ///
1707 /// [Bits 15:8] Level type.
1708 ///
1709 /// @note
1710 /// The value of the "level type" field is not related to level numbers in
1711 /// any way, higher "level type" values do not mean higher levels.
1712 ///
1713 UINT32 LevelType:8;
1714 UINT32 Reserved:16;
1715 } Bits;
1716 ///
1717 /// All bit fields as a 32-bit value
1718 ///
1719 UINT32 Uint32;
1720 } CPUID_EXTENDED_TOPOLOGY_ECX;
1721
1722 ///
1723 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1724 ///
1725 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1726 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1727 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1728 ///
1729 /// @}
1730 ///
1731
1732
1733 /**
1734 CPUID Extended State Information
1735
1736 @param EAX CPUID_EXTENDED_STATE (0x0D)
1737 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1738 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1739 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1740 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1741 **/
1742 #define CPUID_EXTENDED_STATE 0x0D
1743
1744 /**
1745 CPUID Extended State Information Main Leaf
1746
1747 @param EAX CPUID_EXTENDED_STATE (0x0D)
1748 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1749
1750 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1751 can be set to 1 only if EAX[n] is 1. The format of the extended
1752 state main leaf is described by the type
1753 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1754 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1755 area) required by enabled features in XCR0. May be different than
1756 ECX if some features at the end of the XSAVE save area are not
1757 enabled.
1758 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1759 area) of the XSAVE/XRSTOR save area required by all supported
1760 features in the processor, i.e all the valid bit fields in XCR0.
1761 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1762 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1763
1764 <b>Example usage</b>
1765 @code
1766 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1767 UINT32 Ebx;
1768 UINT32 Ecx;
1769 UINT32 Edx;
1770
1771 AsmCpuidEx (
1772 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1773 &Eax.Uint32, &Ebx, &Ecx, &Edx
1774 );
1775 @endcode
1776 **/
1777 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1778
1779 /**
1780 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1781 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1782 **/
1783 typedef union {
1784 ///
1785 /// Individual bit fields
1786 ///
1787 struct {
1788 ///
1789 /// [Bit 0] x87 state.
1790 ///
1791 UINT32 x87:1;
1792 ///
1793 /// [Bit 1] SSE state.
1794 ///
1795 UINT32 SSE:1;
1796 ///
1797 /// [Bit 2] AVX state.
1798 ///
1799 UINT32 AVX:1;
1800 ///
1801 /// [Bits 4:3] MPX state.
1802 ///
1803 UINT32 MPX:2;
1804 ///
1805 /// [Bits 7:5] AVX-512 state.
1806 ///
1807 UINT32 AVX_512:3;
1808 ///
1809 /// [Bit 8] Used for IA32_XSS.
1810 ///
1811 UINT32 IA32_XSS:1;
1812 ///
1813 /// [Bit 9] PKRU state.
1814 ///
1815 UINT32 PKRU:1;
1816 UINT32 Reserved:22;
1817 } Bits;
1818 ///
1819 /// All bit fields as a 32-bit value
1820 ///
1821 UINT32 Uint32;
1822 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
1823
1824 /**
1825 CPUID Extended State Information Sub Leaf
1826
1827 @param EAX CPUID_EXTENDED_STATE (0x0D)
1828 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
1829
1830 @retval EAX The format of the extended state sub-leaf is described by the
1831 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
1832 @retval EBX The size in bytes of the XSAVE area containing all states
1833 enabled by XCRO | IA32_XSS.
1834 @retval ECX The format of the extended state sub-leaf is described by the
1835 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
1836 @retval EDX Reports the supported bits of the upper 32 bits of the
1837 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
1838
1839 <b>Example usage</b>
1840 @code
1841 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
1842 UINT32 Ebx;
1843 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
1844 UINT32 Edx;
1845
1846 AsmCpuidEx (
1847 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
1848 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
1849 );
1850 @endcode
1851 **/
1852 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
1853
1854 /**
1855 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1856 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1857 **/
1858 typedef union {
1859 ///
1860 /// Individual bit fields
1861 ///
1862 struct {
1863 ///
1864 /// [Bit 0] XSAVEOPT is available.
1865 ///
1866 UINT32 XSAVEOPT:1;
1867 ///
1868 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
1869 ///
1870 UINT32 XSAVEC:1;
1871 ///
1872 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
1873 ///
1874 UINT32 XGETBV:1;
1875 ///
1876 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
1877 ///
1878 UINT32 XSAVES:1;
1879 UINT32 Reserved:28;
1880 } Bits;
1881 ///
1882 /// All bit fields as a 32-bit value
1883 ///
1884 UINT32 Uint32;
1885 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
1886
1887 /**
1888 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1889 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
1890 **/
1891 typedef union {
1892 ///
1893 /// Individual bit fields
1894 ///
1895 struct {
1896 ///
1897 /// [Bits 7:0] Used for XCR0.
1898 ///
1899 UINT32 XCR0:1;
1900 ///
1901 /// [Bit 8] PT STate.
1902 ///
1903 UINT32 PT:1;
1904 ///
1905 /// [Bit 9] Used for XCR0.
1906 ///
1907 UINT32 XCR0_1:1;
1908 UINT32 Reserved:22;
1909 } Bits;
1910 ///
1911 /// All bit fields as a 32-bit value
1912 ///
1913 UINT32 Uint32;
1914 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
1915
1916 /**
1917 CPUID Extended State Information Size and Offset Sub Leaf
1918
1919 @note
1920 Leaf 0DH output depends on the initial value in ECX.
1921 Each sub-leaf index (starting at position 2) is supported if it corresponds to
1922 a supported bit in either the XCR0 register or the IA32_XSS MSR.
1923 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1924 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
1925 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
1926 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
1927
1928 @param EAX CPUID_EXTENDED_STATE (0x0D)
1929 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
1930 on supported bits in XCR0 or IA32_XSS_MSR.
1931
1932 @retval EAX The size in bytes (from the offset specified in EBX) of the save
1933 area for an extended state feature associated with a valid
1934 sub-leaf index, n.
1935 @retval EBX The offset in bytes of this extended state component's save area
1936 from the beginning of the XSAVE/XRSTOR area. This field reports
1937 0 if the sub-leaf index, n, does not map to a valid bit in the
1938 XCR0 register.
1939 @retval ECX The format of the extended state components's save area as
1940 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
1941 This field reports 0 if the sub-leaf index, n, is invalid.
1942 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
1943 otherwise it is reserved.
1944
1945 <b>Example usage</b>
1946 @code
1947 UINT32 Eax;
1948 UINT32 Ebx;
1949 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
1950 UINT32 Edx;
1951 UINTN SubLeaf;
1952
1953 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
1954 AsmCpuidEx (
1955 CPUID_EXTENDED_STATE, SubLeaf,
1956 &Eax, &Ebx, &Ecx.Uint32, &Edx
1957 );
1958 }
1959 @endcode
1960 **/
1961 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
1962
1963 /**
1964 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
1965 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
1966 **/
1967 typedef union {
1968 ///
1969 /// Individual bit fields
1970 ///
1971 struct {
1972 ///
1973 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
1974 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
1975 /// in XCR0.
1976 ///
1977 UINT32 XSS:1;
1978 ///
1979 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
1980 /// this extended state component located on the next 64-byte boundary
1981 /// following the preceding state component (otherwise, it is located
1982 /// immediately following the preceding state component).
1983 ///
1984 UINT32 Compacted:1;
1985 UINT32 Reserved:30;
1986 } Bits;
1987 ///
1988 /// All bit fields as a 32-bit value
1989 ///
1990 UINT32 Uint32;
1991 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
1992
1993
1994 /**
1995 CPUID Platform QoS Monitoring Information
1996
1997 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
1998 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).
1999 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).
2000
2001 **/
2002 #define CPUID_PLATFORM_QOS_MONITORING 0x0F
2003
2004 /**
2005 CPUID Platform QoS Monitoring Information Enumeration Sub-leaf
2006
2007 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
2008 @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2009
2010 @retval EAX Reserved.
2011 @retval EBX Maximum range (zero-based) of RMID within this physical
2012 processor of all types.
2013 @retval ECX Reserved.
2014 @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the
2015 type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2016
2017 <b>Example usage</b>
2018 @code
2019 UINT32 Ebx;
2020 CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2021
2022 AsmCpuidEx (
2023 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
2024 NULL, &Ebx, NULL, &Edx.Uint32
2025 );
2026 @endcode
2027 **/
2028 #define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00
2029
2030 /**
2031 CPUID Platform QoS Monitoring Information EDX for CPUID leaf
2032 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
2033 #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.
2034 **/
2035 typedef union {
2036 ///
2037 /// Individual bit fields
2038 ///
2039 struct {
2040 UINT32 Reserved1:1;
2041 ///
2042 /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.
2043 ///
2044 UINT32 L3CacheQosEnforcement:1;
2045 UINT32 Reserved2:30;
2046 } Bits;
2047 ///
2048 /// All bit fields as a 32-bit value
2049 ///
2050 UINT32 Uint32;
2051 } CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;
2052
2053 /**
2054 CPUID Platform QoS Monitoring Information Capability Sub-leaf
2055
2056 @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
2057 @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)
2058
2059 @retval EAX Reserved.
2060 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2061 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2062 @retval EDX L3 Cache QoS Monitoring Capability information described by the
2063 type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.
2064
2065 <b>Example usage</b>
2066 @code
2067 UINT32 Ebx;
2068 UINT32 Ecx;
2069 CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
2070
2071 AsmCpuidEx (
2072 CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
2073 NULL, &Ebx, &Ecx, &Edx.Uint32
2074 );
2075 @endcode
2076 **/
2077 #define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01
2078
2079 /**
2080 CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf
2081 #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
2082 #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.
2083 **/
2084 typedef union {
2085 ///
2086 /// Individual bit fields
2087 ///
2088 struct {
2089 ///
2090 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2091 ///
2092 UINT32 L3CacheOccupancyMonitoring:1;
2093 UINT32 Reserved:31;
2094 } Bits;
2095 ///
2096 /// All bit fields as a 32-bit value
2097 ///
2098 UINT32 Uint32;
2099 } CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;
2100
2101
2102 /**
2103 CPUID Platform QoS Enforcement Information
2104
2105 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).
2106 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
2107 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).
2108 Additional sub leafs 1..n based in RESID from sub leaf 0x00.
2109 **/
2110 #define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10
2111
2112 /**
2113 CPUID Platform QoS Enforcement Information
2114
2115 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
2116 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
2117
2118 @retval EAX Reserved.
2119 @retval EBX L3 Cache QoS Enforcement information described by the
2120 type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.
2121 @retval ECX Reserved.
2122 @retval EDX Reserved.
2123
2124 <b>Example usage</b>
2125 @code
2126 CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
2127
2128 AsmCpuidEx (
2129 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
2130 NULL, &Ebx.Uint32, NULL, NULL
2131 );
2132 @endcode
2133 **/
2134 #define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00
2135
2136 /**
2137 CPUID Platform QoS Enforcement Information EBX for CPUID leaf
2138 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2139 #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.
2140 **/
2141 typedef union {
2142 ///
2143 /// Individual bit fields
2144 ///
2145 struct {
2146 UINT32 Reserved1:1;
2147 ///
2148 /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.
2149 ///
2150 UINT32 L3CacheQosEnforcement:1;
2151 UINT32 Reserved2:30;
2152 } Bits;
2153 ///
2154 /// All bit fields as a 32-bit value
2155 ///
2156 UINT32 Uint32;
2157 } CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;
2158
2159
2160 /**
2161 CPUID Platform QoS Enforcement Information
2162
2163 @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
2164 @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)
2165 Additional sub leafs 1..n based in RESID from sub leaf 0x00.
2166
2167 @retval EAX RESID L3 Cache3 QoS Enforcement information described by the
2168 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.
2169 @retval EBX Bit-granular map of isolation/contention of allocation units.
2170 @retval ECX RESID L3 Cache3 QoS Enforcement information described by the
2171 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.
2172 @retval EDX RESID L3 Cache3 QoS Enforcement information described by the
2173 type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.
2174
2175 <b>Example usage</b>
2176 @code
2177 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
2178 UINT32 Ebx;
2179 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
2180 CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
2181
2182 AsmCpuidEx (
2183 CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
2184 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2185 );
2186 @endcode
2187 **/
2188 #define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01
2189
2190 /**
2191 CPUID Platform QoS Enforcement Information EAX for CPUID leaf
2192 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2193 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2194 **/
2195 typedef union {
2196 ///
2197 /// Individual bit fields
2198 ///
2199 struct {
2200 ///
2201 /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.
2202 ///
2203 UINT32 CapacityLength:4;
2204 UINT32 Reserved:28;
2205 } Bits;
2206 ///
2207 /// All bit fields as a 32-bit value
2208 ///
2209 UINT32 Uint32;
2210 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;
2211
2212 /**
2213 CPUID Platform QoS Enforcement Information ECX for CPUID leaf
2214 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2215 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2216 **/
2217 typedef union {
2218 ///
2219 /// Individual bit fields
2220 ///
2221 struct {
2222 UINT32 Reserved1:1;
2223 ///
2224 /// [Bit 1] Updates of COS should be infrequent if 1.
2225 ///
2226 UINT32 CosUpdatesInfrequent:1;
2227 ///
2228 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2229 ///
2230 UINT32 CodeDataPrioritization:1;
2231 UINT32 Reserved2:29;
2232 } Bits;
2233 ///
2234 /// All bit fields as a 32-bit value
2235 ///
2236 UINT32 Uint32;
2237 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;
2238
2239 /**
2240 CPUID Platform QoS Enforcement Information EDX for CPUID leaf
2241 #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
2242 #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
2243 **/
2244 typedef union {
2245 ///
2246 /// Individual bit fields
2247 ///
2248 struct {
2249 ///
2250 /// [Bits 15:0] Highest COS number supported for this ResID.
2251 ///
2252 UINT32 HighestCosNumber:16;
2253 UINT32 Reserved:16;
2254 } Bits;
2255 ///
2256 /// All bit fields as a 32-bit value
2257 ///
2258 UINT32 Uint32;
2259 } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;
2260
2261
2262 /**
2263 Intel SGX resource capability and configuration.
2264 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
2265
2266 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
2267 CPUID with EAX=12H on Intel SGX resource capability and configuration.
2268
2269 @param EAX CPUID_INTEL_SGX (0x12)
2270 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
2271 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
2272 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
2273 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
2274 until the sub-leaf type is invalid.
2275
2276 **/
2277 #define CPUID_INTEL_SGX 0x12
2278
2279 /**
2280 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
2281 Enumerates Intel SGX capability, including enclave instruction opcode support.
2282
2283 @param EAX CPUID_INTEL_SGX (0x12)
2284 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
2285
2286 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2287 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
2288 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
2289 that can be written to the MISC region of the SSA.
2290 @retval ECX Reserved.
2291 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2292 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
2293
2294 <b>Example usage</b>
2295 @code
2296 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
2297 UINT32 Ebx;
2298 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
2299
2300 AsmCpuidEx (
2301 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
2302 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2303 );
2304 @endcode
2305 **/
2306 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2307
2308 /**
2309 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
2310 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2311 **/
2312 typedef union {
2313 ///
2314 /// Individual bit fields
2315 ///
2316 struct {
2317 ///
2318 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
2319 ///
2320 UINT32 SGX1:1;
2321 ///
2322 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
2323 ///
2324 UINT32 SGX2:1;
2325 UINT32 Reserved:30;
2326 } Bits;
2327 ///
2328 /// All bit fields as a 32-bit value
2329 ///
2330 UINT32 Uint32;
2331 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
2332
2333 /**
2334 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
2335 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2336 **/
2337 typedef union {
2338 ///
2339 /// Individual bit fields
2340 ///
2341 struct {
2342 ///
2343 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
2344 /// when not in 64-bit mode.
2345 ///
2346 UINT32 MaxEnclaveSize_Not64:8;
2347 ///
2348 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
2349 /// when operating in 64-bit mode.
2350 ///
2351 UINT32 MaxEnclaveSize_64:8;
2352 UINT32 Reserved:16;
2353 } Bits;
2354 ///
2355 /// All bit fields as a 32-bit value
2356 ///
2357 UINT32 Uint32;
2358 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
2359
2360
2361 /**
2362 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
2363 Enumerates Intel SGX capability of processor state configuration and enclave
2364 configuration in the SECS structure.
2365
2366 @param EAX CPUID_INTEL_SGX (0x12)
2367 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
2368
2369 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
2370 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
2371 only if EAX[n] is 1, where n < 32.
2372 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
2373 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
2374 only if EBX[n] is 1, where n < 32.
2375 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
2376 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
2377 only if ECX[n] is 1, where n < 32.
2378 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
2379 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
2380 only if EDX[n] is 1, where n < 32.
2381
2382 <b>Example usage</b>
2383 @code
2384 UINT32 Eax;
2385 UINT32 Ebx;
2386 UINT32 Ecx;
2387 UINT32 Edx;
2388
2389 AsmCpuidEx (
2390 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
2391 &Eax, &Ebx, &Ecx, &Edx
2392 );
2393 @endcode
2394 **/
2395 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2396
2397
2398 /**
2399 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
2400 Enumerates available EPC resources.
2401
2402 @param EAX CPUID_INTEL_SGX (0x12)
2403 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
2404
2405 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2406 Resources is described by the type
2407 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
2408 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2409 Resources is described by the type
2410 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
2411 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2412 Resources is described by the type
2413 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
2414 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2415 Resources is described by the type
2416 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
2417
2418 <b>Example usage</b>
2419 @code
2420 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
2421 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
2422 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
2423 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
2424
2425 AsmCpuidEx (
2426 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
2427 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2428 );
2429 @endcode
2430 **/
2431 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2432
2433 /**
2434 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
2435 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2436 **/
2437 typedef union {
2438 ///
2439 /// Individual bit fields
2440 ///
2441 struct {
2442 ///
2443 /// [Bit 3:0] Sub-leaf-type encoding.
2444 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
2445 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
2446 /// in EBX:EAX and EDX:ECX.
2447 /// All other encoding are reserved.
2448 ///
2449 UINT32 SubLeafType:4;
2450 UINT32 Reserved:8;
2451 ///
2452 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
2453 /// the base of the EPC section.
2454 ///
2455 UINT32 LowAddressOfEpcSection:20;
2456 } Bits;
2457 ///
2458 /// All bit fields as a 32-bit value
2459 ///
2460 UINT32 Uint32;
2461 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
2462
2463 /**
2464 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
2465 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2466 **/
2467 typedef union {
2468 ///
2469 /// Individual bit fields
2470 ///
2471 struct {
2472 ///
2473 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
2474 /// the base of the EPC section.
2475 ///
2476 UINT32 HighAddressOfEpcSection:20;
2477 UINT32 Reserved:12;
2478 } Bits;
2479 ///
2480 /// All bit fields as a 32-bit value
2481 ///
2482 UINT32 Uint32;
2483 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
2484
2485 /**
2486 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
2487 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2488 **/
2489 typedef union {
2490 ///
2491 /// Individual bit fields
2492 ///
2493 struct {
2494 ///
2495 /// [Bit 3:0] The EPC section encoding.
2496 /// 0000b: Not valid.
2497 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
2498 /// All other encoding are reserved.
2499 ///
2500 UINT32 EpcSection:4;
2501 UINT32 Reserved:8;
2502 ///
2503 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
2504 /// corresponding EPC section within the Processor Reserved Memory.
2505 ///
2506 UINT32 LowSizeOfEpcSection:20;
2507 } Bits;
2508 ///
2509 /// All bit fields as a 32-bit value
2510 ///
2511 UINT32 Uint32;
2512 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
2513
2514 /**
2515 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
2516 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2517 **/
2518 typedef union {
2519 ///
2520 /// Individual bit fields
2521 ///
2522 struct {
2523 ///
2524 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
2525 /// corresponding EPC section within the Processor Reserved Memory.
2526 ///
2527 UINT32 HighSizeOfEpcSection:20;
2528 UINT32 Reserved:12;
2529 } Bits;
2530 ///
2531 /// All bit fields as a 32-bit value
2532 ///
2533 UINT32 Uint32;
2534 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
2535
2536
2537 /**
2538 CPUID Intel Processor Trace Information
2539
2540 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2541 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2542 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2543
2544 **/
2545 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2546
2547 /**
2548 CPUID Intel Processor Trace Information Main Leaf
2549
2550 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2551 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2552
2553 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2554 @retval EBX Returns Intel processor trace information described by the
2555 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2556 @retval ECX Returns Intel processor trace information described by the
2557 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2558 @retval EDX Reserved.
2559
2560 <b>Example usage</b>
2561 @code
2562 UINT32 Eax;
2563 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2564 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2565
2566 AsmCpuidEx (
2567 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2568 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2569 );
2570 @endcode
2571 **/
2572 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2573
2574 /**
2575 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2576 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2577 **/
2578 typedef union {
2579 ///
2580 /// Individual bit fields
2581 ///
2582 struct {
2583 ///
2584 /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2585 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2586 ///
2587 UINT32 Cr3Filter:1;
2588 ///
2589 /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate
2590 /// Mode.
2591 ///
2592 UINT32 ConfigurablePsb:1;
2593 ///
2594 /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,
2595 /// and preservation of Intel PT MSRs across warm reset.
2596 ///
2597 UINT32 IpTraceStopFiltering:1;
2598 ///
2599 /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of
2600 /// COFI-based packets.
2601 ///
2602 UINT32 Mtc:1;
2603 UINT32 Reserved:28;
2604 } Bits;
2605 ///
2606 /// All bit fields as a 32-bit value
2607 ///
2608 UINT32 Uint32;
2609 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
2610
2611 /**
2612 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2613 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2614 **/
2615 typedef union {
2616 ///
2617 /// Individual bit fields
2618 ///
2619 struct {
2620 ///
2621 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
2622 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
2623 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
2624 ///
2625 UINT32 RTIT:1;
2626 ///
2627 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
2628 /// the maximum allowed by the MaskOrTableOffset field of
2629 /// IA32_RTIT_OUTPUT_MASK_PTRS.
2630 ///
2631 UINT32 ToPA:1;
2632 ///
2633 /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.
2634 ///
2635 UINT32 SingleRangeOutput:1;
2636 ///
2637 /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.
2638 ///
2639 UINT32 TraceTransportSubsystem:1;
2640 UINT32 Reserved:27;
2641 ///
2642 /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP
2643 /// values, which include the CS base component.
2644 ///
2645 UINT32 LIP:1;
2646 } Bits;
2647 ///
2648 /// All bit fields as a 32-bit value
2649 ///
2650 UINT32 Uint32;
2651 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
2652
2653
2654 /**
2655 CPUID Intel Processor Trace Information Sub-leaf
2656
2657 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2658 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
2659
2660 @retval EAX Returns Intel processor trace information described by the
2661 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
2662 @retval EBX Returns Intel processor trace information described by the
2663 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
2664 @retval ECX Reserved.
2665 @retval EDX Reserved.
2666
2667 <b>Example usage</b>
2668 @code
2669 UINT32 MaximumSubLeaf;
2670 UINT32 SubLeaf;
2671 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
2672 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
2673
2674 AsmCpuidEx (
2675 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2676 &MaximumSubLeaf, NULL, NULL, NULL
2677 );
2678
2679 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
2680 AsmCpuidEx (
2681 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
2682 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
2683 );
2684 }
2685 @endcode
2686 **/
2687 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
2688
2689 /**
2690 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2691 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2692 **/
2693 typedef union {
2694 ///
2695 /// Individual bit fields
2696 ///
2697 struct {
2698 ///
2699 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
2700 ///
2701 UINT32 ConfigurableAddressRanges:3;
2702 UINT32 Reserved:13;
2703 ///
2704 /// [Bits 31:16] Bitmap of supported MTC period encodings
2705 ///
2706 UINT32 MtcPeriodEncodings:16;
2707
2708 } Bits;
2709 ///
2710 /// All bit fields as a 32-bit value
2711 ///
2712 UINT32 Uint32;
2713 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
2714
2715 /**
2716 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2717 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
2718 **/
2719 typedef union {
2720 ///
2721 /// Individual bit fields
2722 ///
2723 struct {
2724 ///
2725 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
2726 ///
2727 UINT32 CycleThresholdEncodings:16;
2728 ///
2729 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
2730 ///
2731 UINT32 PsbFrequencyEncodings:16;
2732
2733 } Bits;
2734 ///
2735 /// All bit fields as a 32-bit value
2736 ///
2737 UINT32 Uint32;
2738 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
2739
2740
2741 /**
2742 CPUID Time Stamp Counter Information
2743
2744 @note
2745 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
2746 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
2747 crystal clock frequency.
2748 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
2749 The core crystal clock may differ from the reference clock, bus clock, or core
2750 clock frequencies.
2751
2752 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
2753
2754 @retval EAX An unsigned integer which is the denominator of the
2755 TSC/"core crystal clock" ratio
2756 @retval EBX An unsigned integer which is the numerator of the
2757 TSC/"core crystal clock" ratio.
2758 @retval ECX Reserved.
2759 @retval EDX Reserved.
2760
2761 <b>Example usage</b>
2762 @code
2763 UINT32 Eax;
2764 UINT32 Ebx;
2765
2766 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
2767 @endcode
2768 **/
2769 #define CPUID_TIME_STAMP_COUNTER 0x15
2770
2771
2772 /**
2773 CPUID Processor Frequency Information
2774
2775 @note
2776 Data is returned from this interface in accordance with the processor's
2777 specification and does not reflect actual values. Suitable use of this data
2778 includes the display of processor information in like manner to the processor
2779 brand string and for determining the appropriate range to use when displaying
2780 processor information e.g. frequency history graphs. The returned information
2781 should not be used for any other purpose as the returned information does not
2782 accurately correlate to information / counters returned by other processor
2783 interfaces. While a processor may support the Processor Frequency Information
2784 leaf, fields that return a value of zero are not supported.
2785
2786 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
2787
2788 @retval EAX Returns processor base frequency information described by the
2789 type CPUID_PROCESSOR_FREQUENCY_EAX.
2790 @retval EBX Returns maximum frequency information described by the type
2791 CPUID_PROCESSOR_FREQUENCY_EBX.
2792 @retval ECX Returns bus frequency information described by the type
2793 CPUID_PROCESSOR_FREQUENCY_ECX.
2794 @retval EDX Reserved.
2795
2796 <b>Example usage</b>
2797 @code
2798 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
2799 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
2800 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
2801
2802 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
2803 @endcode
2804 **/
2805 #define CPUID_PROCESSOR_FREQUENCY 0x16
2806
2807 /**
2808 CPUID Processor Frequency Information EAX for CPUID leaf
2809 #CPUID_PROCESSOR_FREQUENCY.
2810 **/
2811 typedef union {
2812 ///
2813 /// Individual bit fields
2814 ///
2815 struct {
2816 ///
2817 /// [Bits 15:0] Processor Base Frequency (in MHz).
2818 ///
2819 UINT32 ProcessorBaseFrequency:16;
2820 UINT32 Reserved:16;
2821 } Bits;
2822 ///
2823 /// All bit fields as a 32-bit value
2824 ///
2825 UINT32 Uint32;
2826 } CPUID_PROCESSOR_FREQUENCY_EAX;
2827
2828 /**
2829 CPUID Processor Frequency Information EBX for CPUID leaf
2830 #CPUID_PROCESSOR_FREQUENCY.
2831 **/
2832 typedef union {
2833 ///
2834 /// Individual bit fields
2835 ///
2836 struct {
2837 ///
2838 /// [Bits 15:0] Maximum Frequency (in MHz).
2839 ///
2840 UINT32 MaximumFrequency:16;
2841 UINT32 Reserved:16;
2842 } Bits;
2843 ///
2844 /// All bit fields as a 32-bit value
2845 ///
2846 UINT32 Uint32;
2847 } CPUID_PROCESSOR_FREQUENCY_EBX;
2848
2849 /**
2850 CPUID Processor Frequency Information ECX for CPUID leaf
2851 #CPUID_PROCESSOR_FREQUENCY.
2852 **/
2853 typedef union {
2854 ///
2855 /// Individual bit fields
2856 ///
2857 struct {
2858 ///
2859 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
2860 ///
2861 UINT32 BusFrequency:16;
2862 UINT32 Reserved:16;
2863 } Bits;
2864 ///
2865 /// All bit fields as a 32-bit value
2866 ///
2867 UINT32 Uint32;
2868 } CPUID_PROCESSOR_FREQUENCY_ECX;
2869
2870
2871 /**
2872 CPUID SoC Vendor Information
2873
2874 @param EAX CPUID_SOC_VENDOR (0x17)
2875 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
2876 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
2877 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
2878 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
2879
2880 @note
2881 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
2882 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
2883 Vendor Brand String is constructed by concatenating in ascending order of
2884 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
2885
2886 **/
2887 #define CPUID_SOC_VENDOR 0x17
2888
2889 /**
2890 CPUID SoC Vendor Information
2891
2892 @param EAX CPUID_SOC_VENDOR (0x17)
2893 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
2894
2895 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
2896 sub-leaf in leaf 17H.
2897 @retval EBX Returns SoC Vendor information described by the type
2898 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
2899 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
2900 projects.
2901 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
2902 vendor assigns.
2903
2904 <b>Example usage</b>
2905 @code
2906 UINT32 Eax;
2907 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
2908 UINT32 Ecx;
2909 UINT32 Edx;
2910
2911 AsmCpuidEx (
2912 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
2913 &Eax, &Ebx.Uint32, &Ecx, &Edx
2914 );
2915 @endcode
2916 **/
2917 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
2918
2919 /**
2920 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
2921 #CPUID_SOC_VENDOR_MAIN_LEAF.
2922 **/
2923 typedef union {
2924 ///
2925 /// Individual bit fields
2926 ///
2927 struct {
2928 ///
2929 /// [Bits 15:0] SOC Vendor ID.
2930 ///
2931 UINT32 SocVendorId:16;
2932 ///
2933 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
2934 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
2935 /// assigned by Intel.
2936 ///
2937 UINT32 IsVendorScheme:1;
2938 UINT32 Reserved:15;
2939 } Bits;
2940 ///
2941 /// All bit fields as a 32-bit value
2942 ///
2943 UINT32 Uint32;
2944 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
2945
2946 /**
2947 CPUID SoC Vendor Information
2948
2949 @param EAX CPUID_SOC_VENDOR (0x17)
2950 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
2951
2952 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2953 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2954 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
2955 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2956 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
2957 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2958 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
2959 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2960
2961 <b>Example usage</b>
2962 @code
2963 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
2964 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
2965 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
2966 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
2967
2968 AsmCpuidEx (
2969 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
2970 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2971 );
2972 @endcode
2973 **/
2974 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
2975
2976 /**
2977 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
2978 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
2979 **/
2980 typedef union {
2981 ///
2982 /// 4 UTF-8 characters of Soc Vendor Brand String
2983 ///
2984 CHAR8 BrandString[4];
2985 ///
2986 /// All fields as a 32-bit value
2987 ///
2988 UINT32 Uint32;
2989 } CPUID_SOC_VENDOR_BRAND_STRING_DATA;
2990
2991 /**
2992 CPUID SoC Vendor Information
2993
2994 @param EAX CPUID_SOC_VENDOR (0x17)
2995 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
2996
2997 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
2998 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
2999 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3000 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3001 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3002 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3003 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3004 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3005
3006 <b>Example usage</b>
3007 @code
3008 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3009 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3010 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3011 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3012
3013 AsmCpuidEx (
3014 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
3015 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3016 );
3017 @endcode
3018 **/
3019 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3020
3021 /**
3022 CPUID SoC Vendor Information
3023
3024 @param EAX CPUID_SOC_VENDOR (0x17)
3025 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
3026
3027 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3028 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3029 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3030 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3031 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3032 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3033 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3034 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3035
3036 <b>Example usage</b>
3037 @code
3038 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3039 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3040 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3041 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3042
3043 AsmCpuidEx (
3044 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
3045 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3046 );
3047 @endcode
3048 **/
3049 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3050
3051
3052 /**
3053 CPUID Extended Function
3054
3055 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
3056
3057 @retval EAX Maximum Input Value for Extended Function CPUID Information.
3058 @retval EBX Reserved.
3059 @retval ECX Reserved.
3060 @retval EDX Reserved.
3061
3062 <b>Example usage</b>
3063 @code
3064 UINT32 Eax;
3065
3066 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
3067 @endcode
3068 **/
3069 #define CPUID_EXTENDED_FUNCTION 0x80000000
3070
3071
3072 /**
3073 CPUID Extended Processor Signature and Feature Bits
3074
3075 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
3076
3077 @retval EAX CPUID_EXTENDED_CPU_SIG.
3078 @retval EBX Reserved.
3079 @retval ECX Extended Processor Signature and Feature Bits information
3080 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
3081 @retval EDX Extended Processor Signature and Feature Bits information
3082 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
3083
3084 <b>Example usage</b>
3085 @code
3086 UINT32 Eax;
3087 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
3088 CPUID_EXTENDED_CPU_SIG_EDX Edx;
3089
3090 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
3091 @endcode
3092 **/
3093 #define CPUID_EXTENDED_CPU_SIG 0x80000001
3094
3095 /**
3096 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
3097 #CPUID_EXTENDED_CPU_SIG.
3098 **/
3099 typedef union {
3100 ///
3101 /// Individual bit fields
3102 ///
3103 struct {
3104 ///
3105 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
3106 ///
3107 UINT32 LAHF_SAHF:1;
3108 UINT32 Reserved1:4;
3109 ///
3110 /// [Bit 5] LZCNT.
3111 ///
3112 UINT32 LZCNT:1;
3113 UINT32 Reserved2:2;
3114 ///
3115 /// [Bit 8] PREFETCHW.
3116 ///
3117 UINT32 PREFETCHW:1;
3118 UINT32 Reserved3:23;
3119 } Bits;
3120 ///
3121 /// All bit fields as a 32-bit value
3122 ///
3123 UINT32 Uint32;
3124 } CPUID_EXTENDED_CPU_SIG_ECX;
3125
3126 /**
3127 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
3128 #CPUID_EXTENDED_CPU_SIG.
3129 **/
3130 typedef union {
3131 ///
3132 /// Individual bit fields
3133 ///
3134 struct {
3135 UINT32 Reserved1:11;
3136 ///
3137 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
3138 ///
3139 UINT32 SYSCALL_SYSRET:1;
3140 UINT32 Reserved2:8;
3141 ///
3142 /// [Bit 20] Execute Disable Bit available.
3143 ///
3144 UINT32 NX:1;
3145 UINT32 Reserved3:5;
3146 ///
3147 /// [Bit 26] 1-GByte pages are available if 1.
3148 ///
3149 UINT32 Page1GB:1;
3150 ///
3151 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
3152 ///
3153 UINT32 RDTSCP:1;
3154 UINT32 Reserved4:1;
3155 ///
3156 /// [Bit 29] Intel(R) 64 Architecture available if 1.
3157 ///
3158 UINT32 LM:1;
3159 UINT32 Reserved5:2;
3160 } Bits;
3161 ///
3162 /// All bit fields as a 32-bit value
3163 ///
3164 UINT32 Uint32;
3165 } CPUID_EXTENDED_CPU_SIG_EDX;
3166
3167
3168 /**
3169 CPUID Processor Brand String
3170
3171 @param EAX CPUID_BRAND_STRING1 (0x80000002)
3172
3173 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
3174 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3175 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3176 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3177
3178 <b>Example usage</b>
3179 @code
3180 CPUID_BRAND_STRING_DATA Eax;
3181 CPUID_BRAND_STRING_DATA Ebx;
3182 CPUID_BRAND_STRING_DATA Ecx;
3183 CPUID_BRAND_STRING_DATA Edx;
3184
3185 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3186 @endcode
3187 **/
3188 #define CPUID_BRAND_STRING1 0x80000002
3189
3190 /**
3191 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
3192 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
3193 **/
3194 typedef union {
3195 ///
3196 /// 4 ASCII characters of Processor Brand String
3197 ///
3198 CHAR8 BrandString[4];
3199 ///
3200 /// All fields as a 32-bit value
3201 ///
3202 UINT32 Uint32;
3203 } CPUID_BRAND_STRING_DATA;
3204
3205 /**
3206 CPUID Processor Brand String
3207
3208 @param EAX CPUID_BRAND_STRING2 (0x80000003)
3209
3210 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3211 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3212 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3213 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3214
3215 <b>Example usage</b>
3216 @code
3217 CPUID_BRAND_STRING_DATA Eax;
3218 CPUID_BRAND_STRING_DATA Ebx;
3219 CPUID_BRAND_STRING_DATA Ecx;
3220 CPUID_BRAND_STRING_DATA Edx;
3221
3222 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3223 @endcode
3224 **/
3225 #define CPUID_BRAND_STRING2 0x80000003
3226
3227 /**
3228 CPUID Processor Brand String
3229
3230 @param EAX CPUID_BRAND_STRING3 (0x80000004)
3231
3232 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3233 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3234 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3235 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3236
3237 <b>Example usage</b>
3238 @code
3239 CPUID_BRAND_STRING_DATA Eax;
3240 CPUID_BRAND_STRING_DATA Ebx;
3241 CPUID_BRAND_STRING_DATA Ecx;
3242 CPUID_BRAND_STRING_DATA Edx;
3243
3244 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3245 @endcode
3246 **/
3247 #define CPUID_BRAND_STRING3 0x80000004
3248
3249
3250 /**
3251 CPUID Extended Cache information
3252
3253 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
3254
3255 @retval EAX Reserved.
3256 @retval EBX Reserved.
3257 @retval ECX Extended cache information described by the type
3258 CPUID_EXTENDED_CACHE_INFO_ECX.
3259 @retval EDX Reserved.
3260
3261 <b>Example usage</b>
3262 @code
3263 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
3264
3265 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
3266 @endcode
3267 **/
3268 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
3269
3270 /**
3271 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
3272 **/
3273 typedef union {
3274 ///
3275 /// Individual bit fields
3276 ///
3277 struct {
3278 ///
3279 /// [Bits 7:0] Cache line size in bytes.
3280 ///
3281 UINT32 CacheLineSize:8;
3282 UINT32 Reserved:4;
3283 ///
3284 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3285 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3286 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3287 ///
3288 UINT32 L2Associativity:4;
3289 ///
3290 /// [Bits 31:16] Cache size in 1K units.
3291 ///
3292 UINT32 CacheSize:16;
3293 } Bits;
3294 ///
3295 /// All bit fields as a 32-bit value
3296 ///
3297 UINT32 Uint32;
3298 } CPUID_EXTENDED_CACHE_INFO_ECX;
3299
3300 ///
3301 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3302 ///
3303 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3304 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3305 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3306 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3307 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3308 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3309 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3310 ///
3311 /// @}
3312 ///
3313
3314 /**
3315 CPUID Extended Time Stamp Counter information
3316
3317 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3318
3319 @retval EAX Reserved.
3320 @retval EBX Reserved.
3321 @retval ECX Reserved.
3322 @retval EDX Extended time stamp counter (TSC) information described by the
3323 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3324
3325 <b>Example usage</b>
3326 @code
3327 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3328
3329 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3330 @endcode
3331 **/
3332 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3333
3334 /**
3335 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3336 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3337 **/
3338 typedef union {
3339 ///
3340 /// Individual bit fields
3341 ///
3342 struct {
3343 UINT32 Reserved1:8;
3344 ///
3345 /// [Bit 8] Invariant TSC available if 1.
3346 ///
3347 UINT32 InvariantTsc:1;
3348 UINT32 Reserved2:23;
3349 } Bits;
3350 ///
3351 /// All bit fields as a 32-bit value
3352 ///
3353 UINT32 Uint32;
3354 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
3355
3356
3357 /**
3358 CPUID Linear Physical Address Size
3359
3360 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
3361
3362 @retval EAX Linear/Physical Address Size described by the type
3363 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
3364 @retval EBX Reserved.
3365 @retval ECX Reserved.
3366 @retval EDX Reserved.
3367
3368 <b>Example usage</b>
3369 @code
3370 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
3371
3372 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
3373 @endcode
3374 **/
3375 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
3376
3377 /**
3378 CPUID Linear Physical Address Size EAX for CPUID leaf
3379 #CPUID_VIR_PHY_ADDRESS_SIZE.
3380 **/
3381 typedef union {
3382 ///
3383 /// Individual bit fields
3384 ///
3385 struct {
3386 ///
3387 /// [Bits 7:0] Number of physical address bits.
3388 ///
3389 /// @note
3390 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
3391 /// number supported should come from this field.
3392 ///
3393 UINT32 PhysicalAddressBits:8;
3394 ///
3395 /// [Bits 15:8] Number of linear address bits.
3396 ///
3397 UINT32 LinearAddressBits:8;
3398 UINT32 Reserved:16;
3399 } Bits;
3400 ///
3401 /// All bit fields as a 32-bit value
3402 ///
3403 UINT32 Uint32;
3404 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
3405
3406 #endif