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1 /** @file
2 MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.
21
22 **/
23
24 #ifndef __CORE2_MSR_H__
25 #define __CORE2_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Is Intel(R) Core(TM) 2 Processor Family?
31
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
34
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
37 **/
38 #define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
40 ( \
41 DisplayModel == 0x0F || \
42 DisplayModel == 0x17 \
43 ) \
44 )
45
46 /**
47 Shared. Model Specific Platform ID (R).
48
49 @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
54
55 <b>Example usage</b>
56 @code
57 MSR_CORE2_PLATFORM_ID_REGISTER Msr;
58
59 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
60 @endcode
61 @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
62 **/
63 #define MSR_CORE2_PLATFORM_ID 0x00000017
64
65 /**
66 MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
67 **/
68 typedef union {
69 ///
70 /// Individual bit fields
71 ///
72 struct {
73 UINT32 Reserved1:8;
74 ///
75 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
76 ///
77 UINT32 MaximumQualifiedRatio:5;
78 UINT32 Reserved2:19;
79 UINT32 Reserved3:18;
80 ///
81 /// [Bits 52:50] See Table 35-2.
82 ///
83 UINT32 PlatformId:3;
84 UINT32 Reserved4:11;
85 } Bits;
86 ///
87 /// All bit fields as a 64-bit value
88 ///
89 UINT64 Uint64;
90 } MSR_CORE2_PLATFORM_ID_REGISTER;
91
92
93 /**
94 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
95 processor features; (R) indicates current processor configuration.
96
97 @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)
98 @param EAX Lower 32-bits of MSR value.
99 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
100 @param EDX Upper 32-bits of MSR value.
101 Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
102
103 <b>Example usage</b>
104 @code
105 MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;
106
107 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
108 AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
109 @endcode
110 @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
111 **/
112 #define MSR_CORE2_EBL_CR_POWERON 0x0000002A
113
114 /**
115 MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
116 **/
117 typedef union {
118 ///
119 /// Individual bit fields
120 ///
121 struct {
122 UINT32 Reserved1:1;
123 ///
124 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
125 /// Note: Not all processor implements R/W.
126 ///
127 UINT32 DataErrorCheckingEnable:1;
128 ///
129 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
130 /// Note: Not all processor implements R/W.
131 ///
132 UINT32 ResponseErrorCheckingEnable:1;
133 ///
134 /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
135 /// all processor implements R/W.
136 ///
137 UINT32 MCERR_DriveEnable:1;
138 ///
139 /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
140 /// Not all processor implements R/W.
141 ///
142 UINT32 AddressParityEnable:1;
143 UINT32 Reserved2:1;
144 UINT32 Reserved3:1;
145 ///
146 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
147 /// all processor implements R/W.
148 ///
149 UINT32 BINIT_DriverEnable:1;
150 ///
151 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
152 ///
153 UINT32 OutputTriStateEnable:1;
154 ///
155 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
156 ///
157 UINT32 ExecuteBIST:1;
158 ///
159 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
160 ///
161 UINT32 MCERR_ObservationEnabled:1;
162 ///
163 /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
164 ///
165 UINT32 IntelTXTCapableChipset:1;
166 ///
167 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
168 ///
169 UINT32 BINIT_ObservationEnabled:1;
170 UINT32 Reserved4:1;
171 ///
172 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
173 ///
174 UINT32 ResetVector:1;
175 UINT32 Reserved5:1;
176 ///
177 /// [Bits 17:16] APIC Cluster ID (R/O).
178 ///
179 UINT32 APICClusterID:2;
180 ///
181 /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
182 /// Non-integer ratio.
183 ///
184 UINT32 NonIntegerBusRatio:1;
185 UINT32 Reserved6:1;
186 ///
187 /// [Bits 21:20] Symmetric Arbitration ID (R/O).
188 ///
189 UINT32 SymmetricArbitrationID:2;
190 ///
191 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
192 ///
193 UINT32 IntegerBusFrequencyRatio:5;
194 UINT32 Reserved7:5;
195 UINT32 Reserved8:32;
196 } Bits;
197 ///
198 /// All bit fields as a 32-bit value
199 ///
200 UINT32 Uint32;
201 ///
202 /// All bit fields as a 64-bit value
203 ///
204 UINT64 Uint64;
205 } MSR_CORE2_EBL_CR_POWERON_REGISTER;
206
207
208 /**
209 Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.
210
211 @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)
212 @param EAX Lower 32-bits of MSR value.
213 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
214 @param EDX Upper 32-bits of MSR value.
215 Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
216
217 <b>Example usage</b>
218 @code
219 MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;
220
221 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
222 AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
223 @endcode
224 @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
225 **/
226 #define MSR_CORE2_FEATURE_CONTROL 0x0000003A
227
228 /**
229 MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
230 **/
231 typedef union {
232 ///
233 /// Individual bit fields
234 ///
235 struct {
236 UINT32 Reserved1:3;
237 ///
238 /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
239 /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
240 /// visible and writeable while in SMM.
241 ///
242 UINT32 SMRREnable:1;
243 UINT32 Reserved2:28;
244 UINT32 Reserved3:32;
245 } Bits;
246 ///
247 /// All bit fields as a 32-bit value
248 ///
249 UINT32 Uint32;
250 ///
251 /// All bit fields as a 64-bit value
252 ///
253 UINT64 Uint64;
254 } MSR_CORE2_FEATURE_CONTROL_REGISTER;
255
256
257 /**
258 Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
259 record registers on the last branch record stack. The From_IP part of the
260 stack contains pointers to the source instruction. See also: - Last Branch
261 Record Stack TOS at 1C9H - Section 17.5.
262
263 @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
264 @param EAX Lower 32-bits of MSR value.
265 @param EDX Upper 32-bits of MSR value.
266
267 <b>Example usage</b>
268 @code
269 UINT64 Msr;
270
271 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
272 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
273 @endcode
274 @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
275 MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
276 MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
277 MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
278 @{
279 **/
280 #define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040
281 #define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041
282 #define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042
283 #define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043
284 /// @}
285
286
287 /**
288 Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
289 record registers on the last branch record stack. This To_IP part of the
290 stack contains pointers to the destination instruction.
291
292 @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
293 @param EAX Lower 32-bits of MSR value.
294 @param EDX Upper 32-bits of MSR value.
295
296 <b>Example usage</b>
297 @code
298 UINT64 Msr;
299
300 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
301 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
302 @endcode
303 @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
304 MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
305 MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
306 MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
307 @{
308 **/
309 #define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060
310 #define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061
311 #define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062
312 #define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063
313 /// @}
314
315
316 /**
317 Unique. System Management Mode Base Address register (WO in SMM)
318 Model-specific implementation of SMRR-like interface, read visible and write
319 only in SMM.
320
321 @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
322 @param EAX Lower 32-bits of MSR value.
323 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
324 @param EDX Upper 32-bits of MSR value.
325 Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
326
327 <b>Example usage</b>
328 @code
329 MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;
330
331 Msr.Uint64 = 0;
332 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
333 @endcode
334 @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
335 **/
336 #define MSR_CORE2_SMRR_PHYSBASE 0x000000A0
337
338 /**
339 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
340 **/
341 typedef union {
342 ///
343 /// Individual bit fields
344 ///
345 struct {
346 UINT32 Reserved1:12;
347 ///
348 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
349 ///
350 UINT32 PhysBase:20;
351 UINT32 Reserved2:32;
352 } Bits;
353 ///
354 /// All bit fields as a 32-bit value
355 ///
356 UINT32 Uint32;
357 ///
358 /// All bit fields as a 64-bit value
359 ///
360 UINT64 Uint64;
361 } MSR_CORE2_SMRR_PHYSBASE_REGISTER;
362
363
364 /**
365 Unique. System Management Mode Physical Address Mask register (WO in SMM)
366 Model-specific implementation of SMRR-like interface, read visible and write
367 only in SMM.
368
369 @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
370 @param EAX Lower 32-bits of MSR value.
371 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
372 @param EDX Upper 32-bits of MSR value.
373 Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
374
375 <b>Example usage</b>
376 @code
377 MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;
378
379 Msr.Uint64 = 0;
380 AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
381 @endcode
382 @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
383 **/
384 #define MSR_CORE2_SMRR_PHYSMASK 0x000000A1
385
386 /**
387 MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
388 **/
389 typedef union {
390 ///
391 /// Individual bit fields
392 ///
393 struct {
394 UINT32 Reserved1:11;
395 ///
396 /// [Bit 11] Valid. Physical address base and range mask are valid.
397 ///
398 UINT32 Valid:1;
399 ///
400 /// [Bits 31:12] PhysMask. SMRR physical address range mask.
401 ///
402 UINT32 PhysMask:20;
403 UINT32 Reserved2:32;
404 } Bits;
405 ///
406 /// All bit fields as a 32-bit value
407 ///
408 UINT32 Uint32;
409 ///
410 /// All bit fields as a 64-bit value
411 ///
412 UINT64 Uint64;
413 } MSR_CORE2_SMRR_PHYSMASK_REGISTER;
414
415
416 /**
417 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
418 bus clock speed for processors based on Intel Core microarchitecture:.
419
420 @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)
421 @param EAX Lower 32-bits of MSR value.
422 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
423 @param EDX Upper 32-bits of MSR value.
424 Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
425
426 <b>Example usage</b>
427 @code
428 MSR_CORE2_FSB_FREQ_REGISTER Msr;
429
430 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
431 @endcode
432 @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
433 **/
434 #define MSR_CORE2_FSB_FREQ 0x000000CD
435
436 /**
437 MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
438 **/
439 typedef union {
440 ///
441 /// Individual bit fields
442 ///
443 struct {
444 ///
445 /// [Bits 2:0] - Scalable Bus Speed
446 /// 101B: 100 MHz (FSB 400)
447 /// 001B: 133 MHz (FSB 533)
448 /// 011B: 167 MHz (FSB 667)
449 /// 010B: 200 MHz (FSB 800)
450 /// 000B: 267 MHz (FSB 1067)
451 /// 100B: 333 MHz (FSB 1333)
452 ///
453 /// 133.33 MHz should be utilized if performing calculation with System
454 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
455 /// performing calculation with System Bus Speed when encoding is 011B.
456 /// 266.67 MHz should be utilized if performing calculation with System
457 /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
458 /// performing calculation with System Bus Speed when encoding is 100B.
459 ///
460 UINT32 ScalableBusSpeed:3;
461 UINT32 Reserved1:29;
462 UINT32 Reserved2:32;
463 } Bits;
464 ///
465 /// All bit fields as a 32-bit value
466 ///
467 UINT32 Uint32;
468 ///
469 /// All bit fields as a 64-bit value
470 ///
471 UINT64 Uint64;
472 } MSR_CORE2_FSB_FREQ_REGISTER;
473
474
475 /**
476 Shared.
477
478 @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)
479 @param EAX Lower 32-bits of MSR value.
480 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
481 @param EDX Upper 32-bits of MSR value.
482 Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
483
484 <b>Example usage</b>
485 @code
486 MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;
487
488 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
489 AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
490 @endcode
491 @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
492 **/
493 #define MSR_CORE2_BBL_CR_CTL3 0x0000011E
494
495 /**
496 MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
497 **/
498 typedef union {
499 ///
500 /// Individual bit fields
501 ///
502 struct {
503 ///
504 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
505 /// Indicates if the L2 is hardware-disabled.
506 ///
507 UINT32 L2HardwareEnabled:1;
508 UINT32 Reserved1:7;
509 ///
510 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
511 /// Disabled (default) Until this bit is set the processor will not
512 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
513 ///
514 UINT32 L2Enabled:1;
515 UINT32 Reserved2:14;
516 ///
517 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
518 ///
519 UINT32 L2NotPresent:1;
520 UINT32 Reserved3:8;
521 UINT32 Reserved4:32;
522 } Bits;
523 ///
524 /// All bit fields as a 32-bit value
525 ///
526 UINT32 Uint32;
527 ///
528 /// All bit fields as a 64-bit value
529 ///
530 UINT64 Uint64;
531 } MSR_CORE2_BBL_CR_CTL3_REGISTER;
532
533
534 /**
535 Shared.
536
537 @param ECX MSR_CORE2_PERF_STATUS (0x00000198)
538 @param EAX Lower 32-bits of MSR value.
539 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
540 @param EDX Upper 32-bits of MSR value.
541 Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
542
543 <b>Example usage</b>
544 @code
545 MSR_CORE2_PERF_STATUS_REGISTER Msr;
546
547 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
548 AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
549 @endcode
550 @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
551 **/
552 #define MSR_CORE2_PERF_STATUS 0x00000198
553
554 /**
555 MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
556 **/
557 typedef union {
558 ///
559 /// Individual bit fields
560 ///
561 struct {
562 ///
563 /// [Bits 15:0] Current Performance State Value.
564 ///
565 UINT32 CurrentPerformanceStateValue:16;
566 UINT32 Reserved1:15;
567 ///
568 /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
569 /// is cleared.
570 ///
571 UINT32 XEOperation:1;
572 UINT32 Reserved2:8;
573 ///
574 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
575 /// configured for the processor.
576 ///
577 UINT32 MaximumBusRatio:5;
578 UINT32 Reserved3:1;
579 ///
580 /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
581 /// is enabled. Applies processors based on Enhanced Intel Core
582 /// microarchitecture.
583 ///
584 UINT32 NonIntegerBusRatio:1;
585 UINT32 Reserved4:17;
586 } Bits;
587 ///
588 /// All bit fields as a 64-bit value
589 ///
590 UINT64 Uint64;
591 } MSR_CORE2_PERF_STATUS_REGISTER;
592
593
594 /**
595 Unique.
596
597 @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)
598 @param EAX Lower 32-bits of MSR value.
599 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
600 @param EDX Upper 32-bits of MSR value.
601 Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
602
603 <b>Example usage</b>
604 @code
605 MSR_CORE2_THERM2_CTL_REGISTER Msr;
606
607 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
608 AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
609 @endcode
610 @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
611 **/
612 #define MSR_CORE2_THERM2_CTL 0x0000019D
613
614 /**
615 MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
616 **/
617 typedef union {
618 ///
619 /// Individual bit fields
620 ///
621 struct {
622 UINT32 Reserved1:16;
623 ///
624 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
625 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
626 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
627 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
628 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
629 ///
630 UINT32 TM_SELECT:1;
631 UINT32 Reserved2:15;
632 UINT32 Reserved3:32;
633 } Bits;
634 ///
635 /// All bit fields as a 32-bit value
636 ///
637 UINT32 Uint32;
638 ///
639 /// All bit fields as a 64-bit value
640 ///
641 UINT64 Uint64;
642 } MSR_CORE2_THERM2_CTL_REGISTER;
643
644
645 /**
646 Enable Misc. Processor Features (R/W) Allows a variety of processor
647 functions to be enabled and disabled.
648
649 @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
650 @param EAX Lower 32-bits of MSR value.
651 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
652 @param EDX Upper 32-bits of MSR value.
653 Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
654
655 <b>Example usage</b>
656 @code
657 MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;
658
659 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
660 AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
661 @endcode
662 @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
663 **/
664 #define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0
665
666 /**
667 MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
668 **/
669 typedef union {
670 ///
671 /// Individual bit fields
672 ///
673 struct {
674 ///
675 /// [Bit 0] Fast-Strings Enable See Table 35-2.
676 ///
677 UINT32 FastStrings:1;
678 UINT32 Reserved1:2;
679 ///
680 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
681 /// Table 35-2.
682 ///
683 UINT32 AutomaticThermalControlCircuit:1;
684 UINT32 Reserved2:3;
685 ///
686 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
687 ///
688 UINT32 PerformanceMonitoring:1;
689 UINT32 Reserved3:1;
690 ///
691 /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
692 /// hardware prefetcher operation on streams of data. When clear
693 /// (default), enables the prefetch queue. Disabling of the hardware
694 /// prefetcher may impact processor performance.
695 ///
696 UINT32 HardwarePrefetcherDisable:1;
697 ///
698 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
699 /// the processor to indicate a pending break event within the processor 0
700 /// = Indicates compatible FERR# signaling behavior This bit must be set
701 /// to 1 to support XAPIC interrupt model usage.
702 ///
703 UINT32 FERR:1;
704 ///
705 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
706 ///
707 UINT32 BTS:1;
708 ///
709 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
710 /// Table 35-2.
711 ///
712 UINT32 PEBS:1;
713 ///
714 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
715 /// thermal sensor indicates that the die temperature is at the
716 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
717 /// TM2 will reduce the bus to core ratio and voltage according to the
718 /// value last written to MSR_THERM2_CTL bits 15:0.
719 /// When this bit is clear (0, default), the processor does not change
720 /// the VID signals or the bus to core ratio when the processor enters a
721 /// thermally managed state. The BIOS must enable this feature if the
722 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
723 /// not set, this feature is not supported and BIOS must not alter the
724 /// contents of the TM2 bit location. The processor is operating out of
725 /// specification if both this bit and the TM1 bit are set to 0.
726 ///
727 UINT32 TM2:1;
728 UINT32 Reserved4:2;
729 ///
730 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
731 /// Table 35-2.
732 ///
733 UINT32 EIST:1;
734 UINT32 Reserved5:1;
735 ///
736 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
737 ///
738 UINT32 MONITOR:1;
739 ///
740 /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set
741 /// to 1, the processor fetches the cache line that contains data
742 /// currently required by the processor. When set to 0, the processor
743 /// fetches cache lines that comprise a cache line pair (128 bytes).
744 /// Single processor platforms should not set this bit. Server platforms
745 /// should set or clear this bit based on platform performance observed in
746 /// validation and testing. BIOS may contain a setup option that controls
747 /// the setting of this bit.
748 ///
749 UINT32 AdjacentCacheLinePrefetchDisable:1;
750 ///
751 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
752 /// (R/WO) When set, this bit causes the following bits to become
753 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
754 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
755 /// be set before an Enhanced Intel SpeedStep Technology transition is
756 /// requested. This bit is cleared on reset.
757 ///
758 UINT32 EISTLock:1;
759 UINT32 Reserved6:1;
760 ///
761 /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.
762 ///
763 UINT32 LimitCpuidMaxval:1;
764 ///
765 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
766 ///
767 UINT32 xTPR_Message_Disable:1;
768 UINT32 Reserved7:8;
769 UINT32 Reserved8:2;
770 ///
771 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
772 ///
773 UINT32 XD:1;
774 UINT32 Reserved9:2;
775 ///
776 /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
777 /// L1 data cache prefetcher is disabled. The default value after reset is
778 /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
779 /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
780 /// loads from the same line done within a time limit, the DCU prefetcher
781 /// assumes the next line will be required. The next line is prefetched in
782 /// to the L1 data cache from memory or L2.
783 ///
784 UINT32 DCUPrefetcherDisable:1;
785 ///
786 /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
787 /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
788 /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
789 /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
790 /// reports the processor's support of IDA is enabled. Note: the power-on
791 /// default value is used by BIOS to detect hardware support of IDA. If
792 /// power-on default value is 1, IDA is available in the processor. If
793 /// power-on default value is 0, IDA is not available.
794 ///
795 UINT32 IDADisable:1;
796 ///
797 /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
798 /// prefetcher is disabled. The default value after reset is 0. BIOS may
799 /// write '1' to disable this feature. The IP prefetcher is an L1 data
800 /// cache prefetcher. The IP prefetcher looks for sequential load history
801 /// to determine whether to prefetch the next expected data into the L1
802 /// cache from memory or L2.
803 ///
804 UINT32 IPPrefetcherDisable:1;
805 UINT32 Reserved10:24;
806 } Bits;
807 ///
808 /// All bit fields as a 64-bit value
809 ///
810 UINT64 Uint64;
811 } MSR_CORE2_IA32_MISC_ENABLE_REGISTER;
812
813
814 /**
815 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
816 that points to the MSR containing the most recent branch record. See
817 MSR_LASTBRANCH_0_FROM_IP (at 40H).
818
819 @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
820 @param EAX Lower 32-bits of MSR value.
821 @param EDX Upper 32-bits of MSR value.
822
823 <b>Example usage</b>
824 @code
825 UINT64 Msr;
826
827 Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
828 AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
829 @endcode
830 @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
831 **/
832 #define MSR_CORE2_LASTBRANCH_TOS 0x000001C9
833
834
835 /**
836 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
837 last branch instruction that the processor executed prior to the last
838 exception that was generated or the last interrupt that was handled.
839
840 @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)
841 @param EAX Lower 32-bits of MSR value.
842 @param EDX Upper 32-bits of MSR value.
843
844 <b>Example usage</b>
845 @code
846 UINT64 Msr;
847
848 Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
849 @endcode
850 @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
851 **/
852 #define MSR_CORE2_LER_FROM_LIP 0x000001DD
853
854
855 /**
856 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
857 to the target of the last branch instruction that the processor executed
858 prior to the last exception that was generated or the last interrupt that
859 was handled.
860
861 @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)
862 @param EAX Lower 32-bits of MSR value.
863 @param EDX Upper 32-bits of MSR value.
864
865 <b>Example usage</b>
866 @code
867 UINT64 Msr;
868
869 Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
870 @endcode
871 @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
872 **/
873 #define MSR_CORE2_LER_TO_LIP 0x000001DE
874
875
876 /**
877 Unique. Fixed-Function Performance Counter Register n (R/W).
878
879 @param ECX MSR_CORE2_PERF_FIXED_CTRn
880 @param EAX Lower 32-bits of MSR value.
881 @param EDX Upper 32-bits of MSR value.
882
883 <b>Example usage</b>
884 @code
885 UINT64 Msr;
886
887 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
888 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
889 @endcode
890 @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
891 MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
892 MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
893 @{
894 **/
895 #define MSR_CORE2_PERF_FIXED_CTR0 0x00000309
896 #define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A
897 #define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B
898 /// @}
899
900
901 /**
902 Unique. RO. This applies to processors that do not support architectural
903 perfmon version 2.
904
905 @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)
906 @param EAX Lower 32-bits of MSR value.
907 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
908 @param EDX Upper 32-bits of MSR value.
909 Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
910
911 <b>Example usage</b>
912 @code
913 MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;
914
915 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
916 AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
917 @endcode
918 @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
919 **/
920 #define MSR_CORE2_PERF_CAPABILITIES 0x00000345
921
922 /**
923 MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
924 **/
925 typedef union {
926 ///
927 /// Individual bit fields
928 ///
929 struct {
930 ///
931 /// [Bits 5:0] LBR Format. See Table 35-2.
932 ///
933 UINT32 LBR_FMT:6;
934 ///
935 /// [Bit 6] PEBS Record Format.
936 ///
937 UINT32 PEBS_FMT:1;
938 ///
939 /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.
940 ///
941 UINT32 PEBS_ARCH_REG:1;
942 UINT32 Reserved1:24;
943 UINT32 Reserved2:32;
944 } Bits;
945 ///
946 /// All bit fields as a 32-bit value
947 ///
948 UINT32 Uint32;
949 ///
950 /// All bit fields as a 64-bit value
951 ///
952 UINT64 Uint64;
953 } MSR_CORE2_PERF_CAPABILITIES_REGISTER;
954
955
956 /**
957 Unique. Fixed-Function-Counter Control Register (R/W).
958
959 @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
960 @param EAX Lower 32-bits of MSR value.
961 @param EDX Upper 32-bits of MSR value.
962
963 <b>Example usage</b>
964 @code
965 UINT64 Msr;
966
967 Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
968 AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
969 @endcode
970 @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
971 **/
972 #define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D
973
974
975 /**
976 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
977
978 @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
979 @param EAX Lower 32-bits of MSR value.
980 @param EDX Upper 32-bits of MSR value.
981
982 <b>Example usage</b>
983 @code
984 UINT64 Msr;
985
986 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);
987 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);
988 @endcode
989 @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
990 **/
991 #define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E
992
993
994 /**
995 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
996
997 @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
998 @param EAX Lower 32-bits of MSR value.
999 @param EDX Upper 32-bits of MSR value.
1000
1001 <b>Example usage</b>
1002 @code
1003 UINT64 Msr;
1004
1005 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
1006 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
1007 @endcode
1008 @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
1009 **/
1010 #define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F
1011
1012
1013 /**
1014 Unique. See Section 18.4.2, "Global Counter Control Facilities.".
1015
1016 @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
1017 @param EAX Lower 32-bits of MSR value.
1018 @param EDX Upper 32-bits of MSR value.
1019
1020 <b>Example usage</b>
1021 @code
1022 UINT64 Msr;
1023
1024 Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
1025 AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
1026 @endcode
1027 @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
1028 **/
1029 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390
1030
1031
1032 /**
1033 Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
1034 (PEBS).".
1035
1036 @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
1037 @param EAX Lower 32-bits of MSR value.
1038 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
1039 @param EDX Upper 32-bits of MSR value.
1040 Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
1041
1042 <b>Example usage</b>
1043 @code
1044 MSR_CORE2_PEBS_ENABLE_REGISTER Msr;
1045
1046 Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
1047 AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
1048 @endcode
1049 @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1050 **/
1051 #define MSR_CORE2_PEBS_ENABLE 0x000003F1
1052
1053 /**
1054 MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
1055 **/
1056 typedef union {
1057 ///
1058 /// Individual bit fields
1059 ///
1060 struct {
1061 ///
1062 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1063 ///
1064 UINT32 Enable:1;
1065 UINT32 Reserved1:31;
1066 UINT32 Reserved2:32;
1067 } Bits;
1068 ///
1069 /// All bit fields as a 32-bit value
1070 ///
1071 UINT32 Uint32;
1072 ///
1073 /// All bit fields as a 64-bit value
1074 ///
1075 UINT64 Uint64;
1076 } MSR_CORE2_PEBS_ENABLE_REGISTER;
1077
1078
1079 /**
1080 Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
1081 processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1082
1083 @param ECX MSR_CORE2_EMON_L3_CTR_CTLn
1084 @param EAX Lower 32-bits of MSR value.
1085 @param EDX Upper 32-bits of MSR value.
1086
1087 <b>Example usage</b>
1088 @code
1089 UINT64 Msr;
1090
1091 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
1092 AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
1093 @endcode
1094 @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
1095 MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
1096 MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
1097 MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
1098 MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
1099 MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
1100 MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
1101 MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
1102 @{
1103 **/
1104 #define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC
1105 #define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD
1106 #define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE
1107 #define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF
1108 #define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0
1109 #define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1
1110 #define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2
1111 #define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3
1112 /// @}
1113
1114
1115 /**
1116 Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
1117 7400 series (processor signature 06_1D) only. See Section 17.2.2.
1118
1119 @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
1120 @param EAX Lower 32-bits of MSR value.
1121 @param EDX Upper 32-bits of MSR value.
1122
1123 <b>Example usage</b>
1124 @code
1125 UINT64 Msr;
1126
1127 Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
1128 AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
1129 @endcode
1130 @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
1131 **/
1132 #define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8
1133
1134 #endif
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