2 MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.
24 #ifndef __HASWELL_E_MSR_H__
25 #define __HASWELL_E_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Core. C-State Configuration Control (R/W) Note: C-state values are processor
31 specific C-state code names, unrelated to MWAIT extension C-state parameters
32 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
34 @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
35 @param EAX Lower 32-bits of MSR value.
36 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
37 @param EDX Upper 32-bits of MSR value.
38 Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
42 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
44 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
45 AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
47 @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
49 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2
52 MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
56 /// Individual bit fields
60 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
61 /// processor-specific C-state code name (consuming the least power) for
62 /// the package. The default is set as factory-configured package C-state
63 /// limit. The following C-state code name encodings are supported: 000b:
64 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
65 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
66 /// supported by the processor are available.
71 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
76 /// [Bit 15] CFG Lock (R/WO).
81 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
83 UINT32 C3AutoDemotion
:1;
85 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
87 UINT32 C1AutoDemotion
:1;
89 /// [Bit 27] Enable C3 Undemotion (R/W).
91 UINT32 C3Undemotion
:1;
93 /// [Bit 28] Enable C1 Undemotion (R/W).
95 UINT32 C1Undemotion
:1;
97 /// [Bit 29] Package C State Demotion Enable (R/W).
99 UINT32 CStateDemotion
:1;
101 /// [Bit 30] Package C State UnDemotion Enable (R/W).
103 UINT32 CStateUndemotion
:1;
108 /// All bit fields as a 32-bit value
112 /// All bit fields as a 64-bit value
115 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
;
119 Thread. Global Machine Check Capability (R/O).
121 @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
122 @param EAX Lower 32-bits of MSR value.
123 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
124 @param EDX Upper 32-bits of MSR value.
125 Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
129 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;
131 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
133 @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
135 #define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179
138 MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
142 /// Individual bit fields
146 /// [Bits 7:0] Count.
150 /// [Bit 8] MCG_CTL_P.
154 /// [Bit 9] MCG_EXT_P.
158 /// [Bit 10] MCP_CMCI_P.
162 /// [Bit 11] MCG_TES_P.
167 /// [Bits 23:16] MCG_EXT_CNT.
169 UINT32 MCG_EXT_CNT
:8;
171 /// [Bit 24] MCG_SER_P.
175 /// [Bit 25] MCG_EM_P.
179 /// [Bit 26] MCG_ELOG_P.
186 /// All bit fields as a 32-bit value
190 /// All bit fields as a 64-bit value
193 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
;
197 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
198 Enhancement. Accessible only while in SMM.
200 @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
201 @param EAX Lower 32-bits of MSR value.
202 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
203 @param EDX Upper 32-bits of MSR value.
204 Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
208 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;
210 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
211 AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
213 @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
215 #define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D
218 MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
222 /// Individual bit fields
228 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
229 /// SMM code access restriction is supported and a host-space interface
230 /// available to SMM handler.
232 UINT32 SMM_Code_Access_Chk
:1;
234 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
235 /// SMM long flow indicator is supported and a host-space interface
236 /// available to SMM handler.
238 UINT32 Long_Flow_Indication
:1;
242 /// All bit fields as a 64-bit value
245 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
;
249 Package. MC Bank Error Configuration (R/W).
251 @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
252 @param EAX Lower 32-bits of MSR value.
253 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
254 @param EDX Upper 32-bits of MSR value.
255 Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
259 MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;
261 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
262 AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
264 @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
266 #define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F
269 MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
273 /// Individual bit fields
278 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
279 /// to log additional info in bits 36:32.
281 UINT32 MemErrorLogEnable
:1;
286 /// All bit fields as a 32-bit value
290 /// All bit fields as a 64-bit value
293 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER
;
297 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
298 RW if MSR_PLATFORM_INFO.[28] = 1.
300 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
301 @param EAX Lower 32-bits of MSR value.
302 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
303 @param EDX Upper 32-bits of MSR value.
304 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
308 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;
310 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
312 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
314 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD
317 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
321 /// Individual bit fields
325 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
326 /// limit of 1 core active.
330 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
331 /// limit of 2 core active.
335 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
336 /// limit of 3 core active.
340 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
341 /// limit of 4 core active.
345 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
346 /// limit of 5 core active.
350 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
351 /// limit of 6 core active.
355 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
356 /// limit of 7 core active.
360 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
361 /// limit of 8 core active.
366 /// All bit fields as a 64-bit value
369 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
;
373 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
374 RW if MSR_PLATFORM_INFO.[28] = 1.
376 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
377 @param EAX Lower 32-bits of MSR value.
378 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
379 @param EDX Upper 32-bits of MSR value.
380 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
384 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;
386 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
388 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
390 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE
393 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
397 /// Individual bit fields
401 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
402 /// limit of 9 core active.
406 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
407 /// limit of 10 core active.
411 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
412 /// limit of 11 core active.
416 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
417 /// limit of 12 core active.
421 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
422 /// limit of 13 core active.
426 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
427 /// limit of 14 core active.
431 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
432 /// limit of 15 core active.
436 /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
437 /// limit of 16 core active.
442 /// All bit fields as a 64-bit value
445 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
;
449 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
450 RW if MSR_PLATFORM_INFO.[28] = 1.
452 @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
453 @param EAX Lower 32-bits of MSR value.
454 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
455 @param EDX Upper 32-bits of MSR value.
456 Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
460 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;
462 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
464 @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
466 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF
469 MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
473 /// Individual bit fields
477 /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
478 /// limit of 17 core active.
482 /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
483 /// limit of 18 core active.
489 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
490 /// the processor uses override configuration specified in
491 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
492 /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
493 /// configuration (Default).
495 UINT32 TurboRatioLimitConfigurationSemaphore
:1;
498 /// All bit fields as a 64-bit value
501 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
;
505 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
506 15.3.2.4, "IA32_MCi_MISC MSRs.".
508 * Bank MC5 reports MC error from the Intel QPI 0 module.
509 * Bank MC6 reports MC error from the integrated I/O module.
510 * Bank MC7 reports MC error from the home agent HA 0.
511 * Bank MC8 reports MC error from the home agent HA 1.
512 * Banks MC9 through MC16 report MC error from each channel of the integrated
514 * Bank MC17 reports MC error from the following pair of CBo/L3 Slices
515 (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.
516 * Bank MC18 reports MC error from the following pair of CBo/L3 Slices
517 (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.
518 * Bank MC19 reports MC error from the following pair of CBo/L3 Slices
519 (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.
520 * Bank MC20 reports MC error from the Intel QPI 1 module.
521 * Bank MC21 reports MC error from the Intel QPI 2 module.
523 @param ECX MSR_HASWELL_E_MCi_CTL
524 @param EAX Lower 32-bits of MSR value.
525 @param EDX Upper 32-bits of MSR value.
531 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);
532 AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);
534 @note MSR_HASWELL_E_MC5_CTL is defined as MSR_MC5_CTL in SDM.
535 MSR_HASWELL_E_MC6_CTL is defined as MSR_MC6_CTL in SDM.
536 MSR_HASWELL_E_MC7_CTL is defined as MSR_MC7_CTL in SDM.
537 MSR_HASWELL_E_MC8_CTL is defined as MSR_MC8_CTL in SDM.
538 MSR_HASWELL_E_MC9_CTL is defined as MSR_MC9_CTL in SDM.
539 MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.
540 MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.
541 MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.
542 MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.
543 MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.
544 MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.
545 MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.
546 MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.
547 MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.
548 MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.
549 MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.
550 MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.
553 #define MSR_HASWELL_E_MC5_CTL 0x00000414
554 #define MSR_HASWELL_E_MC6_CTL 0x00000418
555 #define MSR_HASWELL_E_MC7_CTL 0x0000041C
556 #define MSR_HASWELL_E_MC8_CTL 0x00000420
557 #define MSR_HASWELL_E_MC9_CTL 0x00000424
558 #define MSR_HASWELL_E_MC10_CTL 0x00000428
559 #define MSR_HASWELL_E_MC11_CTL 0x0000042C
560 #define MSR_HASWELL_E_MC12_CTL 0x00000430
561 #define MSR_HASWELL_E_MC13_CTL 0x00000434
562 #define MSR_HASWELL_E_MC14_CTL 0x00000438
563 #define MSR_HASWELL_E_MC15_CTL 0x0000043C
564 #define MSR_HASWELL_E_MC16_CTL 0x00000440
565 #define MSR_HASWELL_E_MC17_CTL 0x00000444
566 #define MSR_HASWELL_E_MC18_CTL 0x00000448
567 #define MSR_HASWELL_E_MC19_CTL 0x0000044C
568 #define MSR_HASWELL_E_MC20_CTL 0x00000450
569 #define MSR_HASWELL_E_MC21_CTL 0x00000454
574 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
575 15.3.2.4, "IA32_MCi_MISC MSRs.".
577 @param ECX MSR_HASWELL_E_MCi_STATUS
578 @param EAX Lower 32-bits of MSR value.
579 @param EDX Upper 32-bits of MSR value.
585 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);
586 AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);
588 @note MSR_HASWELL_E_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
589 MSR_HASWELL_E_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
590 MSR_HASWELL_E_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
591 MSR_HASWELL_E_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
592 MSR_HASWELL_E_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
593 MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
594 MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
595 MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
596 MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
597 MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
598 MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
599 MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
600 MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
601 MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
602 MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
603 MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
604 MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
607 #define MSR_HASWELL_E_MC5_STATUS 0x00000415
608 #define MSR_HASWELL_E_MC6_STATUS 0x00000419
609 #define MSR_HASWELL_E_MC7_STATUS 0x0000041D
610 #define MSR_HASWELL_E_MC8_STATUS 0x00000421
611 #define MSR_HASWELL_E_MC9_STATUS 0x00000425
612 #define MSR_HASWELL_E_MC10_STATUS 0x00000429
613 #define MSR_HASWELL_E_MC11_STATUS 0x0000042D
614 #define MSR_HASWELL_E_MC12_STATUS 0x00000431
615 #define MSR_HASWELL_E_MC13_STATUS 0x00000435
616 #define MSR_HASWELL_E_MC14_STATUS 0x00000439
617 #define MSR_HASWELL_E_MC15_STATUS 0x0000043D
618 #define MSR_HASWELL_E_MC16_STATUS 0x00000441
619 #define MSR_HASWELL_E_MC17_STATUS 0x00000445
620 #define MSR_HASWELL_E_MC18_STATUS 0x00000449
621 #define MSR_HASWELL_E_MC19_STATUS 0x0000044D
622 #define MSR_HASWELL_E_MC20_STATUS 0x00000451
623 #define MSR_HASWELL_E_MC21_STATUS 0x00000455
627 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
628 15.3.2.4, "IA32_MCi_MISC MSRs.".
630 @param ECX MSR_HASWELL_E_MCi_ADDR
631 @param EAX Lower 32-bits of MSR value.
632 @param EDX Upper 32-bits of MSR value.
638 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);
639 AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);
641 @note MSR_HASWELL_E_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
642 MSR_HASWELL_E_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
643 MSR_HASWELL_E_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
644 MSR_HASWELL_E_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
645 MSR_HASWELL_E_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
646 MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
647 MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
648 MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
649 MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
650 MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
651 MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
652 MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
653 MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
654 MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
655 MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
656 MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
657 MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
660 #define MSR_HASWELL_E_MC5_ADDR 0x00000416
661 #define MSR_HASWELL_E_MC6_ADDR 0x0000041A
662 #define MSR_HASWELL_E_MC7_ADDR 0x0000041E
663 #define MSR_HASWELL_E_MC8_ADDR 0x00000422
664 #define MSR_HASWELL_E_MC9_ADDR 0x00000426
665 #define MSR_HASWELL_E_MC10_ADDR 0x0000042A
666 #define MSR_HASWELL_E_MC11_ADDR 0x0000042E
667 #define MSR_HASWELL_E_MC12_ADDR 0x00000432
668 #define MSR_HASWELL_E_MC13_ADDR 0x00000436
669 #define MSR_HASWELL_E_MC14_ADDR 0x0000043A
670 #define MSR_HASWELL_E_MC15_ADDR 0x0000043E
671 #define MSR_HASWELL_E_MC16_ADDR 0x00000442
672 #define MSR_HASWELL_E_MC17_ADDR 0x00000446
673 #define MSR_HASWELL_E_MC18_ADDR 0x0000044A
674 #define MSR_HASWELL_E_MC19_ADDR 0x0000044E
675 #define MSR_HASWELL_E_MC20_ADDR 0x00000452
676 #define MSR_HASWELL_E_MC21_ADDR 0x00000456
681 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
682 15.3.2.4, "IA32_MCi_MISC MSRs.".
684 @param ECX MSR_HASWELL_E_MCi_MISC
685 @param EAX Lower 32-bits of MSR value.
686 @param EDX Upper 32-bits of MSR value.
692 Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);
693 AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);
695 @note MSR_HASWELL_E_MC5_MISC is defined as MSR_MC5_MISC in SDM.
696 MSR_HASWELL_E_MC6_MISC is defined as MSR_MC6_MISC in SDM.
697 MSR_HASWELL_E_MC7_MISC is defined as MSR_MC7_MISC in SDM.
698 MSR_HASWELL_E_MC8_MISC is defined as MSR_MC8_MISC in SDM.
699 MSR_HASWELL_E_MC9_MISC is defined as MSR_MC9_MISC in SDM.
700 MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.
701 MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.
702 MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.
703 MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.
704 MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.
705 MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.
706 MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.
707 MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.
708 MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.
709 MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.
710 MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.
711 MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.
714 #define MSR_HASWELL_E_MC5_MISC 0x00000417
715 #define MSR_HASWELL_E_MC6_MISC 0x0000041B
716 #define MSR_HASWELL_E_MC7_MISC 0x0000041F
717 #define MSR_HASWELL_E_MC8_MISC 0x00000423
718 #define MSR_HASWELL_E_MC9_MISC 0x00000427
719 #define MSR_HASWELL_E_MC10_MISC 0x0000042B
720 #define MSR_HASWELL_E_MC11_MISC 0x0000042F
721 #define MSR_HASWELL_E_MC12_MISC 0x00000433
722 #define MSR_HASWELL_E_MC13_MISC 0x00000437
723 #define MSR_HASWELL_E_MC14_MISC 0x0000043B
724 #define MSR_HASWELL_E_MC15_MISC 0x0000043F
725 #define MSR_HASWELL_E_MC16_MISC 0x00000443
726 #define MSR_HASWELL_E_MC17_MISC 0x00000447
727 #define MSR_HASWELL_E_MC18_MISC 0x0000044B
728 #define MSR_HASWELL_E_MC19_MISC 0x0000044F
729 #define MSR_HASWELL_E_MC20_MISC 0x00000453
730 #define MSR_HASWELL_E_MC21_MISC 0x00000457
735 Package. Unit Multipliers used in RAPL Interfaces (R/O).
737 @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
738 @param EAX Lower 32-bits of MSR value.
739 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
740 @param EDX Upper 32-bits of MSR value.
741 Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
745 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;
747 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
749 @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
751 #define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606
754 MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
758 /// Individual bit fields
762 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
767 /// [Bits 12:8] Package. Energy Status Units Energy related information
768 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
769 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
772 UINT32 EnergyStatusUnits
:5;
775 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
783 /// All bit fields as a 32-bit value
787 /// All bit fields as a 64-bit value
790 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
;
794 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
797 @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
798 @param EAX Lower 32-bits of MSR value.
799 @param EDX Upper 32-bits of MSR value.
805 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
806 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
808 @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
810 #define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618
814 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
816 @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
817 @param EAX Lower 32-bits of MSR value.
818 @param EDX Upper 32-bits of MSR value.
824 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
826 @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
828 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
832 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
835 @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
836 @param EAX Lower 32-bits of MSR value.
837 @param EDX Upper 32-bits of MSR value.
843 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
845 @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
847 #define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B
851 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
853 @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
854 @param EAX Lower 32-bits of MSR value.
855 @param EDX Upper 32-bits of MSR value.
861 Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
862 AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
864 @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
866 #define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C
870 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
871 refers to processor core frequency).
873 @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
874 @param EAX Lower 32-bits of MSR value.
875 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
876 @param EDX Upper 32-bits of MSR value.
877 Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
881 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
883 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
884 AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
886 @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
888 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690
891 MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
895 /// Individual bit fields
899 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
900 /// reduced below the operating system request due to assertion of
901 /// external PROCHOT.
903 UINT32 PROCHOT_Status
:1;
905 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
906 /// operating system request due to a thermal event.
908 UINT32 ThermalStatus
:1;
910 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
911 /// reduced below the operating system request due to PBM limit.
913 UINT32 PowerBudgetManagementStatus
:1;
915 /// [Bit 3] Platform Configuration Services Status (R0) When set,
916 /// frequency is reduced below the operating system request due to PCS
919 UINT32 PlatformConfigurationServicesStatus
:1;
922 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
923 /// When set, frequency is reduced below the operating system request
924 /// because the processor has detected that utilization is low.
926 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
:1;
928 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
929 /// below the operating system request due to a thermal alert from the
930 /// Voltage Regulator.
932 UINT32 VRThermAlertStatus
:1;
935 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
936 /// reduced below the operating system request due to electrical design
937 /// point constraints (e.g. maximum electrical current consumption).
939 UINT32 ElectricalDesignPointStatus
:1;
942 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
943 /// below the operating system request due to Multi-Core Turbo limits.
945 UINT32 MultiCoreTurboStatus
:1;
948 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
949 /// below max non-turbo P1.
951 UINT32 FrequencyP1Status
:1;
953 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
954 /// set, frequency is reduced below max n-core turbo frequency.
956 UINT32 TurboFrequencyLimitingStatus
:1;
958 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
959 /// reduced below the operating system request.
961 UINT32 FrequencyLimitingStatus
:1;
963 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
964 /// has asserted since the log bit was last cleared. This log bit will
965 /// remain set until cleared by software writing 0.
967 UINT32 PROCHOT_Log
:1;
969 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
970 /// has asserted since the log bit was last cleared. This log bit will
971 /// remain set until cleared by software writing 0.
975 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM
976 /// Status bit has asserted since the log bit was last cleared. This log
977 /// bit will remain set until cleared by software writing 0.
979 UINT32 PowerBudgetManagementLog
:1;
981 /// [Bit 19] Platform Configuration Services Log When set, indicates that
982 /// the PCS Status bit has asserted since the log bit was last cleared.
983 /// This log bit will remain set until cleared by software writing 0.
985 UINT32 PlatformConfigurationServicesLog
:1;
988 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
989 /// indicates that the AUBFC Status bit has asserted since the log bit was
990 /// last cleared. This log bit will remain set until cleared by software
993 UINT32 AutonomousUtilizationBasedFrequencyControlLog
:1;
995 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
996 /// Alert Status bit has asserted since the log bit was last cleared. This
997 /// log bit will remain set until cleared by software writing 0.
999 UINT32 VRThermAlertLog
:1;
1002 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1003 /// Status bit has asserted since the log bit was last cleared. This log
1004 /// bit will remain set until cleared by software writing 0.
1006 UINT32 ElectricalDesignPointLog
:1;
1009 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core
1010 /// Turbo Status bit has asserted since the log bit was last cleared. This
1011 /// log bit will remain set until cleared by software writing 0.
1013 UINT32 MultiCoreTurboLog
:1;
1016 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
1017 /// Frequency P1 Status bit has asserted since the log bit was last
1018 /// cleared. This log bit will remain set until cleared by software
1021 UINT32 CoreFrequencyP1Log
:1;
1023 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
1024 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
1025 /// has asserted since the log bit was last cleared. This log bit will
1026 /// remain set until cleared by software writing 0.
1028 UINT32 TurboFrequencyLimitingLog
:1;
1030 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
1031 /// Frequency Limiting Status bit has asserted since the log bit was last
1032 /// cleared. This log bit will remain set until cleared by software
1035 UINT32 CoreFrequencyLimitingLog
:1;
1036 UINT32 Reserved9
:32;
1039 /// All bit fields as a 32-bit value
1043 /// All bit fields as a 64-bit value
1046 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
;
1050 THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
1051 ECX=0):EBX.PQM[bit 12] = 1.
1053 @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
1054 @param EAX Lower 32-bits of MSR value.
1055 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1056 @param EDX Upper 32-bits of MSR value.
1057 Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1059 <b>Example usage</b>
1061 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;
1063 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
1064 AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
1066 @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1068 #define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D
1071 MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
1075 /// Individual bit fields
1079 /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
1080 /// occupancy monitoring all other encoding reserved..
1083 UINT32 Reserved1
:24;
1085 /// [Bits 41:32] RMID (RW).
1088 UINT32 Reserved2
:22;
1091 /// All bit fields as a 64-bit value
1094 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
;
1098 THREAD. Resource Association Register (R/W)..
1100 @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
1101 @param EAX Lower 32-bits of MSR value.
1102 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1103 @param EDX Upper 32-bits of MSR value.
1104 Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1106 <b>Example usage</b>
1108 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;
1110 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
1111 AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
1113 @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1115 #define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F
1118 MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
1122 /// Individual bit fields
1126 /// [Bits 9:0] RMID.
1129 UINT32 Reserved1
:22;
1130 UINT32 Reserved2
:32;
1133 /// All bit fields as a 32-bit value
1137 /// All bit fields as a 64-bit value
1140 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
;
1144 Package. Uncore perfmon per-socket global control.
1146 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
1147 @param EAX Lower 32-bits of MSR value.
1148 @param EDX Upper 32-bits of MSR value.
1150 <b>Example usage</b>
1154 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
1155 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
1157 @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1159 #define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700
1163 Package. Uncore perfmon per-socket global status.
1165 @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
1166 @param EAX Lower 32-bits of MSR value.
1167 @param EDX Upper 32-bits of MSR value.
1169 <b>Example usage</b>
1173 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
1174 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
1176 @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1178 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701
1182 Package. Uncore perfmon per-socket global configuration.
1184 @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
1185 @param EAX Lower 32-bits of MSR value.
1186 @param EDX Upper 32-bits of MSR value.
1188 <b>Example usage</b>
1192 Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
1193 AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
1195 @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1197 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702
1201 Package. Uncore U-box UCLK fixed counter control.
1203 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
1204 @param EAX Lower 32-bits of MSR value.
1205 @param EDX Upper 32-bits of MSR value.
1207 <b>Example usage</b>
1211 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
1212 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
1214 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
1216 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703
1220 Package. Uncore U-box UCLK fixed counter.
1222 @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
1223 @param EAX Lower 32-bits of MSR value.
1224 @param EDX Upper 32-bits of MSR value.
1226 <b>Example usage</b>
1230 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
1231 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
1233 @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
1235 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704
1239 Package. Uncore U-box perfmon event select for U-box counter 0.
1241 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
1242 @param EAX Lower 32-bits of MSR value.
1243 @param EDX Upper 32-bits of MSR value.
1245 <b>Example usage</b>
1249 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
1250 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
1252 @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
1254 #define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705
1258 Package. Uncore U-box perfmon event select for U-box counter 1.
1260 @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
1261 @param EAX Lower 32-bits of MSR value.
1262 @param EDX Upper 32-bits of MSR value.
1264 <b>Example usage</b>
1268 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
1269 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
1271 @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
1273 #define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706
1277 Package. Uncore U-box perfmon U-box wide status.
1279 @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
1280 @param EAX Lower 32-bits of MSR value.
1281 @param EDX Upper 32-bits of MSR value.
1283 <b>Example usage</b>
1287 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
1288 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
1290 @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1292 #define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708
1296 Package. Uncore U-box perfmon counter 0.
1298 @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
1299 @param EAX Lower 32-bits of MSR value.
1300 @param EDX Upper 32-bits of MSR value.
1302 <b>Example usage</b>
1306 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
1307 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
1309 @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
1311 #define MSR_HASWELL_E_U_PMON_CTR0 0x00000709
1315 Package. Uncore U-box perfmon counter 1.
1317 @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
1318 @param EAX Lower 32-bits of MSR value.
1319 @param EDX Upper 32-bits of MSR value.
1321 <b>Example usage</b>
1325 Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
1326 AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
1328 @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
1330 #define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A
1334 Package. Uncore PCU perfmon for PCU-box-wide control.
1336 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
1337 @param EAX Lower 32-bits of MSR value.
1338 @param EDX Upper 32-bits of MSR value.
1340 <b>Example usage</b>
1344 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
1345 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
1347 @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
1349 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710
1353 Package. Uncore PCU perfmon event select for PCU counter 0.
1355 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
1356 @param EAX Lower 32-bits of MSR value.
1357 @param EDX Upper 32-bits of MSR value.
1359 <b>Example usage</b>
1363 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
1364 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
1366 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
1368 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711
1372 Package. Uncore PCU perfmon event select for PCU counter 1.
1374 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
1375 @param EAX Lower 32-bits of MSR value.
1376 @param EDX Upper 32-bits of MSR value.
1378 <b>Example usage</b>
1382 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
1383 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
1385 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
1387 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712
1391 Package. Uncore PCU perfmon event select for PCU counter 2.
1393 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
1394 @param EAX Lower 32-bits of MSR value.
1395 @param EDX Upper 32-bits of MSR value.
1397 <b>Example usage</b>
1401 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
1402 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
1404 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
1406 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713
1410 Package. Uncore PCU perfmon event select for PCU counter 3.
1412 @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
1413 @param EAX Lower 32-bits of MSR value.
1414 @param EDX Upper 32-bits of MSR value.
1416 <b>Example usage</b>
1420 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
1421 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
1423 @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
1425 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714
1429 Package. Uncore PCU perfmon box-wide filter.
1431 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
1432 @param EAX Lower 32-bits of MSR value.
1433 @param EDX Upper 32-bits of MSR value.
1435 <b>Example usage</b>
1439 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
1440 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
1442 @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
1444 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715
1448 Package. Uncore PCU perfmon box wide status.
1450 @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
1451 @param EAX Lower 32-bits of MSR value.
1452 @param EDX Upper 32-bits of MSR value.
1454 <b>Example usage</b>
1458 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
1459 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
1461 @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1463 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716
1467 Package. Uncore PCU perfmon counter 0.
1469 @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
1470 @param EAX Lower 32-bits of MSR value.
1471 @param EDX Upper 32-bits of MSR value.
1473 <b>Example usage</b>
1477 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
1478 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
1480 @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
1482 #define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717
1486 Package. Uncore PCU perfmon counter 1.
1488 @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
1489 @param EAX Lower 32-bits of MSR value.
1490 @param EDX Upper 32-bits of MSR value.
1492 <b>Example usage</b>
1496 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
1497 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
1499 @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
1501 #define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718
1505 Package. Uncore PCU perfmon counter 2.
1507 @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
1508 @param EAX Lower 32-bits of MSR value.
1509 @param EDX Upper 32-bits of MSR value.
1511 <b>Example usage</b>
1515 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
1516 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
1518 @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
1520 #define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719
1524 Package. Uncore PCU perfmon counter 3.
1526 @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
1527 @param EAX Lower 32-bits of MSR value.
1528 @param EDX Upper 32-bits of MSR value.
1530 <b>Example usage</b>
1534 Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
1535 AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
1537 @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
1539 #define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A
1543 Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
1545 @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
1546 @param EAX Lower 32-bits of MSR value.
1547 @param EDX Upper 32-bits of MSR value.
1549 <b>Example usage</b>
1553 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
1554 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
1556 @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
1558 #define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720
1562 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
1564 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
1565 @param EAX Lower 32-bits of MSR value.
1566 @param EDX Upper 32-bits of MSR value.
1568 <b>Example usage</b>
1572 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
1573 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
1575 @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
1577 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721
1581 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
1583 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
1584 @param EAX Lower 32-bits of MSR value.
1585 @param EDX Upper 32-bits of MSR value.
1587 <b>Example usage</b>
1591 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
1592 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
1594 @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
1596 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722
1600 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
1602 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
1603 @param EAX Lower 32-bits of MSR value.
1604 @param EDX Upper 32-bits of MSR value.
1606 <b>Example usage</b>
1610 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
1611 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
1613 @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
1615 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723
1619 Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
1621 @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
1622 @param EAX Lower 32-bits of MSR value.
1623 @param EDX Upper 32-bits of MSR value.
1625 <b>Example usage</b>
1629 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
1630 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
1632 @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
1634 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724
1638 Package. Uncore SBo 0 perfmon box-wide filter.
1640 @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
1641 @param EAX Lower 32-bits of MSR value.
1642 @param EDX Upper 32-bits of MSR value.
1644 <b>Example usage</b>
1648 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
1649 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
1651 @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
1653 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725
1657 Package. Uncore SBo 0 perfmon counter 0.
1659 @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
1660 @param EAX Lower 32-bits of MSR value.
1661 @param EDX Upper 32-bits of MSR value.
1663 <b>Example usage</b>
1667 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
1668 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
1670 @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
1672 #define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726
1676 Package. Uncore SBo 0 perfmon counter 1.
1678 @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
1679 @param EAX Lower 32-bits of MSR value.
1680 @param EDX Upper 32-bits of MSR value.
1682 <b>Example usage</b>
1686 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
1687 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
1689 @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
1691 #define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727
1695 Package. Uncore SBo 0 perfmon counter 2.
1697 @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
1698 @param EAX Lower 32-bits of MSR value.
1699 @param EDX Upper 32-bits of MSR value.
1701 <b>Example usage</b>
1705 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
1706 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
1708 @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
1710 #define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728
1714 Package. Uncore SBo 0 perfmon counter 3.
1716 @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
1717 @param EAX Lower 32-bits of MSR value.
1718 @param EDX Upper 32-bits of MSR value.
1720 <b>Example usage</b>
1724 Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
1725 AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
1727 @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
1729 #define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729
1733 Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
1735 @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
1736 @param EAX Lower 32-bits of MSR value.
1737 @param EDX Upper 32-bits of MSR value.
1739 <b>Example usage</b>
1743 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
1744 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
1746 @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
1748 #define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A
1752 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
1754 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
1755 @param EAX Lower 32-bits of MSR value.
1756 @param EDX Upper 32-bits of MSR value.
1758 <b>Example usage</b>
1762 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
1763 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
1765 @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
1767 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B
1771 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
1773 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
1774 @param EAX Lower 32-bits of MSR value.
1775 @param EDX Upper 32-bits of MSR value.
1777 <b>Example usage</b>
1781 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
1782 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
1784 @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
1786 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C
1790 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
1792 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
1793 @param EAX Lower 32-bits of MSR value.
1794 @param EDX Upper 32-bits of MSR value.
1796 <b>Example usage</b>
1800 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
1801 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
1803 @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
1805 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D
1809 Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
1811 @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
1812 @param EAX Lower 32-bits of MSR value.
1813 @param EDX Upper 32-bits of MSR value.
1815 <b>Example usage</b>
1819 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
1820 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
1822 @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
1824 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E
1828 Package. Uncore SBo 1 perfmon box-wide filter.
1830 @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
1831 @param EAX Lower 32-bits of MSR value.
1832 @param EDX Upper 32-bits of MSR value.
1834 <b>Example usage</b>
1838 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
1839 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
1841 @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
1843 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F
1847 Package. Uncore SBo 1 perfmon counter 0.
1849 @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
1850 @param EAX Lower 32-bits of MSR value.
1851 @param EDX Upper 32-bits of MSR value.
1853 <b>Example usage</b>
1857 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
1858 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
1860 @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
1862 #define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730
1866 Package. Uncore SBo 1 perfmon counter 1.
1868 @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
1869 @param EAX Lower 32-bits of MSR value.
1870 @param EDX Upper 32-bits of MSR value.
1872 <b>Example usage</b>
1876 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
1877 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
1879 @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
1881 #define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731
1885 Package. Uncore SBo 1 perfmon counter 2.
1887 @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
1888 @param EAX Lower 32-bits of MSR value.
1889 @param EDX Upper 32-bits of MSR value.
1891 <b>Example usage</b>
1895 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
1896 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
1898 @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
1900 #define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732
1904 Package. Uncore SBo 1 perfmon counter 3.
1906 @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
1907 @param EAX Lower 32-bits of MSR value.
1908 @param EDX Upper 32-bits of MSR value.
1910 <b>Example usage</b>
1914 Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
1915 AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
1917 @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
1919 #define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733
1923 Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
1925 @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
1926 @param EAX Lower 32-bits of MSR value.
1927 @param EDX Upper 32-bits of MSR value.
1929 <b>Example usage</b>
1933 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
1934 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
1936 @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
1938 #define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734
1942 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
1944 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
1945 @param EAX Lower 32-bits of MSR value.
1946 @param EDX Upper 32-bits of MSR value.
1948 <b>Example usage</b>
1952 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
1953 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
1955 @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
1957 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735
1961 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
1963 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
1964 @param EAX Lower 32-bits of MSR value.
1965 @param EDX Upper 32-bits of MSR value.
1967 <b>Example usage</b>
1971 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
1972 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
1974 @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
1976 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736
1980 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
1982 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
1983 @param EAX Lower 32-bits of MSR value.
1984 @param EDX Upper 32-bits of MSR value.
1986 <b>Example usage</b>
1990 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
1991 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
1993 @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
1995 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737
1999 Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
2001 @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
2002 @param EAX Lower 32-bits of MSR value.
2003 @param EDX Upper 32-bits of MSR value.
2005 <b>Example usage</b>
2009 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
2010 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
2012 @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
2014 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738
2018 Package. Uncore SBo 2 perfmon box-wide filter.
2020 @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
2021 @param EAX Lower 32-bits of MSR value.
2022 @param EDX Upper 32-bits of MSR value.
2024 <b>Example usage</b>
2028 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
2029 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
2031 @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
2033 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739
2037 Package. Uncore SBo 2 perfmon counter 0.
2039 @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
2040 @param EAX Lower 32-bits of MSR value.
2041 @param EDX Upper 32-bits of MSR value.
2043 <b>Example usage</b>
2047 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
2048 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
2050 @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
2052 #define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A
2056 Package. Uncore SBo 2 perfmon counter 1.
2058 @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
2059 @param EAX Lower 32-bits of MSR value.
2060 @param EDX Upper 32-bits of MSR value.
2062 <b>Example usage</b>
2066 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
2067 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
2069 @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
2071 #define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B
2075 Package. Uncore SBo 2 perfmon counter 2.
2077 @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
2078 @param EAX Lower 32-bits of MSR value.
2079 @param EDX Upper 32-bits of MSR value.
2081 <b>Example usage</b>
2085 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
2086 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
2088 @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
2090 #define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C
2094 Package. Uncore SBo 2 perfmon counter 3.
2096 @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
2097 @param EAX Lower 32-bits of MSR value.
2098 @param EDX Upper 32-bits of MSR value.
2100 <b>Example usage</b>
2104 Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
2105 AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
2107 @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
2109 #define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D
2113 Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
2115 @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
2116 @param EAX Lower 32-bits of MSR value.
2117 @param EDX Upper 32-bits of MSR value.
2119 <b>Example usage</b>
2123 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
2124 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
2126 @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
2128 #define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E
2132 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
2134 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
2135 @param EAX Lower 32-bits of MSR value.
2136 @param EDX Upper 32-bits of MSR value.
2138 <b>Example usage</b>
2142 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
2143 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
2145 @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
2147 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F
2151 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
2153 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
2154 @param EAX Lower 32-bits of MSR value.
2155 @param EDX Upper 32-bits of MSR value.
2157 <b>Example usage</b>
2161 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
2162 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
2164 @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
2166 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740
2170 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
2172 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
2173 @param EAX Lower 32-bits of MSR value.
2174 @param EDX Upper 32-bits of MSR value.
2176 <b>Example usage</b>
2180 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
2181 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
2183 @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
2185 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741
2189 Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
2191 @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
2192 @param EAX Lower 32-bits of MSR value.
2193 @param EDX Upper 32-bits of MSR value.
2195 <b>Example usage</b>
2199 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
2200 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
2202 @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
2204 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742
2208 Package. Uncore SBo 3 perfmon box-wide filter.
2210 @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
2211 @param EAX Lower 32-bits of MSR value.
2212 @param EDX Upper 32-bits of MSR value.
2214 <b>Example usage</b>
2218 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
2219 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
2221 @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
2223 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743
2227 Package. Uncore SBo 3 perfmon counter 0.
2229 @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
2230 @param EAX Lower 32-bits of MSR value.
2231 @param EDX Upper 32-bits of MSR value.
2233 <b>Example usage</b>
2237 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
2238 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
2240 @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
2242 #define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744
2246 Package. Uncore SBo 3 perfmon counter 1.
2248 @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
2249 @param EAX Lower 32-bits of MSR value.
2250 @param EDX Upper 32-bits of MSR value.
2252 <b>Example usage</b>
2256 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
2257 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
2259 @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
2261 #define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745
2265 Package. Uncore SBo 3 perfmon counter 2.
2267 @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
2268 @param EAX Lower 32-bits of MSR value.
2269 @param EDX Upper 32-bits of MSR value.
2271 <b>Example usage</b>
2275 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
2276 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
2278 @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
2280 #define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746
2284 Package. Uncore SBo 3 perfmon counter 3.
2286 @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
2287 @param EAX Lower 32-bits of MSR value.
2288 @param EDX Upper 32-bits of MSR value.
2290 <b>Example usage</b>
2294 Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
2295 AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
2297 @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
2299 #define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747
2303 Package. Uncore C-box 0 perfmon for box-wide control.
2305 @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
2306 @param EAX Lower 32-bits of MSR value.
2307 @param EDX Upper 32-bits of MSR value.
2309 <b>Example usage</b>
2313 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
2314 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
2316 @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
2318 #define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00
2322 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
2324 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
2325 @param EAX Lower 32-bits of MSR value.
2326 @param EDX Upper 32-bits of MSR value.
2328 <b>Example usage</b>
2332 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
2333 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
2335 @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
2337 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01
2341 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
2343 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
2344 @param EAX Lower 32-bits of MSR value.
2345 @param EDX Upper 32-bits of MSR value.
2347 <b>Example usage</b>
2351 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
2352 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
2354 @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
2356 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02
2360 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
2362 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
2363 @param EAX Lower 32-bits of MSR value.
2364 @param EDX Upper 32-bits of MSR value.
2366 <b>Example usage</b>
2370 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
2371 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
2373 @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
2375 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03
2379 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
2381 @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
2382 @param EAX Lower 32-bits of MSR value.
2383 @param EDX Upper 32-bits of MSR value.
2385 <b>Example usage</b>
2389 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
2390 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
2392 @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
2394 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04
2398 Package. Uncore C-box 0 perfmon box wide filter 0.
2400 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
2401 @param EAX Lower 32-bits of MSR value.
2402 @param EDX Upper 32-bits of MSR value.
2404 <b>Example usage</b>
2408 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
2409 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
2411 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
2413 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05
2417 Package. Uncore C-box 0 perfmon box wide filter 1.
2419 @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
2420 @param EAX Lower 32-bits of MSR value.
2421 @param EDX Upper 32-bits of MSR value.
2423 <b>Example usage</b>
2427 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
2428 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
2430 @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
2432 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06
2436 Package. Uncore C-box 0 perfmon box wide status.
2438 @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
2439 @param EAX Lower 32-bits of MSR value.
2440 @param EDX Upper 32-bits of MSR value.
2442 <b>Example usage</b>
2446 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
2447 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
2449 @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
2451 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07
2455 Package. Uncore C-box 0 perfmon counter 0.
2457 @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
2458 @param EAX Lower 32-bits of MSR value.
2459 @param EDX Upper 32-bits of MSR value.
2461 <b>Example usage</b>
2465 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
2466 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
2468 @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
2470 #define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08
2474 Package. Uncore C-box 0 perfmon counter 1.
2476 @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
2477 @param EAX Lower 32-bits of MSR value.
2478 @param EDX Upper 32-bits of MSR value.
2480 <b>Example usage</b>
2484 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
2485 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
2487 @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
2489 #define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09
2493 Package. Uncore C-box 0 perfmon counter 2.
2495 @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
2496 @param EAX Lower 32-bits of MSR value.
2497 @param EDX Upper 32-bits of MSR value.
2499 <b>Example usage</b>
2503 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
2504 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
2506 @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
2508 #define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A
2512 Package. Uncore C-box 0 perfmon counter 3.
2514 @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
2515 @param EAX Lower 32-bits of MSR value.
2516 @param EDX Upper 32-bits of MSR value.
2518 <b>Example usage</b>
2522 Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
2523 AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
2525 @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
2527 #define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B
2531 Package. Uncore C-box 1 perfmon for box-wide control.
2533 @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
2534 @param EAX Lower 32-bits of MSR value.
2535 @param EDX Upper 32-bits of MSR value.
2537 <b>Example usage</b>
2541 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
2542 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
2544 @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
2546 #define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10
2550 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
2552 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
2553 @param EAX Lower 32-bits of MSR value.
2554 @param EDX Upper 32-bits of MSR value.
2556 <b>Example usage</b>
2560 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
2561 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
2563 @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
2565 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11
2569 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
2571 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
2572 @param EAX Lower 32-bits of MSR value.
2573 @param EDX Upper 32-bits of MSR value.
2575 <b>Example usage</b>
2579 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
2580 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
2582 @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
2584 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12
2588 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
2590 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
2591 @param EAX Lower 32-bits of MSR value.
2592 @param EDX Upper 32-bits of MSR value.
2594 <b>Example usage</b>
2598 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
2599 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
2601 @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
2603 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13
2607 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
2609 @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
2610 @param EAX Lower 32-bits of MSR value.
2611 @param EDX Upper 32-bits of MSR value.
2613 <b>Example usage</b>
2617 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
2618 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
2620 @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
2622 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14
2626 Package. Uncore C-box 1 perfmon box wide filter 0.
2628 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
2629 @param EAX Lower 32-bits of MSR value.
2630 @param EDX Upper 32-bits of MSR value.
2632 <b>Example usage</b>
2636 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
2637 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
2639 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
2641 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15
2645 Package. Uncore C-box 1 perfmon box wide filter1.
2647 @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
2648 @param EAX Lower 32-bits of MSR value.
2649 @param EDX Upper 32-bits of MSR value.
2651 <b>Example usage</b>
2655 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
2656 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
2658 @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
2660 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16
2664 Package. Uncore C-box 1 perfmon box wide status.
2666 @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
2667 @param EAX Lower 32-bits of MSR value.
2668 @param EDX Upper 32-bits of MSR value.
2670 <b>Example usage</b>
2674 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
2675 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
2677 @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
2679 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17
2683 Package. Uncore C-box 1 perfmon counter 0.
2685 @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
2686 @param EAX Lower 32-bits of MSR value.
2687 @param EDX Upper 32-bits of MSR value.
2689 <b>Example usage</b>
2693 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
2694 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
2696 @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
2698 #define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18
2702 Package. Uncore C-box 1 perfmon counter 1.
2704 @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
2705 @param EAX Lower 32-bits of MSR value.
2706 @param EDX Upper 32-bits of MSR value.
2708 <b>Example usage</b>
2712 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
2713 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
2715 @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
2717 #define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19
2721 Package. Uncore C-box 1 perfmon counter 2.
2723 @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
2724 @param EAX Lower 32-bits of MSR value.
2725 @param EDX Upper 32-bits of MSR value.
2727 <b>Example usage</b>
2731 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
2732 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
2734 @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
2736 #define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A
2740 Package. Uncore C-box 1 perfmon counter 3.
2742 @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
2743 @param EAX Lower 32-bits of MSR value.
2744 @param EDX Upper 32-bits of MSR value.
2746 <b>Example usage</b>
2750 Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
2751 AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
2753 @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
2755 #define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B
2759 Package. Uncore C-box 2 perfmon for box-wide control.
2761 @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
2762 @param EAX Lower 32-bits of MSR value.
2763 @param EDX Upper 32-bits of MSR value.
2765 <b>Example usage</b>
2769 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
2770 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
2772 @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
2774 #define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20
2778 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
2780 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
2781 @param EAX Lower 32-bits of MSR value.
2782 @param EDX Upper 32-bits of MSR value.
2784 <b>Example usage</b>
2788 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
2789 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
2791 @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
2793 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21
2797 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
2799 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
2800 @param EAX Lower 32-bits of MSR value.
2801 @param EDX Upper 32-bits of MSR value.
2803 <b>Example usage</b>
2807 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
2808 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
2810 @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
2812 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22
2816 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
2818 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
2819 @param EAX Lower 32-bits of MSR value.
2820 @param EDX Upper 32-bits of MSR value.
2822 <b>Example usage</b>
2826 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
2827 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
2829 @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
2831 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23
2835 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
2837 @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
2838 @param EAX Lower 32-bits of MSR value.
2839 @param EDX Upper 32-bits of MSR value.
2841 <b>Example usage</b>
2845 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
2846 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
2848 @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
2850 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24
2854 Package. Uncore C-box 2 perfmon box wide filter 0.
2856 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
2857 @param EAX Lower 32-bits of MSR value.
2858 @param EDX Upper 32-bits of MSR value.
2860 <b>Example usage</b>
2864 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
2865 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
2867 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
2869 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25
2873 Package. Uncore C-box 2 perfmon box wide filter1.
2875 @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
2876 @param EAX Lower 32-bits of MSR value.
2877 @param EDX Upper 32-bits of MSR value.
2879 <b>Example usage</b>
2883 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
2884 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
2886 @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
2888 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26
2892 Package. Uncore C-box 2 perfmon box wide status.
2894 @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
2895 @param EAX Lower 32-bits of MSR value.
2896 @param EDX Upper 32-bits of MSR value.
2898 <b>Example usage</b>
2902 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
2903 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
2905 @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
2907 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27
2911 Package. Uncore C-box 2 perfmon counter 0.
2913 @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
2914 @param EAX Lower 32-bits of MSR value.
2915 @param EDX Upper 32-bits of MSR value.
2917 <b>Example usage</b>
2921 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
2922 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
2924 @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
2926 #define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28
2930 Package. Uncore C-box 2 perfmon counter 1.
2932 @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
2933 @param EAX Lower 32-bits of MSR value.
2934 @param EDX Upper 32-bits of MSR value.
2936 <b>Example usage</b>
2940 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
2941 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
2943 @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
2945 #define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29
2949 Package. Uncore C-box 2 perfmon counter 2.
2951 @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
2952 @param EAX Lower 32-bits of MSR value.
2953 @param EDX Upper 32-bits of MSR value.
2955 <b>Example usage</b>
2959 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
2960 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
2962 @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
2964 #define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A
2968 Package. Uncore C-box 2 perfmon counter 3.
2970 @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
2971 @param EAX Lower 32-bits of MSR value.
2972 @param EDX Upper 32-bits of MSR value.
2974 <b>Example usage</b>
2978 Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
2979 AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
2981 @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
2983 #define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B
2987 Package. Uncore C-box 3 perfmon for box-wide control.
2989 @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
2990 @param EAX Lower 32-bits of MSR value.
2991 @param EDX Upper 32-bits of MSR value.
2993 <b>Example usage</b>
2997 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
2998 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
3000 @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3002 #define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30
3006 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3008 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
3009 @param EAX Lower 32-bits of MSR value.
3010 @param EDX Upper 32-bits of MSR value.
3012 <b>Example usage</b>
3016 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
3017 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
3019 @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3021 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31
3025 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3027 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
3028 @param EAX Lower 32-bits of MSR value.
3029 @param EDX Upper 32-bits of MSR value.
3031 <b>Example usage</b>
3035 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
3036 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
3038 @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3040 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32
3044 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3046 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
3047 @param EAX Lower 32-bits of MSR value.
3048 @param EDX Upper 32-bits of MSR value.
3050 <b>Example usage</b>
3054 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
3055 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
3057 @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3059 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33
3063 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3065 @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
3066 @param EAX Lower 32-bits of MSR value.
3067 @param EDX Upper 32-bits of MSR value.
3069 <b>Example usage</b>
3073 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
3074 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
3076 @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3078 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34
3082 Package. Uncore C-box 3 perfmon box wide filter 0.
3084 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
3085 @param EAX Lower 32-bits of MSR value.
3086 @param EDX Upper 32-bits of MSR value.
3088 <b>Example usage</b>
3092 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
3093 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
3095 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
3097 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35
3101 Package. Uncore C-box 3 perfmon box wide filter1.
3103 @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
3104 @param EAX Lower 32-bits of MSR value.
3105 @param EDX Upper 32-bits of MSR value.
3107 <b>Example usage</b>
3111 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
3112 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
3114 @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
3116 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36
3120 Package. Uncore C-box 3 perfmon box wide status.
3122 @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
3123 @param EAX Lower 32-bits of MSR value.
3124 @param EDX Upper 32-bits of MSR value.
3126 <b>Example usage</b>
3130 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
3131 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
3133 @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
3135 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37
3139 Package. Uncore C-box 3 perfmon counter 0.
3141 @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
3142 @param EAX Lower 32-bits of MSR value.
3143 @param EDX Upper 32-bits of MSR value.
3145 <b>Example usage</b>
3149 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
3150 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
3152 @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3154 #define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38
3158 Package. Uncore C-box 3 perfmon counter 1.
3160 @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
3161 @param EAX Lower 32-bits of MSR value.
3162 @param EDX Upper 32-bits of MSR value.
3164 <b>Example usage</b>
3168 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
3169 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
3171 @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3173 #define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39
3177 Package. Uncore C-box 3 perfmon counter 2.
3179 @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
3180 @param EAX Lower 32-bits of MSR value.
3181 @param EDX Upper 32-bits of MSR value.
3183 <b>Example usage</b>
3187 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
3188 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
3190 @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3192 #define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A
3196 Package. Uncore C-box 3 perfmon counter 3.
3198 @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
3199 @param EAX Lower 32-bits of MSR value.
3200 @param EDX Upper 32-bits of MSR value.
3202 <b>Example usage</b>
3206 Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
3207 AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
3209 @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3211 #define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B
3215 Package. Uncore C-box 4 perfmon for box-wide control.
3217 @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
3218 @param EAX Lower 32-bits of MSR value.
3219 @param EDX Upper 32-bits of MSR value.
3221 <b>Example usage</b>
3225 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
3226 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
3228 @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3230 #define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40
3234 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3236 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
3237 @param EAX Lower 32-bits of MSR value.
3238 @param EDX Upper 32-bits of MSR value.
3240 <b>Example usage</b>
3244 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
3245 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
3247 @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3249 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41
3253 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3255 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
3256 @param EAX Lower 32-bits of MSR value.
3257 @param EDX Upper 32-bits of MSR value.
3259 <b>Example usage</b>
3263 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
3264 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
3266 @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3268 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42
3272 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3274 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
3275 @param EAX Lower 32-bits of MSR value.
3276 @param EDX Upper 32-bits of MSR value.
3278 <b>Example usage</b>
3282 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
3283 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
3285 @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3287 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43
3291 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3293 @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
3294 @param EAX Lower 32-bits of MSR value.
3295 @param EDX Upper 32-bits of MSR value.
3297 <b>Example usage</b>
3301 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
3302 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
3304 @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3306 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44
3310 Package. Uncore C-box 4 perfmon box wide filter 0.
3312 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
3313 @param EAX Lower 32-bits of MSR value.
3314 @param EDX Upper 32-bits of MSR value.
3316 <b>Example usage</b>
3320 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
3321 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
3323 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
3325 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45
3329 Package. Uncore C-box 4 perfmon box wide filter1.
3331 @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
3332 @param EAX Lower 32-bits of MSR value.
3333 @param EDX Upper 32-bits of MSR value.
3335 <b>Example usage</b>
3339 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
3340 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
3342 @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
3344 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46
3348 Package. Uncore C-box 4 perfmon box wide status.
3350 @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
3351 @param EAX Lower 32-bits of MSR value.
3352 @param EDX Upper 32-bits of MSR value.
3354 <b>Example usage</b>
3358 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
3359 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
3361 @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3363 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47
3367 Package. Uncore C-box 4 perfmon counter 0.
3369 @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
3370 @param EAX Lower 32-bits of MSR value.
3371 @param EDX Upper 32-bits of MSR value.
3373 <b>Example usage</b>
3377 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
3378 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
3380 @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3382 #define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48
3386 Package. Uncore C-box 4 perfmon counter 1.
3388 @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
3389 @param EAX Lower 32-bits of MSR value.
3390 @param EDX Upper 32-bits of MSR value.
3392 <b>Example usage</b>
3396 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
3397 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
3399 @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3401 #define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49
3405 Package. Uncore C-box 4 perfmon counter 2.
3407 @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
3408 @param EAX Lower 32-bits of MSR value.
3409 @param EDX Upper 32-bits of MSR value.
3411 <b>Example usage</b>
3415 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
3416 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
3418 @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3420 #define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A
3424 Package. Uncore C-box 4 perfmon counter 3.
3426 @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
3427 @param EAX Lower 32-bits of MSR value.
3428 @param EDX Upper 32-bits of MSR value.
3430 <b>Example usage</b>
3434 Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
3435 AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
3437 @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
3439 #define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B
3443 Package. Uncore C-box 5 perfmon for box-wide control.
3445 @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
3446 @param EAX Lower 32-bits of MSR value.
3447 @param EDX Upper 32-bits of MSR value.
3449 <b>Example usage</b>
3453 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
3454 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
3456 @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
3458 #define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50
3462 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
3464 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
3465 @param EAX Lower 32-bits of MSR value.
3466 @param EDX Upper 32-bits of MSR value.
3468 <b>Example usage</b>
3472 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
3473 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
3475 @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
3477 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51
3481 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
3483 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
3484 @param EAX Lower 32-bits of MSR value.
3485 @param EDX Upper 32-bits of MSR value.
3487 <b>Example usage</b>
3491 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
3492 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
3494 @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
3496 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52
3500 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
3502 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
3503 @param EAX Lower 32-bits of MSR value.
3504 @param EDX Upper 32-bits of MSR value.
3506 <b>Example usage</b>
3510 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
3511 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
3513 @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
3515 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53
3519 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
3521 @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
3522 @param EAX Lower 32-bits of MSR value.
3523 @param EDX Upper 32-bits of MSR value.
3525 <b>Example usage</b>
3529 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
3530 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
3532 @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
3534 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54
3538 Package. Uncore C-box 5 perfmon box wide filter 0.
3540 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
3541 @param EAX Lower 32-bits of MSR value.
3542 @param EDX Upper 32-bits of MSR value.
3544 <b>Example usage</b>
3548 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
3549 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
3551 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
3553 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55
3557 Package. Uncore C-box 5 perfmon box wide filter1.
3559 @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
3560 @param EAX Lower 32-bits of MSR value.
3561 @param EDX Upper 32-bits of MSR value.
3563 <b>Example usage</b>
3567 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
3568 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
3570 @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
3572 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56
3576 Package. Uncore C-box 5 perfmon box wide status.
3578 @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
3579 @param EAX Lower 32-bits of MSR value.
3580 @param EDX Upper 32-bits of MSR value.
3582 <b>Example usage</b>
3586 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
3587 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
3589 @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
3591 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57
3595 Package. Uncore C-box 5 perfmon counter 0.
3597 @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
3598 @param EAX Lower 32-bits of MSR value.
3599 @param EDX Upper 32-bits of MSR value.
3601 <b>Example usage</b>
3605 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
3606 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
3608 @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
3610 #define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58
3614 Package. Uncore C-box 5 perfmon counter 1.
3616 @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
3617 @param EAX Lower 32-bits of MSR value.
3618 @param EDX Upper 32-bits of MSR value.
3620 <b>Example usage</b>
3624 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
3625 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
3627 @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
3629 #define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59
3633 Package. Uncore C-box 5 perfmon counter 2.
3635 @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
3636 @param EAX Lower 32-bits of MSR value.
3637 @param EDX Upper 32-bits of MSR value.
3639 <b>Example usage</b>
3643 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
3644 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
3646 @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
3648 #define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A
3652 Package. Uncore C-box 5 perfmon counter 3.
3654 @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
3655 @param EAX Lower 32-bits of MSR value.
3656 @param EDX Upper 32-bits of MSR value.
3658 <b>Example usage</b>
3662 Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
3663 AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
3665 @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
3667 #define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B
3671 Package. Uncore C-box 6 perfmon for box-wide control.
3673 @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
3674 @param EAX Lower 32-bits of MSR value.
3675 @param EDX Upper 32-bits of MSR value.
3677 <b>Example usage</b>
3681 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
3682 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
3684 @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
3686 #define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60
3690 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
3692 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
3693 @param EAX Lower 32-bits of MSR value.
3694 @param EDX Upper 32-bits of MSR value.
3696 <b>Example usage</b>
3700 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
3701 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
3703 @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
3705 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61
3709 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
3711 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
3712 @param EAX Lower 32-bits of MSR value.
3713 @param EDX Upper 32-bits of MSR value.
3715 <b>Example usage</b>
3719 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
3720 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
3722 @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
3724 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62
3728 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
3730 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
3731 @param EAX Lower 32-bits of MSR value.
3732 @param EDX Upper 32-bits of MSR value.
3734 <b>Example usage</b>
3738 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
3739 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
3741 @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
3743 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63
3747 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
3749 @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
3750 @param EAX Lower 32-bits of MSR value.
3751 @param EDX Upper 32-bits of MSR value.
3753 <b>Example usage</b>
3757 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
3758 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
3760 @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
3762 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64
3766 Package. Uncore C-box 6 perfmon box wide filter 0.
3768 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
3769 @param EAX Lower 32-bits of MSR value.
3770 @param EDX Upper 32-bits of MSR value.
3772 <b>Example usage</b>
3776 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
3777 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
3779 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
3781 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65
3785 Package. Uncore C-box 6 perfmon box wide filter1.
3787 @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
3788 @param EAX Lower 32-bits of MSR value.
3789 @param EDX Upper 32-bits of MSR value.
3791 <b>Example usage</b>
3795 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
3796 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
3798 @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
3800 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66
3804 Package. Uncore C-box 6 perfmon box wide status.
3806 @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
3807 @param EAX Lower 32-bits of MSR value.
3808 @param EDX Upper 32-bits of MSR value.
3810 <b>Example usage</b>
3814 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
3815 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
3817 @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
3819 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67
3823 Package. Uncore C-box 6 perfmon counter 0.
3825 @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
3826 @param EAX Lower 32-bits of MSR value.
3827 @param EDX Upper 32-bits of MSR value.
3829 <b>Example usage</b>
3833 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
3834 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
3836 @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
3838 #define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68
3842 Package. Uncore C-box 6 perfmon counter 1.
3844 @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
3845 @param EAX Lower 32-bits of MSR value.
3846 @param EDX Upper 32-bits of MSR value.
3848 <b>Example usage</b>
3852 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
3853 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
3855 @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
3857 #define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69
3861 Package. Uncore C-box 6 perfmon counter 2.
3863 @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
3864 @param EAX Lower 32-bits of MSR value.
3865 @param EDX Upper 32-bits of MSR value.
3867 <b>Example usage</b>
3871 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
3872 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
3874 @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
3876 #define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A
3880 Package. Uncore C-box 6 perfmon counter 3.
3882 @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
3883 @param EAX Lower 32-bits of MSR value.
3884 @param EDX Upper 32-bits of MSR value.
3886 <b>Example usage</b>
3890 Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
3891 AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
3893 @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
3895 #define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B
3899 Package. Uncore C-box 7 perfmon for box-wide control.
3901 @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
3902 @param EAX Lower 32-bits of MSR value.
3903 @param EDX Upper 32-bits of MSR value.
3905 <b>Example usage</b>
3909 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
3910 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
3912 @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
3914 #define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70
3918 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
3920 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
3921 @param EAX Lower 32-bits of MSR value.
3922 @param EDX Upper 32-bits of MSR value.
3924 <b>Example usage</b>
3928 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
3929 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
3931 @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
3933 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71
3937 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
3939 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
3940 @param EAX Lower 32-bits of MSR value.
3941 @param EDX Upper 32-bits of MSR value.
3943 <b>Example usage</b>
3947 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
3948 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
3950 @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
3952 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72
3956 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
3958 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
3959 @param EAX Lower 32-bits of MSR value.
3960 @param EDX Upper 32-bits of MSR value.
3962 <b>Example usage</b>
3966 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
3967 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
3969 @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
3971 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73
3975 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
3977 @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
3978 @param EAX Lower 32-bits of MSR value.
3979 @param EDX Upper 32-bits of MSR value.
3981 <b>Example usage</b>
3985 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
3986 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
3988 @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
3990 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74
3994 Package. Uncore C-box 7 perfmon box wide filter 0.
3996 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
3997 @param EAX Lower 32-bits of MSR value.
3998 @param EDX Upper 32-bits of MSR value.
4000 <b>Example usage</b>
4004 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
4005 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
4007 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
4009 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75
4013 Package. Uncore C-box 7 perfmon box wide filter1.
4015 @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
4016 @param EAX Lower 32-bits of MSR value.
4017 @param EDX Upper 32-bits of MSR value.
4019 <b>Example usage</b>
4023 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
4024 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
4026 @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
4028 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76
4032 Package. Uncore C-box 7 perfmon box wide status.
4034 @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
4035 @param EAX Lower 32-bits of MSR value.
4036 @param EDX Upper 32-bits of MSR value.
4038 <b>Example usage</b>
4042 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
4043 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
4045 @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
4047 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77
4051 Package. Uncore C-box 7 perfmon counter 0.
4053 @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
4054 @param EAX Lower 32-bits of MSR value.
4055 @param EDX Upper 32-bits of MSR value.
4057 <b>Example usage</b>
4061 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
4062 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
4064 @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4066 #define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78
4070 Package. Uncore C-box 7 perfmon counter 1.
4072 @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
4073 @param EAX Lower 32-bits of MSR value.
4074 @param EDX Upper 32-bits of MSR value.
4076 <b>Example usage</b>
4080 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
4081 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
4083 @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4085 #define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79
4089 Package. Uncore C-box 7 perfmon counter 2.
4091 @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
4092 @param EAX Lower 32-bits of MSR value.
4093 @param EDX Upper 32-bits of MSR value.
4095 <b>Example usage</b>
4099 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
4100 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
4102 @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4104 #define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A
4108 Package. Uncore C-box 7 perfmon counter 3.
4110 @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
4111 @param EAX Lower 32-bits of MSR value.
4112 @param EDX Upper 32-bits of MSR value.
4114 <b>Example usage</b>
4118 Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
4119 AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
4121 @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4123 #define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B
4127 Package. Uncore C-box 8 perfmon local box wide control.
4129 @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
4130 @param EAX Lower 32-bits of MSR value.
4131 @param EDX Upper 32-bits of MSR value.
4133 <b>Example usage</b>
4137 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
4138 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
4140 @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
4142 #define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80
4146 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
4148 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
4149 @param EAX Lower 32-bits of MSR value.
4150 @param EDX Upper 32-bits of MSR value.
4152 <b>Example usage</b>
4156 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
4157 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
4159 @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
4161 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81
4165 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
4167 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
4168 @param EAX Lower 32-bits of MSR value.
4169 @param EDX Upper 32-bits of MSR value.
4171 <b>Example usage</b>
4175 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
4176 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
4178 @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
4180 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82
4184 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
4186 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
4187 @param EAX Lower 32-bits of MSR value.
4188 @param EDX Upper 32-bits of MSR value.
4190 <b>Example usage</b>
4194 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
4195 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
4197 @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
4199 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83
4203 Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
4205 @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
4206 @param EAX Lower 32-bits of MSR value.
4207 @param EDX Upper 32-bits of MSR value.
4209 <b>Example usage</b>
4213 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
4214 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
4216 @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
4218 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84
4222 Package. Uncore C-box 8 perfmon box wide filter0.
4224 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
4225 @param EAX Lower 32-bits of MSR value.
4226 @param EDX Upper 32-bits of MSR value.
4228 <b>Example usage</b>
4232 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
4233 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
4235 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
4237 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85
4241 Package. Uncore C-box 8 perfmon box wide filter1.
4243 @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
4244 @param EAX Lower 32-bits of MSR value.
4245 @param EDX Upper 32-bits of MSR value.
4247 <b>Example usage</b>
4251 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
4252 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
4254 @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
4256 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86
4260 Package. Uncore C-box 8 perfmon box wide status.
4262 @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
4263 @param EAX Lower 32-bits of MSR value.
4264 @param EDX Upper 32-bits of MSR value.
4266 <b>Example usage</b>
4270 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
4271 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
4273 @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
4275 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87
4279 Package. Uncore C-box 8 perfmon counter 0.
4281 @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
4282 @param EAX Lower 32-bits of MSR value.
4283 @param EDX Upper 32-bits of MSR value.
4285 <b>Example usage</b>
4289 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
4290 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
4292 @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
4294 #define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88
4298 Package. Uncore C-box 8 perfmon counter 1.
4300 @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
4301 @param EAX Lower 32-bits of MSR value.
4302 @param EDX Upper 32-bits of MSR value.
4304 <b>Example usage</b>
4308 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
4309 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
4311 @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
4313 #define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89
4317 Package. Uncore C-box 8 perfmon counter 2.
4319 @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
4320 @param EAX Lower 32-bits of MSR value.
4321 @param EDX Upper 32-bits of MSR value.
4323 <b>Example usage</b>
4327 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
4328 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
4330 @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
4332 #define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A
4336 Package. Uncore C-box 8 perfmon counter 3.
4338 @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
4339 @param EAX Lower 32-bits of MSR value.
4340 @param EDX Upper 32-bits of MSR value.
4342 <b>Example usage</b>
4346 Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
4347 AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
4349 @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
4351 #define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B
4355 Package. Uncore C-box 9 perfmon local box wide control.
4357 @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
4358 @param EAX Lower 32-bits of MSR value.
4359 @param EDX Upper 32-bits of MSR value.
4361 <b>Example usage</b>
4365 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
4366 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
4368 @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
4370 #define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90
4374 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
4376 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
4377 @param EAX Lower 32-bits of MSR value.
4378 @param EDX Upper 32-bits of MSR value.
4380 <b>Example usage</b>
4384 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
4385 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
4387 @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
4389 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91
4393 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
4395 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
4396 @param EAX Lower 32-bits of MSR value.
4397 @param EDX Upper 32-bits of MSR value.
4399 <b>Example usage</b>
4403 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
4404 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
4406 @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
4408 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92
4412 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
4414 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
4415 @param EAX Lower 32-bits of MSR value.
4416 @param EDX Upper 32-bits of MSR value.
4418 <b>Example usage</b>
4422 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
4423 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
4425 @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
4427 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93
4431 Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
4433 @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
4434 @param EAX Lower 32-bits of MSR value.
4435 @param EDX Upper 32-bits of MSR value.
4437 <b>Example usage</b>
4441 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
4442 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
4444 @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
4446 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94
4450 Package. Uncore C-box 9 perfmon box wide filter0.
4452 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
4453 @param EAX Lower 32-bits of MSR value.
4454 @param EDX Upper 32-bits of MSR value.
4456 <b>Example usage</b>
4460 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
4461 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
4463 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
4465 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95
4469 Package. Uncore C-box 9 perfmon box wide filter1.
4471 @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
4472 @param EAX Lower 32-bits of MSR value.
4473 @param EDX Upper 32-bits of MSR value.
4475 <b>Example usage</b>
4479 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
4480 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
4482 @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
4484 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96
4488 Package. Uncore C-box 9 perfmon box wide status.
4490 @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
4491 @param EAX Lower 32-bits of MSR value.
4492 @param EDX Upper 32-bits of MSR value.
4494 <b>Example usage</b>
4498 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
4499 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
4501 @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
4503 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97
4507 Package. Uncore C-box 9 perfmon counter 0.
4509 @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
4510 @param EAX Lower 32-bits of MSR value.
4511 @param EDX Upper 32-bits of MSR value.
4513 <b>Example usage</b>
4517 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
4518 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
4520 @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
4522 #define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98
4526 Package. Uncore C-box 9 perfmon counter 1.
4528 @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
4529 @param EAX Lower 32-bits of MSR value.
4530 @param EDX Upper 32-bits of MSR value.
4532 <b>Example usage</b>
4536 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
4537 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
4539 @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
4541 #define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99
4545 Package. Uncore C-box 9 perfmon counter 2.
4547 @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
4548 @param EAX Lower 32-bits of MSR value.
4549 @param EDX Upper 32-bits of MSR value.
4551 <b>Example usage</b>
4555 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
4556 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
4558 @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
4560 #define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A
4564 Package. Uncore C-box 9 perfmon counter 3.
4566 @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
4567 @param EAX Lower 32-bits of MSR value.
4568 @param EDX Upper 32-bits of MSR value.
4570 <b>Example usage</b>
4574 Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
4575 AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
4577 @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
4579 #define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B
4583 Package. Uncore C-box 10 perfmon local box wide control.
4585 @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
4586 @param EAX Lower 32-bits of MSR value.
4587 @param EDX Upper 32-bits of MSR value.
4589 <b>Example usage</b>
4593 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
4594 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
4596 @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
4598 #define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0
4602 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
4604 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
4605 @param EAX Lower 32-bits of MSR value.
4606 @param EDX Upper 32-bits of MSR value.
4608 <b>Example usage</b>
4612 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
4613 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
4615 @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
4617 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1
4621 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
4623 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
4624 @param EAX Lower 32-bits of MSR value.
4625 @param EDX Upper 32-bits of MSR value.
4627 <b>Example usage</b>
4631 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
4632 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
4634 @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
4636 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2
4640 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
4642 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
4643 @param EAX Lower 32-bits of MSR value.
4644 @param EDX Upper 32-bits of MSR value.
4646 <b>Example usage</b>
4650 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
4651 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
4653 @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
4655 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3
4659 Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
4661 @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
4662 @param EAX Lower 32-bits of MSR value.
4663 @param EDX Upper 32-bits of MSR value.
4665 <b>Example usage</b>
4669 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
4670 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
4672 @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
4674 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4
4678 Package. Uncore C-box 10 perfmon box wide filter0.
4680 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
4681 @param EAX Lower 32-bits of MSR value.
4682 @param EDX Upper 32-bits of MSR value.
4684 <b>Example usage</b>
4688 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
4689 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
4691 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
4693 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5
4697 Package. Uncore C-box 10 perfmon box wide filter1.
4699 @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
4700 @param EAX Lower 32-bits of MSR value.
4701 @param EDX Upper 32-bits of MSR value.
4703 <b>Example usage</b>
4707 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
4708 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
4710 @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
4712 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6
4716 Package. Uncore C-box 10 perfmon box wide status.
4718 @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
4719 @param EAX Lower 32-bits of MSR value.
4720 @param EDX Upper 32-bits of MSR value.
4722 <b>Example usage</b>
4726 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
4727 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
4729 @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
4731 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7
4735 Package. Uncore C-box 10 perfmon counter 0.
4737 @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
4738 @param EAX Lower 32-bits of MSR value.
4739 @param EDX Upper 32-bits of MSR value.
4741 <b>Example usage</b>
4745 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
4746 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
4748 @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
4750 #define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8
4754 Package. Uncore C-box 10 perfmon counter 1.
4756 @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
4757 @param EAX Lower 32-bits of MSR value.
4758 @param EDX Upper 32-bits of MSR value.
4760 <b>Example usage</b>
4764 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
4765 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
4767 @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
4769 #define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9
4773 Package. Uncore C-box 10 perfmon counter 2.
4775 @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
4776 @param EAX Lower 32-bits of MSR value.
4777 @param EDX Upper 32-bits of MSR value.
4779 <b>Example usage</b>
4783 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
4784 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
4786 @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
4788 #define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA
4792 Package. Uncore C-box 10 perfmon counter 3.
4794 @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
4795 @param EAX Lower 32-bits of MSR value.
4796 @param EDX Upper 32-bits of MSR value.
4798 <b>Example usage</b>
4802 Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
4803 AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
4805 @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
4807 #define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB
4811 Package. Uncore C-box 11 perfmon local box wide control.
4813 @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
4814 @param EAX Lower 32-bits of MSR value.
4815 @param EDX Upper 32-bits of MSR value.
4817 <b>Example usage</b>
4821 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
4822 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
4824 @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
4826 #define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0
4830 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
4832 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
4833 @param EAX Lower 32-bits of MSR value.
4834 @param EDX Upper 32-bits of MSR value.
4836 <b>Example usage</b>
4840 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
4841 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
4843 @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
4845 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1
4849 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
4851 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
4852 @param EAX Lower 32-bits of MSR value.
4853 @param EDX Upper 32-bits of MSR value.
4855 <b>Example usage</b>
4859 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
4860 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
4862 @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
4864 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2
4868 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
4870 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
4871 @param EAX Lower 32-bits of MSR value.
4872 @param EDX Upper 32-bits of MSR value.
4874 <b>Example usage</b>
4878 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
4879 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
4881 @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
4883 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3
4887 Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
4889 @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
4890 @param EAX Lower 32-bits of MSR value.
4891 @param EDX Upper 32-bits of MSR value.
4893 <b>Example usage</b>
4897 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
4898 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
4900 @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
4902 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4
4906 Package. Uncore C-box 11 perfmon box wide filter0.
4908 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
4909 @param EAX Lower 32-bits of MSR value.
4910 @param EDX Upper 32-bits of MSR value.
4912 <b>Example usage</b>
4916 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
4917 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
4919 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
4921 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5
4925 Package. Uncore C-box 11 perfmon box wide filter1.
4927 @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
4928 @param EAX Lower 32-bits of MSR value.
4929 @param EDX Upper 32-bits of MSR value.
4931 <b>Example usage</b>
4935 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
4936 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
4938 @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
4940 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6
4944 Package. Uncore C-box 11 perfmon box wide status.
4946 @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
4947 @param EAX Lower 32-bits of MSR value.
4948 @param EDX Upper 32-bits of MSR value.
4950 <b>Example usage</b>
4954 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
4955 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
4957 @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
4959 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7
4963 Package. Uncore C-box 11 perfmon counter 0.
4965 @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
4966 @param EAX Lower 32-bits of MSR value.
4967 @param EDX Upper 32-bits of MSR value.
4969 <b>Example usage</b>
4973 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
4974 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
4976 @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
4978 #define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8
4982 Package. Uncore C-box 11 perfmon counter 1.
4984 @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
4985 @param EAX Lower 32-bits of MSR value.
4986 @param EDX Upper 32-bits of MSR value.
4988 <b>Example usage</b>
4992 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
4993 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
4995 @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
4997 #define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9
5001 Package. Uncore C-box 11 perfmon counter 2.
5003 @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
5004 @param EAX Lower 32-bits of MSR value.
5005 @param EDX Upper 32-bits of MSR value.
5007 <b>Example usage</b>
5011 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
5012 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
5014 @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
5016 #define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA
5020 Package. Uncore C-box 11 perfmon counter 3.
5022 @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
5023 @param EAX Lower 32-bits of MSR value.
5024 @param EDX Upper 32-bits of MSR value.
5026 <b>Example usage</b>
5030 Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
5031 AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
5033 @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
5035 #define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB
5039 Package. Uncore C-box 12 perfmon local box wide control.
5041 @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
5042 @param EAX Lower 32-bits of MSR value.
5043 @param EDX Upper 32-bits of MSR value.
5045 <b>Example usage</b>
5049 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
5050 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
5052 @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
5054 #define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0
5058 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
5060 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
5061 @param EAX Lower 32-bits of MSR value.
5062 @param EDX Upper 32-bits of MSR value.
5064 <b>Example usage</b>
5068 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
5069 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
5071 @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
5073 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1
5077 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
5079 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
5080 @param EAX Lower 32-bits of MSR value.
5081 @param EDX Upper 32-bits of MSR value.
5083 <b>Example usage</b>
5087 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
5088 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
5090 @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
5092 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2
5096 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
5098 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
5099 @param EAX Lower 32-bits of MSR value.
5100 @param EDX Upper 32-bits of MSR value.
5102 <b>Example usage</b>
5106 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
5107 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
5109 @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
5111 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3
5115 Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
5117 @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
5118 @param EAX Lower 32-bits of MSR value.
5119 @param EDX Upper 32-bits of MSR value.
5121 <b>Example usage</b>
5125 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
5126 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
5128 @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
5130 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4
5134 Package. Uncore C-box 12 perfmon box wide filter0.
5136 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
5137 @param EAX Lower 32-bits of MSR value.
5138 @param EDX Upper 32-bits of MSR value.
5140 <b>Example usage</b>
5144 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
5145 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
5147 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
5149 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5
5153 Package. Uncore C-box 12 perfmon box wide filter1.
5155 @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
5156 @param EAX Lower 32-bits of MSR value.
5157 @param EDX Upper 32-bits of MSR value.
5159 <b>Example usage</b>
5163 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
5164 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
5166 @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
5168 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6
5172 Package. Uncore C-box 12 perfmon box wide status.
5174 @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
5175 @param EAX Lower 32-bits of MSR value.
5176 @param EDX Upper 32-bits of MSR value.
5178 <b>Example usage</b>
5182 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
5183 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
5185 @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
5187 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7
5191 Package. Uncore C-box 12 perfmon counter 0.
5193 @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
5194 @param EAX Lower 32-bits of MSR value.
5195 @param EDX Upper 32-bits of MSR value.
5197 <b>Example usage</b>
5201 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
5202 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
5204 @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
5206 #define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8
5210 Package. Uncore C-box 12 perfmon counter 1.
5212 @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
5213 @param EAX Lower 32-bits of MSR value.
5214 @param EDX Upper 32-bits of MSR value.
5216 <b>Example usage</b>
5220 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
5221 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
5223 @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
5225 #define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9
5229 Package. Uncore C-box 12 perfmon counter 2.
5231 @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
5232 @param EAX Lower 32-bits of MSR value.
5233 @param EDX Upper 32-bits of MSR value.
5235 <b>Example usage</b>
5239 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
5240 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
5242 @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
5244 #define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA
5248 Package. Uncore C-box 12 perfmon counter 3.
5250 @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
5251 @param EAX Lower 32-bits of MSR value.
5252 @param EDX Upper 32-bits of MSR value.
5254 <b>Example usage</b>
5258 Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
5259 AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
5261 @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
5263 #define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB
5267 Package. Uncore C-box 13 perfmon local box wide control.
5269 @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
5270 @param EAX Lower 32-bits of MSR value.
5271 @param EDX Upper 32-bits of MSR value.
5273 <b>Example usage</b>
5277 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
5278 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
5280 @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
5282 #define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0
5286 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
5288 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
5289 @param EAX Lower 32-bits of MSR value.
5290 @param EDX Upper 32-bits of MSR value.
5292 <b>Example usage</b>
5296 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
5297 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
5299 @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
5301 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1
5305 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
5307 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
5308 @param EAX Lower 32-bits of MSR value.
5309 @param EDX Upper 32-bits of MSR value.
5311 <b>Example usage</b>
5315 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
5316 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
5318 @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
5320 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2
5324 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
5326 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
5327 @param EAX Lower 32-bits of MSR value.
5328 @param EDX Upper 32-bits of MSR value.
5330 <b>Example usage</b>
5334 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
5335 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
5337 @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
5339 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3
5343 Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
5345 @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
5346 @param EAX Lower 32-bits of MSR value.
5347 @param EDX Upper 32-bits of MSR value.
5349 <b>Example usage</b>
5353 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
5354 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
5356 @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
5358 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4
5362 Package. Uncore C-box 13 perfmon box wide filter0.
5364 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
5365 @param EAX Lower 32-bits of MSR value.
5366 @param EDX Upper 32-bits of MSR value.
5368 <b>Example usage</b>
5372 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
5373 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
5375 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
5377 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5
5381 Package. Uncore C-box 13 perfmon box wide filter1.
5383 @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
5384 @param EAX Lower 32-bits of MSR value.
5385 @param EDX Upper 32-bits of MSR value.
5387 <b>Example usage</b>
5391 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
5392 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
5394 @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
5396 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6
5400 Package. Uncore C-box 13 perfmon box wide status.
5402 @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
5403 @param EAX Lower 32-bits of MSR value.
5404 @param EDX Upper 32-bits of MSR value.
5406 <b>Example usage</b>
5410 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
5411 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
5413 @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
5415 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7
5419 Package. Uncore C-box 13 perfmon counter 0.
5421 @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
5422 @param EAX Lower 32-bits of MSR value.
5423 @param EDX Upper 32-bits of MSR value.
5425 <b>Example usage</b>
5429 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
5430 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
5432 @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
5434 #define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8
5438 Package. Uncore C-box 13 perfmon counter 1.
5440 @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
5441 @param EAX Lower 32-bits of MSR value.
5442 @param EDX Upper 32-bits of MSR value.
5444 <b>Example usage</b>
5448 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
5449 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
5451 @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
5453 #define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9
5457 Package. Uncore C-box 13 perfmon counter 2.
5459 @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
5460 @param EAX Lower 32-bits of MSR value.
5461 @param EDX Upper 32-bits of MSR value.
5463 <b>Example usage</b>
5467 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
5468 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
5470 @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
5472 #define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA
5476 Package. Uncore C-box 13 perfmon counter 3.
5478 @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
5479 @param EAX Lower 32-bits of MSR value.
5480 @param EDX Upper 32-bits of MSR value.
5482 <b>Example usage</b>
5486 Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
5487 AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
5489 @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
5491 #define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB
5495 Package. Uncore C-box 14 perfmon local box wide control.
5497 @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
5498 @param EAX Lower 32-bits of MSR value.
5499 @param EDX Upper 32-bits of MSR value.
5501 <b>Example usage</b>
5505 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
5506 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
5508 @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
5510 #define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0
5514 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
5516 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
5517 @param EAX Lower 32-bits of MSR value.
5518 @param EDX Upper 32-bits of MSR value.
5520 <b>Example usage</b>
5524 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
5525 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
5527 @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
5529 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1
5533 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
5535 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
5536 @param EAX Lower 32-bits of MSR value.
5537 @param EDX Upper 32-bits of MSR value.
5539 <b>Example usage</b>
5543 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
5544 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
5546 @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
5548 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2
5552 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
5554 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
5555 @param EAX Lower 32-bits of MSR value.
5556 @param EDX Upper 32-bits of MSR value.
5558 <b>Example usage</b>
5562 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
5563 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
5565 @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
5567 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3
5571 Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
5573 @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
5574 @param EAX Lower 32-bits of MSR value.
5575 @param EDX Upper 32-bits of MSR value.
5577 <b>Example usage</b>
5581 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
5582 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
5584 @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
5586 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4
5590 Package. Uncore C-box 14 perfmon box wide filter0.
5592 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
5593 @param EAX Lower 32-bits of MSR value.
5594 @param EDX Upper 32-bits of MSR value.
5596 <b>Example usage</b>
5600 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
5601 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
5603 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
5605 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5
5609 Package. Uncore C-box 14 perfmon box wide filter1.
5611 @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
5612 @param EAX Lower 32-bits of MSR value.
5613 @param EDX Upper 32-bits of MSR value.
5615 <b>Example usage</b>
5619 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
5620 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
5622 @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
5624 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6
5628 Package. Uncore C-box 14 perfmon box wide status.
5630 @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
5631 @param EAX Lower 32-bits of MSR value.
5632 @param EDX Upper 32-bits of MSR value.
5634 <b>Example usage</b>
5638 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
5639 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
5641 @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
5643 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7
5647 Package. Uncore C-box 14 perfmon counter 0.
5649 @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
5650 @param EAX Lower 32-bits of MSR value.
5651 @param EDX Upper 32-bits of MSR value.
5653 <b>Example usage</b>
5657 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
5658 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
5660 @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
5662 #define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8
5666 Package. Uncore C-box 14 perfmon counter 1.
5668 @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
5669 @param EAX Lower 32-bits of MSR value.
5670 @param EDX Upper 32-bits of MSR value.
5672 <b>Example usage</b>
5676 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
5677 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
5679 @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
5681 #define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9
5685 Package. Uncore C-box 14 perfmon counter 2.
5687 @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
5688 @param EAX Lower 32-bits of MSR value.
5689 @param EDX Upper 32-bits of MSR value.
5691 <b>Example usage</b>
5695 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
5696 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
5698 @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
5700 #define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA
5704 Package. Uncore C-box 14 perfmon counter 3.
5706 @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
5707 @param EAX Lower 32-bits of MSR value.
5708 @param EDX Upper 32-bits of MSR value.
5710 <b>Example usage</b>
5714 Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
5715 AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
5717 @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
5719 #define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB
5723 Package. Uncore C-box 15 perfmon local box wide control.
5725 @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
5726 @param EAX Lower 32-bits of MSR value.
5727 @param EDX Upper 32-bits of MSR value.
5729 <b>Example usage</b>
5733 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
5734 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
5736 @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
5738 #define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0
5742 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
5744 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
5745 @param EAX Lower 32-bits of MSR value.
5746 @param EDX Upper 32-bits of MSR value.
5748 <b>Example usage</b>
5752 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
5753 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
5755 @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
5757 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1
5761 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
5763 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
5764 @param EAX Lower 32-bits of MSR value.
5765 @param EDX Upper 32-bits of MSR value.
5767 <b>Example usage</b>
5771 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
5772 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
5774 @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
5776 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2
5780 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
5782 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
5783 @param EAX Lower 32-bits of MSR value.
5784 @param EDX Upper 32-bits of MSR value.
5786 <b>Example usage</b>
5790 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
5791 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
5793 @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
5795 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3
5799 Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
5801 @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
5802 @param EAX Lower 32-bits of MSR value.
5803 @param EDX Upper 32-bits of MSR value.
5805 <b>Example usage</b>
5809 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
5810 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
5812 @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
5814 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4
5818 Package. Uncore C-box 15 perfmon box wide filter0.
5820 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
5821 @param EAX Lower 32-bits of MSR value.
5822 @param EDX Upper 32-bits of MSR value.
5824 <b>Example usage</b>
5828 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
5829 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
5831 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
5833 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5
5837 Package. Uncore C-box 15 perfmon box wide filter1.
5839 @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
5840 @param EAX Lower 32-bits of MSR value.
5841 @param EDX Upper 32-bits of MSR value.
5843 <b>Example usage</b>
5847 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
5848 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
5850 @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
5852 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6
5856 Package. Uncore C-box 15 perfmon box wide status.
5858 @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
5859 @param EAX Lower 32-bits of MSR value.
5860 @param EDX Upper 32-bits of MSR value.
5862 <b>Example usage</b>
5866 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
5867 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
5869 @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
5871 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7
5875 Package. Uncore C-box 15 perfmon counter 0.
5877 @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
5878 @param EAX Lower 32-bits of MSR value.
5879 @param EDX Upper 32-bits of MSR value.
5881 <b>Example usage</b>
5885 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
5886 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
5888 @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
5890 #define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8
5894 Package. Uncore C-box 15 perfmon counter 1.
5896 @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
5897 @param EAX Lower 32-bits of MSR value.
5898 @param EDX Upper 32-bits of MSR value.
5900 <b>Example usage</b>
5904 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
5905 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
5907 @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
5909 #define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9
5913 Package. Uncore C-box 15 perfmon counter 2.
5915 @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
5916 @param EAX Lower 32-bits of MSR value.
5917 @param EDX Upper 32-bits of MSR value.
5919 <b>Example usage</b>
5923 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
5924 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
5926 @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
5928 #define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA
5932 Package. Uncore C-box 15 perfmon counter 3.
5934 @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
5935 @param EAX Lower 32-bits of MSR value.
5936 @param EDX Upper 32-bits of MSR value.
5938 <b>Example usage</b>
5942 Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
5943 AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
5945 @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
5947 #define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB
5951 Package. Uncore C-box 16 perfmon for box-wide control.
5953 @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
5954 @param EAX Lower 32-bits of MSR value.
5955 @param EDX Upper 32-bits of MSR value.
5957 <b>Example usage</b>
5961 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
5962 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
5964 @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
5966 #define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00
5970 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
5972 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
5973 @param EAX Lower 32-bits of MSR value.
5974 @param EDX Upper 32-bits of MSR value.
5976 <b>Example usage</b>
5980 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
5981 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
5983 @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
5985 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01
5989 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
5991 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
5992 @param EAX Lower 32-bits of MSR value.
5993 @param EDX Upper 32-bits of MSR value.
5995 <b>Example usage</b>
5999 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
6000 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
6002 @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
6004 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02
6008 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
6010 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
6011 @param EAX Lower 32-bits of MSR value.
6012 @param EDX Upper 32-bits of MSR value.
6014 <b>Example usage</b>
6018 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
6019 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
6021 @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
6023 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03
6027 Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
6029 @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
6030 @param EAX Lower 32-bits of MSR value.
6031 @param EDX Upper 32-bits of MSR value.
6033 <b>Example usage</b>
6037 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
6038 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
6040 @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
6042 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04
6046 Package. Uncore C-box 16 perfmon box wide filter 0.
6048 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
6049 @param EAX Lower 32-bits of MSR value.
6050 @param EDX Upper 32-bits of MSR value.
6052 <b>Example usage</b>
6056 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
6057 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
6059 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
6061 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05
6065 Package. Uncore C-box 16 perfmon box wide filter 1.
6067 @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
6068 @param EAX Lower 32-bits of MSR value.
6069 @param EDX Upper 32-bits of MSR value.
6071 <b>Example usage</b>
6075 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
6076 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
6078 @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
6080 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06
6084 Package. Uncore C-box 16 perfmon box wide status.
6086 @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
6087 @param EAX Lower 32-bits of MSR value.
6088 @param EDX Upper 32-bits of MSR value.
6090 <b>Example usage</b>
6094 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
6095 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
6097 @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
6099 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07
6103 Package. Uncore C-box 16 perfmon counter 0.
6105 @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
6106 @param EAX Lower 32-bits of MSR value.
6107 @param EDX Upper 32-bits of MSR value.
6109 <b>Example usage</b>
6113 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
6114 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
6116 @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
6118 #define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08
6122 Package. Uncore C-box 16 perfmon counter 1.
6124 @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
6125 @param EAX Lower 32-bits of MSR value.
6126 @param EDX Upper 32-bits of MSR value.
6128 <b>Example usage</b>
6132 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
6133 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
6135 @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
6137 #define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09
6141 Package. Uncore C-box 16 perfmon counter 2.
6143 @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
6144 @param EAX Lower 32-bits of MSR value.
6145 @param EDX Upper 32-bits of MSR value.
6147 <b>Example usage</b>
6151 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
6152 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
6154 @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
6156 #define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A
6160 Package. Uncore C-box 16 perfmon counter 3.
6162 @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
6163 @param EAX Lower 32-bits of MSR value.
6164 @param EDX Upper 32-bits of MSR value.
6166 <b>Example usage</b>
6170 Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
6171 AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
6173 @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
6175 #define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B
6179 Package. Uncore C-box 17 perfmon for box-wide control.
6181 @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
6182 @param EAX Lower 32-bits of MSR value.
6183 @param EDX Upper 32-bits of MSR value.
6185 <b>Example usage</b>
6189 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
6190 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
6192 @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
6194 #define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10
6198 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
6200 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
6201 @param EAX Lower 32-bits of MSR value.
6202 @param EDX Upper 32-bits of MSR value.
6204 <b>Example usage</b>
6208 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
6209 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
6211 @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
6213 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11
6217 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
6219 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
6220 @param EAX Lower 32-bits of MSR value.
6221 @param EDX Upper 32-bits of MSR value.
6223 <b>Example usage</b>
6227 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
6228 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
6230 @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
6232 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12
6236 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
6238 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
6239 @param EAX Lower 32-bits of MSR value.
6240 @param EDX Upper 32-bits of MSR value.
6242 <b>Example usage</b>
6246 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
6247 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
6249 @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
6251 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13
6255 Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
6257 @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
6258 @param EAX Lower 32-bits of MSR value.
6259 @param EDX Upper 32-bits of MSR value.
6261 <b>Example usage</b>
6265 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
6266 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
6268 @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
6270 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14
6274 Package. Uncore C-box 17 perfmon box wide filter 0.
6276 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
6277 @param EAX Lower 32-bits of MSR value.
6278 @param EDX Upper 32-bits of MSR value.
6280 <b>Example usage</b>
6284 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
6285 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
6287 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
6289 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15
6293 Package. Uncore C-box 17 perfmon box wide filter1.
6295 @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
6296 @param EAX Lower 32-bits of MSR value.
6297 @param EDX Upper 32-bits of MSR value.
6299 <b>Example usage</b>
6303 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
6304 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
6306 @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
6308 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16
6311 Package. Uncore C-box 17 perfmon box wide status.
6313 @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
6314 @param EAX Lower 32-bits of MSR value.
6315 @param EDX Upper 32-bits of MSR value.
6317 <b>Example usage</b>
6321 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
6322 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
6324 @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
6326 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17
6330 Package. Uncore C-box 17 perfmon counter n.
6332 @param ECX MSR_HASWELL_E_C17_PMON_CTRn
6333 @param EAX Lower 32-bits of MSR value.
6334 @param EDX Upper 32-bits of MSR value.
6336 <b>Example usage</b>
6340 Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
6341 AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
6343 @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
6344 MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
6345 MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
6346 MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
6349 #define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18
6350 #define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19
6351 #define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A
6352 #define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B