2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.
24 #ifndef __SANDY_BRIDGE_MSR_H__
25 #define __SANDY_BRIDGE_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel processors based on the Sandy Bridge microarchitecture?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x2A || \
42 DisplayModel == 0x2D \
47 Thread. SMI Counter (R/O).
49 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
57 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
61 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
63 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
66 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
70 /// Individual bit fields
74 /// [Bits 31:0] SMI Count (R/O) Count SMIs.
80 /// All bit fields as a 32-bit value
84 /// All bit fields as a 64-bit value
87 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
;
91 Package. See http://biosbits.org.
93 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
94 @param EAX Lower 32-bits of MSR value.
95 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
96 @param EDX Upper 32-bits of MSR value.
97 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
101 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
103 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
104 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
106 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
108 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
111 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
115 /// Individual bit fields
120 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
121 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
124 UINT32 MaximumNonTurboRatio
:8;
127 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
128 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
129 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
130 /// Turbo mode is disabled.
134 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
135 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
136 /// and when set to 0, indicates TDP Limit for Turbo mode is not
143 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
144 /// minimum ratio (maximum efficiency) that the processor can operates, in
147 UINT32 MaximumEfficiencyRatio
:8;
151 /// All bit fields as a 64-bit value
154 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
;
158 Core. C-State Configuration Control (R/W) Note: C-state values are
159 processor specific C-state code names, unrelated to MWAIT extension C-state
160 parameters or ACPI CStates. See http://biosbits.org.
162 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
163 @param EAX Lower 32-bits of MSR value.
164 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
165 @param EDX Upper 32-bits of MSR value.
166 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
170 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
172 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
173 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
175 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
177 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
180 MSR information returned for MSR index
181 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
185 /// Individual bit fields
189 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
190 /// processor-specific C-state code name (consuming the least power). for
191 /// the package. The default is set as factory-configured package C-state
192 /// limit. The following C-state code name encodings are supported: 000b:
193 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
194 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
195 /// This field cannot be used to limit package C-state to C3.
200 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
201 /// IO_read instructions sent to IO register specified by
202 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
207 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
208 /// until next reset.
213 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
214 /// will conditionally demote C6/C7 requests to C3 based on uncore
215 /// auto-demote information.
217 UINT32 C3AutoDemotion
:1;
219 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
220 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
221 /// auto-demote information.
223 UINT32 C1AutoDemotion
:1;
225 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
228 UINT32 C3Undemotion
:1;
230 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
233 UINT32 C1Undemotion
:1;
238 /// All bit fields as a 32-bit value
242 /// All bit fields as a 64-bit value
245 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
249 Core. Power Management IO Redirection in C-state (R/W) See
252 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
253 @param EAX Lower 32-bits of MSR value.
254 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
255 @param EDX Upper 32-bits of MSR value.
256 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
260 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
262 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
263 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
265 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
267 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
270 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
274 /// Individual bit fields
278 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
279 /// visible to software for IO redirection. If IO MWAIT Redirection is
280 /// enabled, reads to this address will be consumed by the power
281 /// management logic and decoded to MWAIT instructions. When IO port
282 /// address redirection is enabled, this is the IO port address reported
283 /// to the OS/software.
287 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
288 /// maximum C-State code name to be included when IO read to MWAIT
289 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
290 /// is the max C-State to include 001b - C6 is the max C-State to include
291 /// 010b - C7 is the max C-State to include.
293 UINT32 CStateRange
:3;
298 /// All bit fields as a 32-bit value
302 /// All bit fields as a 64-bit value
305 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
;
309 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
310 handler to handle unsuccessful read of this MSR.
312 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
313 @param EAX Lower 32-bits of MSR value.
314 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
315 @param EDX Upper 32-bits of MSR value.
316 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
320 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
322 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
323 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
325 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
327 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
330 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
334 /// Individual bit fields
338 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
339 /// MSR, the configuration of AES instruction set availability is as
340 /// follows: 11b: AES instructions are not available until next RESET.
341 /// otherwise, AES instructions are available. Note, AES instruction set
342 /// is not available if read is unsuccessful. If the configuration is not
343 /// 01b, AES instruction can be mis-configured if a privileged agent
344 /// unintentionally writes 11b.
346 UINT32 AESConfiguration
:2;
351 /// All bit fields as a 32-bit value
355 /// All bit fields as a 64-bit value
358 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
;
362 Core. See Table 35-2; If CPUID.0AH:EAX[15:8] = 8.
364 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
365 @param EAX Lower 32-bits of MSR value.
366 @param EDX Upper 32-bits of MSR value.
372 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
373 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
375 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
376 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
377 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
378 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
381 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
382 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
383 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
384 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
391 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
392 @param EAX Lower 32-bits of MSR value.
393 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
394 @param EDX Upper 32-bits of MSR value.
395 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
399 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
401 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
402 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
404 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
406 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
409 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
413 /// Individual bit fields
418 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
419 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
421 UINT32 CoreVoltage
:16;
425 /// All bit fields as a 64-bit value
428 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
;
432 Thread. Clock Modulation (R/W) See Table 35-2 IA32_CLOCK_MODULATION MSR was
433 originally named IA32_THERM_CONTROL MSR.
435 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
436 @param EAX Lower 32-bits of MSR value.
437 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
438 @param EDX Upper 32-bits of MSR value.
439 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
443 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
445 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
446 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
448 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
450 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
453 MSR information returned for MSR index
454 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
458 /// Individual bit fields
462 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
465 UINT32 OnDemandClockModulationDutyCycle
:4;
467 /// [Bit 4] On demand Clock Modulation Enable (R/W).
469 UINT32 OnDemandClockModulationEnable
:1;
474 /// All bit fields as a 32-bit value
478 /// All bit fields as a 64-bit value
481 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
;
485 Enable Misc. Processor Features (R/W) Allows a variety of processor
486 functions to be enabled and disabled.
488 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
489 @param EAX Lower 32-bits of MSR value.
490 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
491 @param EDX Upper 32-bits of MSR value.
492 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
496 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
498 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
499 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
501 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
503 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
506 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
510 /// Individual bit fields
514 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
516 UINT32 FastStrings
:1;
519 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
521 UINT32 PerformanceMonitoring
:1;
524 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
528 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
534 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
540 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
545 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
547 UINT32 LimitCpuidMaxval
:1;
549 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
551 UINT32 xTPR_Message_Disable
:1;
555 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
560 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
561 /// that support Intel Turbo Boost Technology, the turbo mode feature is
562 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
563 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
564 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
565 /// the power-on default value is used by BIOS to detect hardware support
566 /// of turbo mode. If power-on default value is 1, turbo mode is available
567 /// in the processor. If power-on default value is 0, turbo mode is not
570 UINT32 TurboModeDisable
:1;
574 /// All bit fields as a 64-bit value
577 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
;
583 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
584 @param EAX Lower 32-bits of MSR value.
585 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
586 @param EDX Upper 32-bits of MSR value.
587 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
591 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
593 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
594 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
596 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
598 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
601 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
605 /// Individual bit fields
610 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
611 /// PROCHOT# will be asserted. The value is degree C.
613 UINT32 TemperatureTarget
:8;
618 /// All bit fields as a 32-bit value
622 /// All bit fields as a 64-bit value
625 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
629 Miscellaneous Feature Control (R/W).
631 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
632 @param EAX Lower 32-bits of MSR value.
633 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
634 @param EDX Upper 32-bits of MSR value.
635 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
639 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
641 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
642 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
644 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
646 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
649 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
653 /// Individual bit fields
657 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
658 /// L2 hardware prefetcher, which fetches additional lines of code or data
659 /// into the L2 cache.
661 UINT32 L2HardwarePrefetcherDisable
:1;
663 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
664 /// disables the adjacent cache line prefetcher, which fetches the cache
665 /// line that comprises a cache line pair (128 bytes).
667 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
669 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
670 /// the L1 data cache prefetcher, which fetches the next cache line into
673 UINT32 DCUHardwarePrefetcherDisable
:1;
675 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
676 /// data cache IP prefetcher, which uses sequential load history (based on
677 /// instruction Pointer of previous loads) to determine whether to
678 /// prefetch additional lines.
680 UINT32 DCUIPPrefetcherDisable
:1;
685 /// All bit fields as a 32-bit value
689 /// All bit fields as a 64-bit value
692 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
;
696 Thread. Offcore Response Event Select Register (R/W).
698 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
699 @param EAX Lower 32-bits of MSR value.
700 @param EDX Upper 32-bits of MSR value.
706 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
707 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
709 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
711 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
715 Thread. Offcore Response Event Select Register (R/W).
717 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
718 @param EAX Lower 32-bits of MSR value.
719 @param EDX Upper 32-bits of MSR value.
725 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
726 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
728 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
730 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
734 See http://biosbits.org.
736 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
737 @param EAX Lower 32-bits of MSR value.
738 @param EDX Upper 32-bits of MSR value.
744 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
745 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
747 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
749 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
753 Thread. Last Branch Record Filtering Select Register (R/W) See Section
754 17.7.2, "Filtering of Last Branch Records.".
756 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
757 @param EAX Lower 32-bits of MSR value.
758 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
759 @param EDX Upper 32-bits of MSR value.
760 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
764 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
766 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
767 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
769 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
771 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
774 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
778 /// Individual bit fields
782 /// [Bit 0] CPL_EQ_0.
786 /// [Bit 1] CPL_NEQ_0.
794 /// [Bit 3] NEAR_REL_CALL.
796 UINT32 NEAR_REL_CALL
:1;
798 /// [Bit 4] NEAR_IND_CALL.
800 UINT32 NEAR_IND_CALL
:1;
802 /// [Bit 5] NEAR_RET.
806 /// [Bit 6] NEAR_IND_JMP.
808 UINT32 NEAR_IND_JMP
:1;
810 /// [Bit 7] NEAR_REL_JMP.
812 UINT32 NEAR_REL_JMP
:1;
814 /// [Bit 8] FAR_BRANCH.
821 /// All bit fields as a 32-bit value
825 /// All bit fields as a 64-bit value
828 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
;
832 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
833 that points to the MSR containing the most recent branch record. See
834 MSR_LASTBRANCH_0_FROM_IP (at 680H).
836 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
837 @param EAX Lower 32-bits of MSR value.
838 @param EDX Upper 32-bits of MSR value.
844 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
845 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
847 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
849 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
853 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
854 last branch instruction that the processor executed prior to the last
855 exception that was generated or the last interrupt that was handled.
857 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
858 @param EAX Lower 32-bits of MSR value.
859 @param EDX Upper 32-bits of MSR value.
865 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
867 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
869 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
873 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
874 to the target of the last branch instruction that the processor executed
875 prior to the last exception that was generated or the last interrupt that
878 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
879 @param EAX Lower 32-bits of MSR value.
880 @param EDX Upper 32-bits of MSR value.
886 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
888 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
890 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
894 Core. See http://biosbits.org.
896 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
897 @param EAX Lower 32-bits of MSR value.
898 @param EDX Upper 32-bits of MSR value.
904 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
905 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
907 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
909 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
913 Package. Always 0 (CMCI not supported).
915 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)
916 @param EAX Lower 32-bits of MSR value.
917 @param EDX Upper 32-bits of MSR value.
923 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);
924 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);
926 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
928 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284
932 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
934 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
935 @param EAX Lower 32-bits of MSR value.
936 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
937 @param EDX Upper 32-bits of MSR value.
938 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
942 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
944 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);
945 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
947 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
949 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E
952 MSR information returned for MSR index
953 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS
957 /// Individual bit fields
961 /// [Bit 0] Thread. Ovf_PMC0.
965 /// [Bit 1] Thread. Ovf_PMC1.
969 /// [Bit 2] Thread. Ovf_PMC2.
973 /// [Bit 3] Thread. Ovf_PMC3.
977 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
981 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
985 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
989 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
994 /// [Bit 32] Thread. Ovf_FixedCtr0.
996 UINT32 Ovf_FixedCtr0
:1;
998 /// [Bit 33] Thread. Ovf_FixedCtr1.
1000 UINT32 Ovf_FixedCtr1
:1;
1002 /// [Bit 34] Thread. Ovf_FixedCtr2.
1004 UINT32 Ovf_FixedCtr2
:1;
1005 UINT32 Reserved2
:26;
1007 /// [Bit 61] Thread. Ovf_Uncore.
1009 UINT32 Ovf_Uncore
:1;
1011 /// [Bit 62] Thread. Ovf_BufDSSAVE.
1013 UINT32 Ovf_BufDSSAVE
:1;
1015 /// [Bit 63] Thread. CondChgd.
1020 /// All bit fields as a 64-bit value
1023 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
1027 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
1030 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
1031 @param EAX Lower 32-bits of MSR value.
1032 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1033 @param EDX Upper 32-bits of MSR value.
1034 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1036 <b>Example usage</b>
1038 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
1040 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
1041 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
1043 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
1045 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
1048 MSR information returned for MSR index
1049 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
1053 /// Individual bit fields
1057 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
1061 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
1065 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
1069 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
1073 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
1078 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
1083 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
1088 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
1092 UINT32 Reserved1
:24;
1094 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
1096 UINT32 FIXED_CTR0
:1;
1098 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
1100 UINT32 FIXED_CTR1
:1;
1102 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
1104 UINT32 FIXED_CTR2
:1;
1105 UINT32 Reserved2
:29;
1108 /// All bit fields as a 64-bit value
1111 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
;
1115 See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
1117 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
1118 @param EAX Lower 32-bits of MSR value.
1119 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1120 @param EDX Upper 32-bits of MSR value.
1121 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1123 <b>Example usage</b>
1125 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1127 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
1128 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1130 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
1132 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
1135 MSR information returned for MSR index
1136 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
1140 /// Individual bit fields
1144 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
1148 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
1152 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
1156 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
1160 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
1164 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
1168 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
1172 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
1175 UINT32 Reserved1
:24;
1177 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
1179 UINT32 Ovf_FixedCtr0
:1;
1181 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
1183 UINT32 Ovf_FixedCtr1
:1;
1185 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
1187 UINT32 Ovf_FixedCtr2
:1;
1188 UINT32 Reserved2
:26;
1190 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
1192 UINT32 Ovf_Uncore
:1;
1194 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
1196 UINT32 Ovf_BufDSSAVE
:1;
1198 /// [Bit 63] Thread. Set 1 to clear CondChgd.
1203 /// All bit fields as a 64-bit value
1206 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1210 Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
1212 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
1213 @param EAX Lower 32-bits of MSR value.
1214 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1215 @param EDX Upper 32-bits of MSR value.
1216 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1218 <b>Example usage</b>
1220 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1222 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
1223 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1225 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1227 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
1230 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
1234 /// Individual bit fields
1238 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1240 UINT32 PEBS_EN_PMC0
:1;
1242 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1244 UINT32 PEBS_EN_PMC1
:1;
1246 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1248 UINT32 PEBS_EN_PMC2
:1;
1250 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1252 UINT32 PEBS_EN_PMC3
:1;
1253 UINT32 Reserved1
:28;
1255 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1257 UINT32 LL_EN_PMC0
:1;
1259 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1261 UINT32 LL_EN_PMC1
:1;
1263 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1265 UINT32 LL_EN_PMC2
:1;
1267 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1269 UINT32 LL_EN_PMC3
:1;
1270 UINT32 Reserved2
:27;
1272 /// [Bit 63] Enable Precise Store. (R/W).
1277 /// All bit fields as a 64-bit value
1280 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
;
1284 Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring
1287 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
1288 @param EAX Lower 32-bits of MSR value.
1289 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1290 @param EDX Upper 32-bits of MSR value.
1291 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1293 <b>Example usage</b>
1295 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
1297 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
1298 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
1300 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1302 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
1305 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
1309 /// Individual bit fields
1313 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1314 /// that will be counted. (R/W).
1316 UINT32 MinimumThreshold
:16;
1317 UINT32 Reserved1
:16;
1318 UINT32 Reserved2
:32;
1321 /// All bit fields as a 32-bit value
1325 /// All bit fields as a 64-bit value
1328 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
;
1332 Package. Note: C-state values are processor specific C-state code names,
1333 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1334 Residency Counter. (R/O) Value since last reset that this package is in
1335 processor-specific C3 states. Count at the same frequency as the TSC.
1337 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
1338 @param EAX Lower 32-bits of MSR value.
1339 @param EDX Upper 32-bits of MSR value.
1341 <b>Example usage</b>
1345 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
1346 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
1348 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1350 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
1354 Package. Note: C-state values are processor specific C-state code names,
1355 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1356 Residency Counter. (R/O) Value since last reset that this package is in
1357 processor-specific C6 states. Count at the same frequency as the TSC.
1359 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
1360 @param EAX Lower 32-bits of MSR value.
1361 @param EDX Upper 32-bits of MSR value.
1363 <b>Example usage</b>
1367 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
1368 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
1370 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1372 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
1376 Package. Note: C-state values are processor specific C-state code names,
1377 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1378 Residency Counter. (R/O) Value since last reset that this package is in
1379 processor-specific C7 states. Count at the same frequency as the TSC.
1381 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
1382 @param EAX Lower 32-bits of MSR value.
1383 @param EDX Upper 32-bits of MSR value.
1385 <b>Example usage</b>
1389 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
1390 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
1392 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1394 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
1398 Core. Note: C-state values are processor specific C-state code names,
1399 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1400 Residency Counter. (R/O) Value since last reset that this core is in
1401 processor-specific C3 states. Count at the same frequency as the TSC.
1403 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
1404 @param EAX Lower 32-bits of MSR value.
1405 @param EDX Upper 32-bits of MSR value.
1407 <b>Example usage</b>
1411 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
1412 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
1414 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1416 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
1420 Core. Note: C-state values are processor specific C-state code names,
1421 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1422 Residency Counter. (R/O) Value since last reset that this core is in
1423 processor-specific C6 states. Count at the same frequency as the TSC.
1425 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
1426 @param EAX Lower 32-bits of MSR value.
1427 @param EDX Upper 32-bits of MSR value.
1429 <b>Example usage</b>
1433 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
1434 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
1436 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1438 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
1442 Core. Note: C-state values are processor specific C-state code names,
1443 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
1444 Residency Counter. (R/O) Value since last reset that this core is in
1445 processor-specific C7 states. Count at the same frequency as the TSC.
1447 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
1448 @param EAX Lower 32-bits of MSR value.
1449 @param EDX Upper 32-bits of MSR value.
1451 <b>Example usage</b>
1455 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
1456 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
1458 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
1460 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
1464 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1466 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)
1467 @param EAX Lower 32-bits of MSR value.
1468 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1469 @param EDX Upper 32-bits of MSR value.
1470 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1472 <b>Example usage</b>
1474 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;
1476 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);
1477 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);
1479 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
1481 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410
1484 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL
1488 /// Individual bit fields
1492 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
1493 /// hardware detected errors.
1495 UINT32 PCUHardwareError
:1;
1497 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
1498 /// controller detected errors.
1500 UINT32 PCUControllerError
:1;
1502 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
1503 /// firmware detected errors.
1505 UINT32 PCUFirmwareError
:1;
1506 UINT32 Reserved1
:29;
1507 UINT32 Reserved2
:32;
1510 /// All bit fields as a 32-bit value
1514 /// All bit fields as a 64-bit value
1517 } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
;
1521 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
1523 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1524 @param EAX Lower 32-bits of MSR value.
1525 @param EDX Upper 32-bits of MSR value.
1527 <b>Example usage</b>
1531 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
1533 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1535 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1539 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1542 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
1543 @param EAX Lower 32-bits of MSR value.
1544 @param EDX Upper 32-bits of MSR value.
1546 <b>Example usage</b>
1550 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
1552 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1554 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
1558 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1559 processor specific C-state code names, unrelated to MWAIT extension C-state
1560 parameters or ACPI CStates.
1562 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
1563 @param EAX Lower 32-bits of MSR value.
1564 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1565 @param EDX Upper 32-bits of MSR value.
1566 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1568 <b>Example usage</b>
1570 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
1572 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
1573 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
1575 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1577 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
1580 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
1584 /// Individual bit fields
1588 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1589 /// that should be used to decide if the package should be put into a
1590 /// package C3 state.
1592 UINT32 TimeLimit
:10;
1594 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1595 /// unit of the interrupt response time limit. The following time unit
1596 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1597 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1602 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1603 /// valid and can be used by the processor for package C-sate management.
1606 UINT32 Reserved2
:16;
1607 UINT32 Reserved3
:32;
1610 /// All bit fields as a 32-bit value
1614 /// All bit fields as a 64-bit value
1617 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
;
1621 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
1622 budget allocated for the package to exit from C6 to a C0 state, where
1623 interrupt request can be delivered to the core and serviced. Additional
1624 core-exit latency amy be applicable depending on the actual C-state the core
1625 is in. Note: C-state values are processor specific C-state code names,
1626 unrelated to MWAIT extension C-state parameters or ACPI CStates.
1628 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
1629 @param EAX Lower 32-bits of MSR value.
1630 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1631 @param EDX Upper 32-bits of MSR value.
1632 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1634 <b>Example usage</b>
1636 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
1638 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
1639 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
1641 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
1643 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
1646 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
1650 /// Individual bit fields
1654 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1655 /// that should be used to decide if the package should be put into a
1656 /// package C6 state.
1658 UINT32 TimeLimit
:10;
1660 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1661 /// unit of the interrupt response time limit. The following time unit
1662 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1663 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1668 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1669 /// valid and can be used by the processor for package C-sate management.
1672 UINT32 Reserved2
:16;
1673 UINT32 Reserved3
:32;
1676 /// All bit fields as a 32-bit value
1680 /// All bit fields as a 64-bit value
1683 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
;
1687 Package. Note: C-state values are processor specific C-state code names,
1688 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1689 Residency Counter. (R/O) Value since last reset that this package is in
1690 processor-specific C2 states. Count at the same frequency as the TSC.
1692 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
1693 @param EAX Lower 32-bits of MSR value.
1694 @param EDX Upper 32-bits of MSR value.
1696 <b>Example usage</b>
1700 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
1701 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
1703 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1705 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
1709 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1712 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
1713 @param EAX Lower 32-bits of MSR value.
1714 @param EDX Upper 32-bits of MSR value.
1716 <b>Example usage</b>
1720 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
1721 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
1723 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1725 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
1729 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1731 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
1732 @param EAX Lower 32-bits of MSR value.
1733 @param EDX Upper 32-bits of MSR value.
1735 <b>Example usage</b>
1739 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
1741 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1743 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
1747 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1750 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
1751 @param EAX Lower 32-bits of MSR value.
1752 @param EDX Upper 32-bits of MSR value.
1754 <b>Example usage</b>
1758 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
1759 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
1761 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1763 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
1767 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1770 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
1771 @param EAX Lower 32-bits of MSR value.
1772 @param EDX Upper 32-bits of MSR value.
1774 <b>Example usage</b>
1778 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
1779 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
1781 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1783 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
1787 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1790 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
1791 @param EAX Lower 32-bits of MSR value.
1792 @param EDX Upper 32-bits of MSR value.
1794 <b>Example usage</b>
1798 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
1800 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1802 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
1806 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1807 branch record registers on the last branch record stack. This part of the
1808 stack contains pointers to the source instruction. See also: - Last Branch
1809 Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section
1812 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
1813 @param EAX Lower 32-bits of MSR value.
1814 @param EDX Upper 32-bits of MSR value.
1816 <b>Example usage</b>
1820 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
1821 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
1823 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1824 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1825 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1826 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1827 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1828 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1829 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1830 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1831 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1832 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1833 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1834 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1835 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1836 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1837 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1838 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1841 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
1842 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
1843 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
1844 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
1845 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
1846 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
1847 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
1848 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
1849 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
1850 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
1851 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
1852 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
1853 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
1854 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
1855 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
1856 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
1861 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1862 record registers on the last branch record stack. This part of the stack
1863 contains pointers to the destination instruction.
1865 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
1866 @param EAX Lower 32-bits of MSR value.
1867 @param EDX Upper 32-bits of MSR value.
1869 <b>Example usage</b>
1873 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
1874 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
1876 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1877 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1878 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1879 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1880 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1881 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1882 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1883 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1884 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1885 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1886 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1887 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1888 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1889 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1890 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1891 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1894 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
1895 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
1896 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
1897 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
1898 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
1899 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
1900 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
1901 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
1902 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
1903 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
1904 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
1905 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
1906 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
1907 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
1908 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
1909 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
1914 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1915 RW if MSR_PLATFORM_INFO.[28] = 1.
1917 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
1918 @param EAX Lower 32-bits of MSR value.
1919 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1920 @param EDX Upper 32-bits of MSR value.
1921 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1923 <b>Example usage</b>
1925 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
1927 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
1929 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1931 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
1934 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
1938 /// Individual bit fields
1942 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1943 /// limit of 1 core active.
1947 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1948 /// limit of 2 core active.
1952 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1953 /// limit of 3 core active.
1957 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1958 /// limit of 4 core active.
1962 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
1963 /// limit of 5 core active.
1967 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
1968 /// limit of 6 core active.
1972 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
1973 /// limit of 7 core active.
1977 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
1978 /// limit of 8 core active.
1983 /// All bit fields as a 64-bit value
1986 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
;
1990 Package. Uncore PMU global control.
1992 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
1993 @param EAX Lower 32-bits of MSR value.
1994 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1995 @param EDX Upper 32-bits of MSR value.
1996 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1998 <b>Example usage</b>
2000 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
2002 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
2003 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
2005 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
2007 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
2010 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
2014 /// Individual bit fields
2018 /// [Bit 0] Slice 0 select.
2020 UINT32 PMI_Sel_Slice0
:1;
2022 /// [Bit 1] Slice 1 select.
2024 UINT32 PMI_Sel_Slice1
:1;
2026 /// [Bit 2] Slice 2 select.
2028 UINT32 PMI_Sel_Slice2
:1;
2030 /// [Bit 3] Slice 3 select.
2032 UINT32 PMI_Sel_Slice3
:1;
2034 /// [Bit 4] Slice 4 select.
2036 UINT32 PMI_Sel_Slice4
:1;
2037 UINT32 Reserved1
:14;
2038 UINT32 Reserved2
:10;
2040 /// [Bit 29] Enable all uncore counters.
2044 /// [Bit 30] Enable wake on PMI.
2048 /// [Bit 31] Enable Freezing counter when overflow.
2051 UINT32 Reserved3
:32;
2054 /// All bit fields as a 32-bit value
2058 /// All bit fields as a 64-bit value
2061 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2065 Package. Uncore PMU main status.
2067 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
2068 @param EAX Lower 32-bits of MSR value.
2069 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2070 @param EDX Upper 32-bits of MSR value.
2071 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2073 <b>Example usage</b>
2075 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2077 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
2078 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2080 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2082 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
2085 MSR information returned for MSR index
2086 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
2090 /// Individual bit fields
2094 /// [Bit 0] Fixed counter overflowed.
2098 /// [Bit 1] An ARB counter overflowed.
2103 /// [Bit 3] A CBox counter overflowed (on any slice).
2106 UINT32 Reserved2
:28;
2107 UINT32 Reserved3
:32;
2110 /// All bit fields as a 32-bit value
2114 /// All bit fields as a 64-bit value
2117 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2121 Package. Uncore fixed counter control (R/W).
2123 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
2124 @param EAX Lower 32-bits of MSR value.
2125 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2126 @param EDX Upper 32-bits of MSR value.
2127 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2129 <b>Example usage</b>
2131 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
2133 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
2134 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
2136 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
2138 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
2141 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
2145 /// Individual bit fields
2148 UINT32 Reserved1
:20;
2150 /// [Bit 20] Enable overflow propagation.
2152 UINT32 EnableOverflow
:1;
2155 /// [Bit 22] Enable counting.
2157 UINT32 EnableCounting
:1;
2159 UINT32 Reserved4
:32;
2162 /// All bit fields as a 32-bit value
2166 /// All bit fields as a 64-bit value
2169 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
;
2173 Package. Uncore fixed counter.
2175 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
2176 @param EAX Lower 32-bits of MSR value.
2177 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2178 @param EDX Upper 32-bits of MSR value.
2179 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2181 <b>Example usage</b>
2183 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
2185 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
2186 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
2188 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
2190 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
2193 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
2197 /// Individual bit fields
2201 /// [Bits 31:0] Current count.
2203 UINT32 CurrentCount
:32;
2205 /// [Bits 47:32] Current count.
2207 UINT32 CurrentCountHi
:16;
2211 /// All bit fields as a 64-bit value
2214 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
;
2218 Package. Uncore C-Box configuration information (R/O).
2220 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
2221 @param EAX Lower 32-bits of MSR value.
2222 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2223 @param EDX Upper 32-bits of MSR value.
2224 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2226 <b>Example usage</b>
2228 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
2230 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
2232 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
2234 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
2237 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
2241 /// Individual bit fields
2245 /// [Bits 3:0] Report the number of C-Box units with performance counters,
2246 /// including processor cores and processor graphics".
2249 UINT32 Reserved1
:28;
2250 UINT32 Reserved2
:32;
2253 /// All bit fields as a 32-bit value
2257 /// All bit fields as a 64-bit value
2260 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
;
2264 Package. Uncore Arb unit, performance counter 0.
2266 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
2267 @param EAX Lower 32-bits of MSR value.
2268 @param EDX Upper 32-bits of MSR value.
2270 <b>Example usage</b>
2274 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
2275 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
2277 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
2279 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
2283 Package. Uncore Arb unit, performance counter 1.
2285 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
2286 @param EAX Lower 32-bits of MSR value.
2287 @param EDX Upper 32-bits of MSR value.
2289 <b>Example usage</b>
2293 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
2294 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
2296 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
2298 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
2302 Package. Uncore Arb unit, counter 0 event select MSR.
2304 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
2305 @param EAX Lower 32-bits of MSR value.
2306 @param EDX Upper 32-bits of MSR value.
2308 <b>Example usage</b>
2312 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
2313 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
2315 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
2317 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
2321 Package. Uncore Arb unit, counter 1 event select MSR.
2323 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
2324 @param EAX Lower 32-bits of MSR value.
2325 @param EDX Upper 32-bits of MSR value.
2327 <b>Example usage</b>
2331 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
2332 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
2334 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
2336 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
2340 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
2341 budget allocated for the package to exit from C7 to a C0 state, where
2342 interrupt request can be delivered to the core and serviced. Additional
2343 core-exit latency amy be applicable depending on the actual C-state the core
2344 is in. Note: C-state values are processor specific C-state code names,
2345 unrelated to MWAIT extension C-state parameters or ACPI CStates.
2347 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
2348 @param EAX Lower 32-bits of MSR value.
2349 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2350 @param EDX Upper 32-bits of MSR value.
2351 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2353 <b>Example usage</b>
2355 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
2357 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
2358 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
2360 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
2362 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
2365 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
2369 /// Individual bit fields
2373 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
2374 /// that should be used to decide if the package should be put into a
2375 /// package C7 state.
2377 UINT32 TimeLimit
:10;
2379 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
2380 /// unit of the interrupt response time limit. The following time unit
2381 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
2382 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
2387 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
2388 /// valid and can be used by the processor for package C-sate management.
2391 UINT32 Reserved2
:16;
2392 UINT32 Reserved3
:32;
2395 /// All bit fields as a 32-bit value
2399 /// All bit fields as a 64-bit value
2402 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
;
2406 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2409 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
2410 @param EAX Lower 32-bits of MSR value.
2411 @param EDX Upper 32-bits of MSR value.
2413 <b>Example usage</b>
2417 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
2418 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
2420 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
2422 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
2426 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
2429 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
2430 @param EAX Lower 32-bits of MSR value.
2431 @param EDX Upper 32-bits of MSR value.
2433 <b>Example usage</b>
2437 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
2438 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
2440 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
2442 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
2446 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
2449 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
2450 @param EAX Lower 32-bits of MSR value.
2451 @param EDX Upper 32-bits of MSR value.
2453 <b>Example usage</b>
2457 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
2459 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
2461 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
2465 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2468 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
2469 @param EAX Lower 32-bits of MSR value.
2470 @param EDX Upper 32-bits of MSR value.
2472 <b>Example usage</b>
2476 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
2477 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
2479 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
2481 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
2485 Package. Uncore C-Box 0, counter n event select MSR.
2487 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn
2488 @param EAX Lower 32-bits of MSR value.
2489 @param EDX Upper 32-bits of MSR value.
2491 <b>Example usage</b>
2495 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
2496 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
2498 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2499 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2500 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.
2501 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.
2504 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
2505 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
2506 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702
2507 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703
2512 Package. Uncore C-Box n, unit status for counter 0-3.
2514 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS
2515 @param EAX Lower 32-bits of MSR value.
2516 @param EDX Upper 32-bits of MSR value.
2518 <b>Example usage</b>
2522 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);
2523 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);
2525 @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.
2526 MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.
2527 MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.
2528 MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.
2529 MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.
2532 #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705
2533 #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715
2534 #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725
2535 #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735
2536 #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745
2541 Package. Uncore C-Box 0, performance counter n.
2543 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn
2544 @param EAX Lower 32-bits of MSR value.
2545 @param EDX Upper 32-bits of MSR value.
2547 <b>Example usage</b>
2551 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
2552 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
2554 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2555 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2556 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.
2557 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.
2560 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
2561 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
2562 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708
2563 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709
2568 Package. Uncore C-Box 1, counter n event select MSR.
2570 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn
2571 @param EAX Lower 32-bits of MSR value.
2572 @param EDX Upper 32-bits of MSR value.
2574 <b>Example usage</b>
2578 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
2579 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
2581 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2582 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2583 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.
2584 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.
2587 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2588 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2589 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712
2590 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713
2595 Package. Uncore C-Box 1, performance counter n.
2597 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn
2598 @param EAX Lower 32-bits of MSR value.
2599 @param EDX Upper 32-bits of MSR value.
2601 <b>Example usage</b>
2605 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
2606 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
2608 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2609 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2610 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.
2611 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.
2614 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
2615 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
2616 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718
2617 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719
2622 Package. Uncore C-Box 2, counter n event select MSR.
2624 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn
2625 @param EAX Lower 32-bits of MSR value.
2626 @param EDX Upper 32-bits of MSR value.
2628 <b>Example usage</b>
2632 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
2633 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
2635 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2636 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2637 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.
2638 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.
2641 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2642 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2643 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722
2644 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723
2649 Package. Uncore C-Box 2, performance counter n.
2651 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn
2652 @param EAX Lower 32-bits of MSR value.
2653 @param EDX Upper 32-bits of MSR value.
2655 <b>Example usage</b>
2659 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
2660 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
2662 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2663 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2664 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.
2665 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.
2668 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
2669 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
2670 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728
2671 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729
2676 Package. Uncore C-Box 3, counter n event select MSR.
2678 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn
2679 @param EAX Lower 32-bits of MSR value.
2680 @param EDX Upper 32-bits of MSR value.
2682 <b>Example usage</b>
2686 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
2687 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
2689 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2690 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2691 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.
2692 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.
2695 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2696 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2697 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732
2698 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733
2703 Package. Uncore C-Box 3, performance counter n.
2705 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn
2706 @param EAX Lower 32-bits of MSR value.
2707 @param EDX Upper 32-bits of MSR value.
2709 <b>Example usage</b>
2713 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
2714 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
2716 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2717 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2718 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.
2719 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.
2722 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
2723 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
2724 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738
2725 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739
2730 Package. Uncore C-Box 4, counter n event select MSR.
2732 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn
2733 @param EAX Lower 32-bits of MSR value.
2734 @param EDX Upper 32-bits of MSR value.
2736 <b>Example usage</b>
2740 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);
2741 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);
2743 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.
2744 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.
2745 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.
2746 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.
2749 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740
2750 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741
2751 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742
2752 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743
2757 Package. Uncore C-Box 4, performance counter n.
2759 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn
2760 @param EAX Lower 32-bits of MSR value.
2761 @param EDX Upper 32-bits of MSR value.
2763 <b>Example usage</b>
2767 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);
2768 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);
2770 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.
2771 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.
2772 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.
2773 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.
2776 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746
2777 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747
2778 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748
2779 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749
2784 Package. MC Bank Error Configuration (R/W).
2786 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
2787 @param EAX Lower 32-bits of MSR value.
2788 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2789 @param EDX Upper 32-bits of MSR value.
2790 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2792 <b>Example usage</b>
2794 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
2796 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
2797 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
2799 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
2801 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
2804 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
2808 /// Individual bit fields
2813 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
2814 /// to log additional info in bits 36:32.
2816 UINT32 MemErrorLogEnable
:1;
2817 UINT32 Reserved2
:30;
2818 UINT32 Reserved3
:32;
2821 /// All bit fields as a 32-bit value
2825 /// All bit fields as a 64-bit value
2828 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
;
2834 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
2835 @param EAX Lower 32-bits of MSR value.
2836 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2837 @param EDX Upper 32-bits of MSR value.
2838 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2840 <b>Example usage</b>
2842 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
2844 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
2845 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
2847 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
2849 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
2852 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
2856 /// Individual bit fields
2860 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
2861 /// counting logic for specific events requiring additional configuration,
2862 /// see Table 19-15.
2864 UINT32 ENABLE_PEBS_NUM_ALT
:1;
2865 UINT32 Reserved1
:31;
2866 UINT32 Reserved2
:32;
2869 /// All bit fields as a 32-bit value
2873 /// All bit fields as a 64-bit value
2876 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
;
2880 Package. Package RAPL Perf Status (R/O).
2882 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
2883 @param EAX Lower 32-bits of MSR value.
2884 @param EDX Upper 32-bits of MSR value.
2886 <b>Example usage</b>
2890 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
2892 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
2894 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
2898 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
2901 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
2902 @param EAX Lower 32-bits of MSR value.
2903 @param EDX Upper 32-bits of MSR value.
2905 <b>Example usage</b>
2909 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
2910 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
2912 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
2914 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
2918 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
2920 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
2921 @param EAX Lower 32-bits of MSR value.
2922 @param EDX Upper 32-bits of MSR value.
2924 <b>Example usage</b>
2928 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
2930 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
2932 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
2936 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
2939 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
2940 @param EAX Lower 32-bits of MSR value.
2941 @param EDX Upper 32-bits of MSR value.
2943 <b>Example usage</b>
2947 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
2949 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
2951 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
2955 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
2957 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
2958 @param EAX Lower 32-bits of MSR value.
2959 @param EDX Upper 32-bits of MSR value.
2961 <b>Example usage</b>
2965 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
2966 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
2968 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
2970 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
2974 Package. Uncore U-box UCLK fixed counter control.
2976 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
2977 @param EAX Lower 32-bits of MSR value.
2978 @param EDX Upper 32-bits of MSR value.
2980 <b>Example usage</b>
2984 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
2985 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
2987 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
2989 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
2993 Package. Uncore U-box UCLK fixed counter.
2995 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
2996 @param EAX Lower 32-bits of MSR value.
2997 @param EDX Upper 32-bits of MSR value.
2999 <b>Example usage</b>
3003 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
3004 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
3006 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
3008 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
3012 Package. Uncore U-box perfmon event select for U-box counter 0.
3014 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
3015 @param EAX Lower 32-bits of MSR value.
3016 @param EDX Upper 32-bits of MSR value.
3018 <b>Example usage</b>
3022 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
3023 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
3025 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
3027 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
3031 Package. Uncore U-box perfmon event select for U-box counter 1.
3033 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
3034 @param EAX Lower 32-bits of MSR value.
3035 @param EDX Upper 32-bits of MSR value.
3037 <b>Example usage</b>
3041 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
3042 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
3044 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
3046 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
3050 Package. Uncore U-box perfmon counter 0.
3052 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
3053 @param EAX Lower 32-bits of MSR value.
3054 @param EDX Upper 32-bits of MSR value.
3056 <b>Example usage</b>
3060 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
3061 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
3063 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
3065 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
3069 Package. Uncore U-box perfmon counter 1.
3071 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
3072 @param EAX Lower 32-bits of MSR value.
3073 @param EDX Upper 32-bits of MSR value.
3075 <b>Example usage</b>
3079 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
3080 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
3082 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
3084 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
3088 Package. Uncore PCU perfmon for PCU-box-wide control.
3090 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
3091 @param EAX Lower 32-bits of MSR value.
3092 @param EDX Upper 32-bits of MSR value.
3094 <b>Example usage</b>
3098 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
3099 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
3101 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
3103 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
3107 Package. Uncore PCU perfmon event select for PCU counter 0.
3109 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
3110 @param EAX Lower 32-bits of MSR value.
3111 @param EDX Upper 32-bits of MSR value.
3113 <b>Example usage</b>
3117 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
3118 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
3120 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
3122 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
3126 Package. Uncore PCU perfmon event select for PCU counter 1.
3128 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
3129 @param EAX Lower 32-bits of MSR value.
3130 @param EDX Upper 32-bits of MSR value.
3132 <b>Example usage</b>
3136 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
3137 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
3139 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
3141 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
3145 Package. Uncore PCU perfmon event select for PCU counter 2.
3147 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
3148 @param EAX Lower 32-bits of MSR value.
3149 @param EDX Upper 32-bits of MSR value.
3151 <b>Example usage</b>
3155 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
3156 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
3158 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
3160 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
3164 Package. Uncore PCU perfmon event select for PCU counter 3.
3166 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
3167 @param EAX Lower 32-bits of MSR value.
3168 @param EDX Upper 32-bits of MSR value.
3170 <b>Example usage</b>
3174 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
3175 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
3177 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
3179 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
3183 Package. Uncore PCU perfmon box-wide filter.
3185 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
3186 @param EAX Lower 32-bits of MSR value.
3187 @param EDX Upper 32-bits of MSR value.
3189 <b>Example usage</b>
3193 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
3194 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
3196 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
3198 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
3202 Package. Uncore PCU perfmon counter 0.
3204 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
3205 @param EAX Lower 32-bits of MSR value.
3206 @param EDX Upper 32-bits of MSR value.
3208 <b>Example usage</b>
3212 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
3213 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
3215 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
3217 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
3221 Package. Uncore PCU perfmon counter 1.
3223 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
3224 @param EAX Lower 32-bits of MSR value.
3225 @param EDX Upper 32-bits of MSR value.
3227 <b>Example usage</b>
3231 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
3232 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
3234 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
3236 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
3240 Package. Uncore PCU perfmon counter 2.
3242 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
3243 @param EAX Lower 32-bits of MSR value.
3244 @param EDX Upper 32-bits of MSR value.
3246 <b>Example usage</b>
3250 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
3251 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
3253 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
3255 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
3259 Package. Uncore PCU perfmon counter 3.
3261 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
3262 @param EAX Lower 32-bits of MSR value.
3263 @param EDX Upper 32-bits of MSR value.
3265 <b>Example usage</b>
3269 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
3270 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
3272 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
3274 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
3278 Package. Uncore C-box 0 perfmon local box wide control.
3280 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
3281 @param EAX Lower 32-bits of MSR value.
3282 @param EDX Upper 32-bits of MSR value.
3284 <b>Example usage</b>
3288 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
3289 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
3291 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
3293 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
3297 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
3299 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
3300 @param EAX Lower 32-bits of MSR value.
3301 @param EDX Upper 32-bits of MSR value.
3303 <b>Example usage</b>
3307 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
3308 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
3310 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
3312 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
3316 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
3318 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
3319 @param EAX Lower 32-bits of MSR value.
3320 @param EDX Upper 32-bits of MSR value.
3322 <b>Example usage</b>
3326 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
3327 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
3329 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
3331 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
3335 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
3337 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
3338 @param EAX Lower 32-bits of MSR value.
3339 @param EDX Upper 32-bits of MSR value.
3341 <b>Example usage</b>
3345 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
3346 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
3348 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
3350 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
3354 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
3356 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
3357 @param EAX Lower 32-bits of MSR value.
3358 @param EDX Upper 32-bits of MSR value.
3360 <b>Example usage</b>
3364 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
3365 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
3367 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
3369 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
3373 Package. Uncore C-box 0 perfmon box wide filter.
3375 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
3376 @param EAX Lower 32-bits of MSR value.
3377 @param EDX Upper 32-bits of MSR value.
3379 <b>Example usage</b>
3383 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
3384 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
3386 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
3388 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
3392 Package. Uncore C-box 0 perfmon counter 0.
3394 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
3395 @param EAX Lower 32-bits of MSR value.
3396 @param EDX Upper 32-bits of MSR value.
3398 <b>Example usage</b>
3402 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
3403 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
3405 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3407 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
3411 Package. Uncore C-box 0 perfmon counter 1.
3413 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
3414 @param EAX Lower 32-bits of MSR value.
3415 @param EDX Upper 32-bits of MSR value.
3417 <b>Example usage</b>
3421 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
3422 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
3424 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3426 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
3430 Package. Uncore C-box 0 perfmon counter 2.
3432 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
3433 @param EAX Lower 32-bits of MSR value.
3434 @param EDX Upper 32-bits of MSR value.
3436 <b>Example usage</b>
3440 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
3441 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
3443 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3445 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
3449 Package. Uncore C-box 0 perfmon counter 3.
3451 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
3452 @param EAX Lower 32-bits of MSR value.
3453 @param EDX Upper 32-bits of MSR value.
3455 <b>Example usage</b>
3459 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
3460 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
3462 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3464 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
3468 Package. Uncore C-box 1 perfmon local box wide control.
3470 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
3471 @param EAX Lower 32-bits of MSR value.
3472 @param EDX Upper 32-bits of MSR value.
3474 <b>Example usage</b>
3478 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
3479 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
3481 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
3483 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
3487 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
3489 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
3490 @param EAX Lower 32-bits of MSR value.
3491 @param EDX Upper 32-bits of MSR value.
3493 <b>Example usage</b>
3497 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
3498 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
3500 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
3502 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
3506 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
3508 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
3509 @param EAX Lower 32-bits of MSR value.
3510 @param EDX Upper 32-bits of MSR value.
3512 <b>Example usage</b>
3516 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
3517 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
3519 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
3521 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
3525 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
3527 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
3528 @param EAX Lower 32-bits of MSR value.
3529 @param EDX Upper 32-bits of MSR value.
3531 <b>Example usage</b>
3535 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
3536 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
3538 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
3540 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
3544 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
3546 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
3547 @param EAX Lower 32-bits of MSR value.
3548 @param EDX Upper 32-bits of MSR value.
3550 <b>Example usage</b>
3554 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
3555 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
3557 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
3559 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
3563 Package. Uncore C-box 1 perfmon box wide filter.
3565 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
3566 @param EAX Lower 32-bits of MSR value.
3567 @param EDX Upper 32-bits of MSR value.
3569 <b>Example usage</b>
3573 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
3574 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
3576 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
3578 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
3582 Package. Uncore C-box 1 perfmon counter 0.
3584 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
3585 @param EAX Lower 32-bits of MSR value.
3586 @param EDX Upper 32-bits of MSR value.
3588 <b>Example usage</b>
3592 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
3593 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
3595 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
3597 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
3601 Package. Uncore C-box 1 perfmon counter 1.
3603 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
3604 @param EAX Lower 32-bits of MSR value.
3605 @param EDX Upper 32-bits of MSR value.
3607 <b>Example usage</b>
3611 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
3612 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
3614 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
3616 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
3620 Package. Uncore C-box 1 perfmon counter 2.
3622 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
3623 @param EAX Lower 32-bits of MSR value.
3624 @param EDX Upper 32-bits of MSR value.
3626 <b>Example usage</b>
3630 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
3631 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
3633 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
3635 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
3639 Package. Uncore C-box 1 perfmon counter 3.
3641 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
3642 @param EAX Lower 32-bits of MSR value.
3643 @param EDX Upper 32-bits of MSR value.
3645 <b>Example usage</b>
3649 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
3650 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
3652 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
3654 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
3658 Package. Uncore C-box 2 perfmon local box wide control.
3660 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
3661 @param EAX Lower 32-bits of MSR value.
3662 @param EDX Upper 32-bits of MSR value.
3664 <b>Example usage</b>
3668 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
3669 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
3671 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
3673 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
3677 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
3679 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
3680 @param EAX Lower 32-bits of MSR value.
3681 @param EDX Upper 32-bits of MSR value.
3683 <b>Example usage</b>
3687 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
3688 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
3690 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
3692 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
3696 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
3698 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
3699 @param EAX Lower 32-bits of MSR value.
3700 @param EDX Upper 32-bits of MSR value.
3702 <b>Example usage</b>
3706 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
3707 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
3709 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
3711 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
3715 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
3717 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
3718 @param EAX Lower 32-bits of MSR value.
3719 @param EDX Upper 32-bits of MSR value.
3721 <b>Example usage</b>
3725 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
3726 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
3728 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
3730 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
3734 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
3736 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
3737 @param EAX Lower 32-bits of MSR value.
3738 @param EDX Upper 32-bits of MSR value.
3740 <b>Example usage</b>
3744 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
3745 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
3747 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
3749 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
3753 Package. Uncore C-box 2 perfmon box wide filter.
3755 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
3756 @param EAX Lower 32-bits of MSR value.
3757 @param EDX Upper 32-bits of MSR value.
3759 <b>Example usage</b>
3763 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
3764 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
3766 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
3768 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
3772 Package. Uncore C-box 2 perfmon counter 0.
3774 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
3775 @param EAX Lower 32-bits of MSR value.
3776 @param EDX Upper 32-bits of MSR value.
3778 <b>Example usage</b>
3782 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
3783 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
3785 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
3787 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
3791 Package. Uncore C-box 2 perfmon counter 1.
3793 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
3794 @param EAX Lower 32-bits of MSR value.
3795 @param EDX Upper 32-bits of MSR value.
3797 <b>Example usage</b>
3801 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
3802 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
3804 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
3806 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
3810 Package. Uncore C-box 2 perfmon counter 2.
3812 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
3813 @param EAX Lower 32-bits of MSR value.
3814 @param EDX Upper 32-bits of MSR value.
3816 <b>Example usage</b>
3820 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
3821 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
3823 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
3825 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
3829 Package. Uncore C-box 2 perfmon counter 3.
3831 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
3832 @param EAX Lower 32-bits of MSR value.
3833 @param EDX Upper 32-bits of MSR value.
3835 <b>Example usage</b>
3839 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
3840 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
3842 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
3844 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
3848 Package. Uncore C-box 3 perfmon local box wide control.
3850 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
3851 @param EAX Lower 32-bits of MSR value.
3852 @param EDX Upper 32-bits of MSR value.
3854 <b>Example usage</b>
3858 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
3859 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
3861 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3863 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
3867 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3869 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
3870 @param EAX Lower 32-bits of MSR value.
3871 @param EDX Upper 32-bits of MSR value.
3873 <b>Example usage</b>
3877 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
3878 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
3880 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3882 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
3886 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3888 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
3889 @param EAX Lower 32-bits of MSR value.
3890 @param EDX Upper 32-bits of MSR value.
3892 <b>Example usage</b>
3896 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
3897 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
3899 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3901 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
3905 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3907 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
3908 @param EAX Lower 32-bits of MSR value.
3909 @param EDX Upper 32-bits of MSR value.
3911 <b>Example usage</b>
3915 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
3916 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
3918 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3920 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
3924 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3926 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
3927 @param EAX Lower 32-bits of MSR value.
3928 @param EDX Upper 32-bits of MSR value.
3930 <b>Example usage</b>
3934 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
3935 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
3937 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3939 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
3943 Package. Uncore C-box 3 perfmon box wide filter.
3945 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
3946 @param EAX Lower 32-bits of MSR value.
3947 @param EDX Upper 32-bits of MSR value.
3949 <b>Example usage</b>
3953 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
3954 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
3956 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
3958 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
3962 Package. Uncore C-box 3 perfmon counter 0.
3964 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
3965 @param EAX Lower 32-bits of MSR value.
3966 @param EDX Upper 32-bits of MSR value.
3968 <b>Example usage</b>
3972 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
3973 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
3975 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3977 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
3981 Package. Uncore C-box 3 perfmon counter 1.
3983 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
3984 @param EAX Lower 32-bits of MSR value.
3985 @param EDX Upper 32-bits of MSR value.
3987 <b>Example usage</b>
3991 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
3992 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
3994 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3996 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
4000 Package. Uncore C-box 3 perfmon counter 2.
4002 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
4003 @param EAX Lower 32-bits of MSR value.
4004 @param EDX Upper 32-bits of MSR value.
4006 <b>Example usage</b>
4010 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
4011 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
4013 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
4015 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
4019 Package. Uncore C-box 3 perfmon counter 3.
4021 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
4022 @param EAX Lower 32-bits of MSR value.
4023 @param EDX Upper 32-bits of MSR value.
4025 <b>Example usage</b>
4029 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
4030 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
4032 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
4034 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
4038 Package. Uncore C-box 4 perfmon local box wide control.
4040 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
4041 @param EAX Lower 32-bits of MSR value.
4042 @param EDX Upper 32-bits of MSR value.
4044 <b>Example usage</b>
4048 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
4049 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
4051 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
4053 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
4057 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
4059 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
4060 @param EAX Lower 32-bits of MSR value.
4061 @param EDX Upper 32-bits of MSR value.
4063 <b>Example usage</b>
4067 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
4068 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
4070 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
4072 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
4076 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
4078 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
4079 @param EAX Lower 32-bits of MSR value.
4080 @param EDX Upper 32-bits of MSR value.
4082 <b>Example usage</b>
4086 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
4087 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
4089 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
4091 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
4095 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
4097 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
4098 @param EAX Lower 32-bits of MSR value.
4099 @param EDX Upper 32-bits of MSR value.
4101 <b>Example usage</b>
4105 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
4106 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
4108 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
4110 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
4114 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
4116 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
4117 @param EAX Lower 32-bits of MSR value.
4118 @param EDX Upper 32-bits of MSR value.
4120 <b>Example usage</b>
4124 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
4125 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
4127 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
4129 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
4133 Package. Uncore C-box 4 perfmon box wide filter.
4135 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
4136 @param EAX Lower 32-bits of MSR value.
4137 @param EDX Upper 32-bits of MSR value.
4139 <b>Example usage</b>
4143 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
4144 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
4146 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
4148 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
4152 Package. Uncore C-box 4 perfmon counter 0.
4154 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
4155 @param EAX Lower 32-bits of MSR value.
4156 @param EDX Upper 32-bits of MSR value.
4158 <b>Example usage</b>
4162 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
4163 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
4165 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4167 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
4171 Package. Uncore C-box 4 perfmon counter 1.
4173 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
4174 @param EAX Lower 32-bits of MSR value.
4175 @param EDX Upper 32-bits of MSR value.
4177 <b>Example usage</b>
4181 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
4182 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
4184 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4186 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
4190 Package. Uncore C-box 4 perfmon counter 2.
4192 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
4193 @param EAX Lower 32-bits of MSR value.
4194 @param EDX Upper 32-bits of MSR value.
4196 <b>Example usage</b>
4200 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
4201 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
4203 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4205 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
4209 Package. Uncore C-box 4 perfmon counter 3.
4211 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
4212 @param EAX Lower 32-bits of MSR value.
4213 @param EDX Upper 32-bits of MSR value.
4215 <b>Example usage</b>
4219 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
4220 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
4222 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4224 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
4228 Package. Uncore C-box 5 perfmon local box wide control.
4230 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
4231 @param EAX Lower 32-bits of MSR value.
4232 @param EDX Upper 32-bits of MSR value.
4234 <b>Example usage</b>
4238 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
4239 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
4241 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
4243 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
4247 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
4249 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
4250 @param EAX Lower 32-bits of MSR value.
4251 @param EDX Upper 32-bits of MSR value.
4253 <b>Example usage</b>
4257 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
4258 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
4260 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
4262 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
4266 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
4268 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
4269 @param EAX Lower 32-bits of MSR value.
4270 @param EDX Upper 32-bits of MSR value.
4272 <b>Example usage</b>
4276 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
4277 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
4279 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
4281 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
4285 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
4287 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
4288 @param EAX Lower 32-bits of MSR value.
4289 @param EDX Upper 32-bits of MSR value.
4291 <b>Example usage</b>
4295 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
4296 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
4298 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
4300 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
4304 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
4306 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
4307 @param EAX Lower 32-bits of MSR value.
4308 @param EDX Upper 32-bits of MSR value.
4310 <b>Example usage</b>
4314 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
4315 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
4317 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
4319 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
4323 Package. Uncore C-box 5 perfmon box wide filter.
4325 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
4326 @param EAX Lower 32-bits of MSR value.
4327 @param EDX Upper 32-bits of MSR value.
4329 <b>Example usage</b>
4333 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
4334 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
4336 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
4338 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
4342 Package. Uncore C-box 5 perfmon counter 0.
4344 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
4345 @param EAX Lower 32-bits of MSR value.
4346 @param EDX Upper 32-bits of MSR value.
4348 <b>Example usage</b>
4352 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
4353 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
4355 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
4357 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
4361 Package. Uncore C-box 5 perfmon counter 1.
4363 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
4364 @param EAX Lower 32-bits of MSR value.
4365 @param EDX Upper 32-bits of MSR value.
4367 <b>Example usage</b>
4371 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
4372 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
4374 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
4376 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
4380 Package. Uncore C-box 5 perfmon counter 2.
4382 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
4383 @param EAX Lower 32-bits of MSR value.
4384 @param EDX Upper 32-bits of MSR value.
4386 <b>Example usage</b>
4390 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
4391 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
4393 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
4395 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
4399 Package. Uncore C-box 5 perfmon counter 3.
4401 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
4402 @param EAX Lower 32-bits of MSR value.
4403 @param EDX Upper 32-bits of MSR value.
4405 <b>Example usage</b>
4409 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
4410 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
4412 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
4414 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
4418 Package. Uncore C-box 6 perfmon local box wide control.
4420 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
4421 @param EAX Lower 32-bits of MSR value.
4422 @param EDX Upper 32-bits of MSR value.
4424 <b>Example usage</b>
4428 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
4429 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
4431 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
4433 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
4437 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
4439 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
4440 @param EAX Lower 32-bits of MSR value.
4441 @param EDX Upper 32-bits of MSR value.
4443 <b>Example usage</b>
4447 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
4448 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
4450 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
4452 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
4456 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
4458 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
4459 @param EAX Lower 32-bits of MSR value.
4460 @param EDX Upper 32-bits of MSR value.
4462 <b>Example usage</b>
4466 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
4467 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
4469 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
4471 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
4475 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
4477 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
4478 @param EAX Lower 32-bits of MSR value.
4479 @param EDX Upper 32-bits of MSR value.
4481 <b>Example usage</b>
4485 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
4486 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
4488 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
4490 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
4494 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
4496 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
4497 @param EAX Lower 32-bits of MSR value.
4498 @param EDX Upper 32-bits of MSR value.
4500 <b>Example usage</b>
4504 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
4505 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
4507 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
4509 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
4513 Package. Uncore C-box 6 perfmon box wide filter.
4515 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
4516 @param EAX Lower 32-bits of MSR value.
4517 @param EDX Upper 32-bits of MSR value.
4519 <b>Example usage</b>
4523 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
4524 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
4526 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
4528 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
4532 Package. Uncore C-box 6 perfmon counter 0.
4534 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
4535 @param EAX Lower 32-bits of MSR value.
4536 @param EDX Upper 32-bits of MSR value.
4538 <b>Example usage</b>
4542 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
4543 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
4545 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4547 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
4551 Package. Uncore C-box 6 perfmon counter 1.
4553 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
4554 @param EAX Lower 32-bits of MSR value.
4555 @param EDX Upper 32-bits of MSR value.
4557 <b>Example usage</b>
4561 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
4562 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
4564 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4566 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
4570 Package. Uncore C-box 6 perfmon counter 2.
4572 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
4573 @param EAX Lower 32-bits of MSR value.
4574 @param EDX Upper 32-bits of MSR value.
4576 <b>Example usage</b>
4580 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
4581 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
4583 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4585 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
4589 Package. Uncore C-box 6 perfmon counter 3.
4591 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
4592 @param EAX Lower 32-bits of MSR value.
4593 @param EDX Upper 32-bits of MSR value.
4595 <b>Example usage</b>
4599 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
4600 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
4602 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4604 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
4608 Package. Uncore C-box 7 perfmon local box wide control.
4610 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
4611 @param EAX Lower 32-bits of MSR value.
4612 @param EDX Upper 32-bits of MSR value.
4614 <b>Example usage</b>
4618 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
4619 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
4621 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
4623 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
4627 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
4629 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
4630 @param EAX Lower 32-bits of MSR value.
4631 @param EDX Upper 32-bits of MSR value.
4633 <b>Example usage</b>
4637 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
4638 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
4640 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
4642 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
4646 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
4648 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
4649 @param EAX Lower 32-bits of MSR value.
4650 @param EDX Upper 32-bits of MSR value.
4652 <b>Example usage</b>
4656 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
4657 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
4659 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
4661 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
4665 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4667 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
4668 @param EAX Lower 32-bits of MSR value.
4669 @param EDX Upper 32-bits of MSR value.
4671 <b>Example usage</b>
4675 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
4676 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
4678 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4680 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
4684 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4686 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
4687 @param EAX Lower 32-bits of MSR value.
4688 @param EDX Upper 32-bits of MSR value.
4690 <b>Example usage</b>
4694 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
4695 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
4697 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4699 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
4703 Package. Uncore C-box 7 perfmon box wide filter.
4705 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
4706 @param EAX Lower 32-bits of MSR value.
4707 @param EDX Upper 32-bits of MSR value.
4709 <b>Example usage</b>
4713 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
4714 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
4716 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
4718 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
4722 Package. Uncore C-box 7 perfmon counter 0.
4724 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
4725 @param EAX Lower 32-bits of MSR value.
4726 @param EDX Upper 32-bits of MSR value.
4728 <b>Example usage</b>
4732 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
4733 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
4735 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4737 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
4741 Package. Uncore C-box 7 perfmon counter 1.
4743 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
4744 @param EAX Lower 32-bits of MSR value.
4745 @param EDX Upper 32-bits of MSR value.
4747 <b>Example usage</b>
4751 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
4752 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
4754 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4756 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
4760 Package. Uncore C-box 7 perfmon counter 2.
4762 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
4763 @param EAX Lower 32-bits of MSR value.
4764 @param EDX Upper 32-bits of MSR value.
4766 <b>Example usage</b>
4770 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
4771 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
4773 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4775 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
4779 Package. Uncore C-box 7 perfmon counter 3.
4781 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
4782 @param EAX Lower 32-bits of MSR value.
4783 @param EDX Upper 32-bits of MSR value.
4785 <b>Example usage</b>
4789 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
4790 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
4792 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4794 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9