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UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment
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1 /** @file
2 MSR Definitions for Intel processors based on the Silvermont microarchitecture.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.
21
22 **/
23
24 #ifndef __SILVERMONT_MSR_H__
25 #define __SILVERMONT_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Shared. Model Specific Platform ID (R).
31
32 @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
37
38 <b>Example usage</b>
39 @code
40 MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;
41
42 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
43 @endcode
44 @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
45 **/
46 #define MSR_SILVERMONT_PLATFORM_ID 0x00000017
47
48 /**
49 MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
50 **/
51 typedef union {
52 ///
53 /// Individual bit fields
54 ///
55 struct {
56 UINT32 Reserved1:8;
57 ///
58 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
59 ///
60 UINT32 MaximumQualifiedRatio:5;
61 UINT32 Reserved2:19;
62 UINT32 Reserved3:18;
63 ///
64 /// [Bits 52:50] See Table 35-2.
65 ///
66 UINT32 PlatformId:3;
67 UINT32 Reserved4:11;
68 } Bits;
69 ///
70 /// All bit fields as a 64-bit value
71 ///
72 UINT64 Uint64;
73 } MSR_SILVERMONT_PLATFORM_ID_REGISTER;
74
75
76 /**
77 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
78 processor features; (R) indicates current processor configuration.
79
80 @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
81 @param EAX Lower 32-bits of MSR value.
82 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
83 @param EDX Upper 32-bits of MSR value.
84 Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
85
86 <b>Example usage</b>
87 @code
88 MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;
89
90 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
91 AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
92 @endcode
93 @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
94 **/
95 #define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A
96
97 /**
98 MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
99 **/
100 typedef union {
101 ///
102 /// Individual bit fields
103 ///
104 struct {
105 UINT32 Reserved1:1;
106 ///
107 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
108 /// Always 0.
109 ///
110 UINT32 DataErrorCheckingEnable:1;
111 ///
112 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
113 /// Always 0.
114 ///
115 UINT32 ResponseErrorCheckingEnable:1;
116 ///
117 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
118 ///
119 UINT32 AERR_DriveEnable:1;
120 ///
121 /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
122 /// Disabled Always 0.
123 ///
124 UINT32 BERR_Enable:1;
125 UINT32 Reserved2:1;
126 UINT32 Reserved3:1;
127 ///
128 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
129 ///
130 UINT32 BINIT_DriverEnable:1;
131 UINT32 Reserved4:1;
132 ///
133 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
134 ///
135 UINT32 ExecuteBIST:1;
136 ///
137 /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
138 /// Always 0.
139 ///
140 UINT32 AERR_ObservationEnabled:1;
141 UINT32 Reserved5:1;
142 ///
143 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
144 /// Always 0.
145 ///
146 UINT32 BINIT_ObservationEnabled:1;
147 UINT32 Reserved6:1;
148 ///
149 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
150 ///
151 UINT32 ResetVector:1;
152 UINT32 Reserved7:1;
153 ///
154 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
155 ///
156 UINT32 APICClusterID:2;
157 UINT32 Reserved8:2;
158 ///
159 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
160 ///
161 UINT32 SymmetricArbitrationID:2;
162 ///
163 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
164 ///
165 UINT32 IntegerBusFrequencyRatio:5;
166 UINT32 Reserved9:5;
167 UINT32 Reserved10:32;
168 } Bits;
169 ///
170 /// All bit fields as a 32-bit value
171 ///
172 UINT32 Uint32;
173 ///
174 /// All bit fields as a 64-bit value
175 ///
176 UINT64 Uint64;
177 } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
178
179
180 /**
181 Core. SMI Counter (R/O).
182
183 @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)
184 @param EAX Lower 32-bits of MSR value.
185 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
186 @param EDX Upper 32-bits of MSR value.
187 Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
188
189 <b>Example usage</b>
190 @code
191 MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;
192
193 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
194 @endcode
195 @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
196 **/
197 #define MSR_SILVERMONT_SMI_COUNT 0x00000034
198
199 /**
200 MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
201 **/
202 typedef union {
203 ///
204 /// Individual bit fields
205 ///
206 struct {
207 ///
208 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
209 /// RESET.
210 ///
211 UINT32 SMICount:32;
212 UINT32 Reserved:32;
213 } Bits;
214 ///
215 /// All bit fields as a 32-bit value
216 ///
217 UINT32 Uint32;
218 ///
219 /// All bit fields as a 64-bit value
220 ///
221 UINT64 Uint64;
222 } MSR_SILVERMONT_SMI_COUNT_REGISTER;
223
224
225 /**
226 Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
227 record registers on the last branch record stack. This part of the stack
228 contains pointers to the source instruction for one of the last eight
229 branches, exceptions, or interrupts taken by the processor. See also: -
230 Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
231 Interrupt, and Exception Recording (Pentium M Processors).".
232
233 @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
234 @param EAX Lower 32-bits of MSR value.
235 @param EDX Upper 32-bits of MSR value.
236
237 <b>Example usage</b>
238 @code
239 UINT64 Msr;
240
241 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
242 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
243 @endcode
244 @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
245 MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
246 MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
247 MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
248 MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
249 MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
250 MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
251 MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
252 @{
253 **/
254 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040
255 #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041
256 #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042
257 #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043
258 #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044
259 #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045
260 #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046
261 #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047
262 /// @}
263
264
265 /**
266 Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
267 record registers on the last branch record stack. This part of the stack
268 contains pointers to the destination instruction for one of the last eight
269 branches, exceptions, or interrupts taken by the processor.
270
271 @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP
272 @param EAX Lower 32-bits of MSR value.
273 @param EDX Upper 32-bits of MSR value.
274
275 <b>Example usage</b>
276 @code
277 UINT64 Msr;
278
279 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
280 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
281 @endcode
282 @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
283 MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
284 MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
285 MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
286 MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
287 MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
288 MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
289 MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
290 @{
291 **/
292 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060
293 #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061
294 #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062
295 #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063
296 #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064
297 #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065
298 #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066
299 #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067
300 /// @}
301
302
303 /**
304 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
305 bus clock speed for processors based on Silvermont microarchitecture:.
306
307 @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)
308 @param EAX Lower 32-bits of MSR value.
309 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
310 @param EDX Upper 32-bits of MSR value.
311 Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
312
313 <b>Example usage</b>
314 @code
315 MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;
316
317 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
318 @endcode
319 @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
320 **/
321 #define MSR_SILVERMONT_FSB_FREQ 0x000000CD
322
323 /**
324 MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
325 **/
326 typedef union {
327 ///
328 /// Individual bit fields
329 ///
330 struct {
331 ///
332 /// [Bits 3:0] Scalable Bus Speed
333 ///
334 /// Silvermont Processor Family
335 /// ---------------------------
336 /// 100B: 080.0 MHz
337 /// 000B: 083.3 MHz
338 /// 001B: 100.0 MHz
339 /// 010B: 133.3 MHz
340 /// 011B: 116.7 MHz
341 ///
342 /// Airmont Processor Family
343 /// ---------------------------
344 /// 0000B: 083.3 MHz
345 /// 0001B: 100.0 MHz
346 /// 0010B: 133.3 MHz
347 /// 0011B: 116.7 MHz
348 /// 0100B: 080.0 MHz
349 /// 0101B: 093.3 MHz
350 /// 0110B: 090.0 MHz
351 /// 0111B: 088.9 MHz
352 /// 1000B: 087.5 MHz
353 ///
354 UINT32 ScalableBusSpeed:4;
355 UINT32 Reserved1:28;
356 UINT32 Reserved2:32;
357 } Bits;
358 ///
359 /// All bit fields as a 32-bit value
360 ///
361 UINT32 Uint32;
362 ///
363 /// All bit fields as a 64-bit value
364 ///
365 UINT64 Uint64;
366 } MSR_SILVERMONT_FSB_FREQ_REGISTER;
367
368
369 /**
370 Shared. C-State Configuration Control (R/W) Note: C-state values are
371 processor specific C-state code names, unrelated to MWAIT extension C-state
372 parameters or ACPI CStates. See http://biosbits.org.
373
374 @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
375 @param EAX Lower 32-bits of MSR value.
376 Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
377 @param EDX Upper 32-bits of MSR value.
378 Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
379
380 <b>Example usage</b>
381 @code
382 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
383
384 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
385 AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
386 @endcode
387 @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
388 **/
389 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
390
391 /**
392 MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
393 **/
394 typedef union {
395 ///
396 /// Individual bit fields
397 ///
398 struct {
399 ///
400 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
401 /// processor-specific C-state code name (consuming the least power). for
402 /// the package. The default is set as factory-configured package C-state
403 /// limit. The following C-state code name encodings are supported: 000b:
404 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
405 /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
406 ///
407 UINT32 Limit:3;
408 UINT32 Reserved1:7;
409 ///
410 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
411 /// IO_read instructions sent to IO register specified by
412 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
413 ///
414 UINT32 IO_MWAIT:1;
415 UINT32 Reserved2:4;
416 ///
417 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
418 /// until next reset.
419 ///
420 UINT32 CFGLock:1;
421 UINT32 Reserved3:16;
422 UINT32 Reserved4:32;
423 } Bits;
424 ///
425 /// All bit fields as a 32-bit value
426 ///
427 UINT32 Uint32;
428 ///
429 /// All bit fields as a 64-bit value
430 ///
431 UINT64 Uint64;
432 } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
433
434
435 /**
436 Shared. Power Management IO Redirection in C-state (R/W) See
437 http://biosbits.org.
438
439 @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
440 @param EAX Lower 32-bits of MSR value.
441 Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
442 @param EDX Upper 32-bits of MSR value.
443 Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
444
445 <b>Example usage</b>
446 @code
447 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;
448
449 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
450 AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
451 @endcode
452 @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
453 **/
454 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4
455
456 /**
457 MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
458 **/
459 typedef union {
460 ///
461 /// Individual bit fields
462 ///
463 struct {
464 ///
465 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
466 /// visible to software for IO redirection. If IO MWAIT Redirection is
467 /// enabled, reads to this address will be consumed by the power
468 /// management logic and decoded to MWAIT instructions. When IO port
469 /// address redirection is enabled, this is the IO port address reported
470 /// to the OS/software.
471 ///
472 UINT32 Lvl2Base:16;
473 ///
474 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
475 /// maximum C-State code name to be included when IO read to MWAIT
476 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
477 /// is the max C-State to include 110b - C6 is the max C-State to include
478 /// 111b - C7 is the max C-State to include.
479 ///
480 UINT32 CStateRange:3;
481 UINT32 Reserved1:13;
482 UINT32 Reserved2:32;
483 } Bits;
484 ///
485 /// All bit fields as a 32-bit value
486 ///
487 UINT32 Uint32;
488 ///
489 /// All bit fields as a 64-bit value
490 ///
491 UINT64 Uint64;
492 } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
493
494
495 /**
496 Shared.
497
498 @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
499 @param EAX Lower 32-bits of MSR value.
500 Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
501 @param EDX Upper 32-bits of MSR value.
502 Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
503
504 <b>Example usage</b>
505 @code
506 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;
507
508 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
509 AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
510 @endcode
511 @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
512 **/
513 #define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E
514
515 /**
516 MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
517 **/
518 typedef union {
519 ///
520 /// Individual bit fields
521 ///
522 struct {
523 ///
524 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
525 /// Indicates if the L2 is hardware-disabled.
526 ///
527 UINT32 L2HardwareEnabled:1;
528 UINT32 Reserved1:7;
529 ///
530 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
531 /// Disabled (default) Until this bit is set the processor will not
532 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
533 ///
534 UINT32 L2Enabled:1;
535 UINT32 Reserved2:14;
536 ///
537 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
538 ///
539 UINT32 L2NotPresent:1;
540 UINT32 Reserved3:8;
541 UINT32 Reserved4:32;
542 } Bits;
543 ///
544 /// All bit fields as a 32-bit value
545 ///
546 UINT32 Uint32;
547 ///
548 /// All bit fields as a 64-bit value
549 ///
550 UINT64 Uint64;
551 } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
552
553
554 /**
555 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
556 handler to handle unsuccessful read of this MSR.
557
558 @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
559 @param EAX Lower 32-bits of MSR value.
560 Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
561 @param EDX Upper 32-bits of MSR value.
562 Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
563
564 <b>Example usage</b>
565 @code
566 MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;
567
568 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
569 AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
570 @endcode
571 @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
572 **/
573 #define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C
574
575 /**
576 MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
577 **/
578 typedef union {
579 ///
580 /// Individual bit fields
581 ///
582 struct {
583 ///
584 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
585 /// MSR, the configuration of AES instruction set availability is as
586 /// follows: 11b: AES instructions are not available until next RESET.
587 /// otherwise, AES instructions are available. Note, AES instruction set
588 /// is not available if read is unsuccessful. If the configuration is not
589 /// 01b, AES instruction can be mis-configured if a privileged agent
590 /// unintentionally writes 11b.
591 ///
592 UINT32 AESConfiguration:2;
593 UINT32 Reserved1:30;
594 UINT32 Reserved2:32;
595 } Bits;
596 ///
597 /// All bit fields as a 32-bit value
598 ///
599 UINT32 Uint32;
600 ///
601 /// All bit fields as a 64-bit value
602 ///
603 UINT64 Uint64;
604 } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
605
606
607 /**
608 Enable Misc. Processor Features (R/W) Allows a variety of processor
609 functions to be enabled and disabled.
610
611 @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
612 @param EAX Lower 32-bits of MSR value.
613 Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
614 @param EDX Upper 32-bits of MSR value.
615 Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
616
617 <b>Example usage</b>
618 @code
619 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;
620
621 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
622 AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
623 @endcode
624 @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
625 **/
626 #define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0
627
628 /**
629 MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
630 **/
631 typedef union {
632 ///
633 /// Individual bit fields
634 ///
635 struct {
636 ///
637 /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
638 ///
639 UINT32 FastStrings:1;
640 UINT32 Reserved1:2;
641 ///
642 /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See
643 /// Table 35-2.
644 ///
645 UINT32 AutomaticThermalControlCircuit:1;
646 UINT32 Reserved2:3;
647 ///
648 /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
649 ///
650 UINT32 PerformanceMonitoring:1;
651 UINT32 Reserved3:3;
652 ///
653 /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
654 ///
655 UINT32 BTS:1;
656 ///
657 /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table
658 /// 35-2.
659 ///
660 UINT32 PEBS:1;
661 UINT32 Reserved4:3;
662 ///
663 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
664 /// Table 35-2.
665 ///
666 UINT32 EIST:1;
667 UINT32 Reserved5:1;
668 ///
669 /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
670 ///
671 UINT32 MONITOR:1;
672 UINT32 Reserved6:3;
673 ///
674 /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
675 ///
676 UINT32 LimitCpuidMaxval:1;
677 ///
678 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
679 ///
680 UINT32 xTPR_Message_Disable:1;
681 UINT32 Reserved7:8;
682 UINT32 Reserved8:2;
683 ///
684 /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
685 ///
686 UINT32 XD:1;
687 UINT32 Reserved9:3;
688 ///
689 /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors
690 /// that support Intel Turbo Boost Technology, the turbo mode feature is
691 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
692 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
693 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
694 /// the power-on default value is used by BIOS to detect hardware support
695 /// of turbo mode. If power-on default value is 1, turbo mode is available
696 /// in the processor. If power-on default value is 0, turbo mode is not
697 /// available.
698 ///
699 UINT32 TurboModeDisable:1;
700 UINT32 Reserved10:25;
701 } Bits;
702 ///
703 /// All bit fields as a 64-bit value
704 ///
705 UINT64 Uint64;
706 } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
707
708
709 /**
710 Package.
711
712 @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
713 @param EAX Lower 32-bits of MSR value.
714 Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
715 @param EDX Upper 32-bits of MSR value.
716 Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
717
718 <b>Example usage</b>
719 @code
720 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;
721
722 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
723 AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
724 @endcode
725 @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
726 **/
727 #define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2
728
729 /**
730 MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
731 **/
732 typedef union {
733 ///
734 /// Individual bit fields
735 ///
736 struct {
737 UINT32 Reserved1:16;
738 ///
739 /// [Bits 23:16] Temperature Target (R) The default thermal throttling or
740 /// PROCHOT# activation temperature in degree C, The effective temperature
741 /// for thermal throttling or PROCHOT# activation is "Temperature Target"
742 /// + "Target Offset".
743 ///
744 UINT32 TemperatureTarget:8;
745 ///
746 /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to
747 /// adjust the throttling and PROCHOT# activation temperature from the
748 /// default target specified in TEMPERATURE_TARGET (bits 23:16).
749 ///
750 UINT32 TargetOffset:6;
751 UINT32 Reserved2:2;
752 UINT32 Reserved3:32;
753 } Bits;
754 ///
755 /// All bit fields as a 32-bit value
756 ///
757 UINT32 Uint32;
758 ///
759 /// All bit fields as a 64-bit value
760 ///
761 UINT64 Uint64;
762 } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
763
764
765 /**
766 Shared. Offcore Response Event Select Register (R/W).
767
768 @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
769 @param EAX Lower 32-bits of MSR value.
770 @param EDX Upper 32-bits of MSR value.
771
772 <b>Example usage</b>
773 @code
774 UINT64 Msr;
775
776 Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
777 AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
778 @endcode
779 @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
780 **/
781 #define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6
782
783
784 /**
785 Shared. Offcore Response Event Select Register (R/W).
786
787 @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
788 @param EAX Lower 32-bits of MSR value.
789 @param EDX Upper 32-bits of MSR value.
790
791 <b>Example usage</b>
792 @code
793 UINT64 Msr;
794
795 Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
796 AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
797 @endcode
798 @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
799 **/
800 #define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7
801
802
803 /**
804 Package. Maximum Ratio Limit of Turbo Mode (RW).
805
806 @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
807 @param EAX Lower 32-bits of MSR value.
808 Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
809 @param EDX Upper 32-bits of MSR value.
810 Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
811
812 <b>Example usage</b>
813 @code
814 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
815
816 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
817 AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
818 @endcode
819 @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
820 **/
821 #define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD
822
823 /**
824 MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
825 **/
826 typedef union {
827 ///
828 /// Individual bit fields
829 ///
830 struct {
831 ///
832 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
833 /// limit of 1 core active.
834 ///
835 UINT32 Maximum1C:8;
836 ///
837 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
838 /// limit of 2 core active.
839 ///
840 UINT32 Maximum2C:8;
841 ///
842 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
843 /// limit of 3 core active.
844 ///
845 UINT32 Maximum3C:8;
846 ///
847 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
848 /// limit of 4 core active.
849 ///
850 UINT32 Maximum4C:8;
851 ///
852 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
853 /// limit of 5 core active.
854 ///
855 UINT32 Maximum5C:8;
856 ///
857 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
858 /// limit of 6 core active.
859 ///
860 UINT32 Maximum6C:8;
861 ///
862 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
863 /// limit of 7 core active.
864 ///
865 UINT32 Maximum7C:8;
866 ///
867 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
868 /// limit of 8 core active.
869 ///
870 UINT32 Maximum8C:8;
871 } Bits;
872 ///
873 /// All bit fields as a 64-bit value
874 ///
875 UINT64 Uint64;
876 } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
877
878
879 /**
880 Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that
881 points to the MSR containing the most recent branch record. See
882 MSR_LASTBRANCH_0_FROM_IP (at 40H).
883
884 @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
885 @param EAX Lower 32-bits of MSR value.
886 @param EDX Upper 32-bits of MSR value.
887
888 <b>Example usage</b>
889 @code
890 UINT64 Msr;
891
892 Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
893 AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
894 @endcode
895 @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
896 **/
897 #define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9
898
899
900 /**
901 Core. Last Exception Record From Linear IP (R) Contains a pointer to the
902 last branch instruction that the processor executed prior to the last
903 exception that was generated or the last interrupt that was handled.
904
905 @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
906 @param EAX Lower 32-bits of MSR value.
907 @param EDX Upper 32-bits of MSR value.
908
909 <b>Example usage</b>
910 @code
911 UINT64 Msr;
912
913 Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
914 @endcode
915 @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
916 **/
917 #define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD
918
919
920 /**
921 Core. Last Exception Record To Linear IP (R) This area contains a pointer
922 to the target of the last branch instruction that the processor executed
923 prior to the last exception that was generated or the last interrupt that
924 was handled.
925
926 @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
927 @param EAX Lower 32-bits of MSR value.
928 @param EDX Upper 32-bits of MSR value.
929
930 <b>Example usage</b>
931 @code
932 UINT64 Msr;
933
934 Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
935 @endcode
936 @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
937 **/
938 #define MSR_SILVERMONT_LER_TO_LIP 0x000001DE
939
940
941 /**
942 Core. See Table 35-2. See Section 18.4.2, "Global Counter Control
943 Facilities.".
944
945 @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)
946 @param EAX Lower 32-bits of MSR value.
947 @param EDX Upper 32-bits of MSR value.
948
949 <b>Example usage</b>
950 @code
951 UINT64 Msr;
952
953 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);
954 AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);
955 @endcode
956 @note MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
957 **/
958 #define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E
959
960
961 /**
962 Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
963 (PEBS).".
964
965 @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
966 @param EAX Lower 32-bits of MSR value.
967 Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
968 @param EDX Upper 32-bits of MSR value.
969 Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
970
971 <b>Example usage</b>
972 @code
973 MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;
974
975 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
976 AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
977 @endcode
978 @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
979 **/
980 #define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1
981
982 /**
983 MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
984 **/
985 typedef union {
986 ///
987 /// Individual bit fields
988 ///
989 struct {
990 ///
991 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
992 ///
993 UINT32 PEBS:1;
994 UINT32 Reserved1:31;
995 UINT32 Reserved2:32;
996 } Bits;
997 ///
998 /// All bit fields as a 32-bit value
999 ///
1000 UINT32 Uint32;
1001 ///
1002 /// All bit fields as a 64-bit value
1003 ///
1004 UINT64 Uint64;
1005 } MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
1006
1007
1008 /**
1009 Package. Note: C-state values are processor specific C-state code names,
1010 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1011 Residency Counter. (R/O) Value since last reset that this package is in
1012 processor-specific C6 states. Counts at the TSC Frequency.
1013
1014 @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
1015 @param EAX Lower 32-bits of MSR value.
1016 @param EDX Upper 32-bits of MSR value.
1017
1018 <b>Example usage</b>
1019 @code
1020 UINT64 Msr;
1021
1022 Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
1023 AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
1024 @endcode
1025 @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1026 **/
1027 #define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA
1028
1029
1030 /**
1031 Core. Note: C-state values are processor specific C-state code names,
1032 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1033 Residency Counter. (R/O) Value since last reset that this core is in
1034 processor-specific C6 states. Counts at the TSC Frequency.
1035
1036 @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
1037 @param EAX Lower 32-bits of MSR value.
1038 @param EDX Upper 32-bits of MSR value.
1039
1040 <b>Example usage</b>
1041 @code
1042 UINT64 Msr;
1043
1044 Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
1045 AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
1046 @endcode
1047 @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1048 **/
1049 #define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD
1050
1051
1052 /**
1053 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1054
1055 @param ECX MSR_SILVERMONT_MCi_CTL
1056 @param EAX Lower 32-bits of MSR value.
1057 @param EDX Upper 32-bits of MSR value.
1058
1059 <b>Example usage</b>
1060 @code
1061 UINT64 Msr;
1062
1063 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);
1064 AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);
1065 @endcode
1066 @note MSR_SILVERMONT_MC3_CTL is defined as MSR_MC3_CTL in SDM.
1067 MSR_SILVERMONT_MC4_CTL is defined as MSR_MC4_CTL in SDM.
1068 MSR_SILVERMONT_MC5_CTL is defined as MSR_MC5_CTL in SDM.
1069 @{
1070 **/
1071 #define MSR_SILVERMONT_MC3_CTL 0x0000040C
1072 #define MSR_SILVERMONT_MC4_CTL 0x00000410
1073 #define MSR_SILVERMONT_MC5_CTL 0x00000414
1074 /// @}
1075
1076
1077 /**
1078 Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
1079
1080 @param ECX MSR_SILVERMONT_MCi_STATUS
1081 @param EAX Lower 32-bits of MSR value.
1082 @param EDX Upper 32-bits of MSR value.
1083
1084 <b>Example usage</b>
1085 @code
1086 UINT64 Msr;
1087
1088 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);
1089 AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);
1090 @endcode
1091 @note MSR_SILVERMONT_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
1092 MSR_SILVERMONT_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
1093 MSR_SILVERMONT_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
1094 @{
1095 **/
1096 #define MSR_SILVERMONT_MC3_STATUS 0x0000040D
1097 #define MSR_SILVERMONT_MC4_STATUS 0x00000411
1098 #define MSR_SILVERMONT_MC5_STATUS 0x00000415
1099 /// @}
1100
1101
1102 /**
1103 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register
1104 is either not implemented or contains no address if the ADDRV flag in the
1105 MSR_MCi_STATUS register is clear. When not implemented in the processor, all
1106 reads and writes to this MSR will cause a general-protection exception.
1107
1108 @param ECX MSR_SILVERMONT_MCi_ADDR
1109 @param EAX Lower 32-bits of MSR value.
1110 @param EDX Upper 32-bits of MSR value.
1111
1112 <b>Example usage</b>
1113 @code
1114 UINT64 Msr;
1115
1116 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);
1117 AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);
1118 @endcode
1119 @note MSR_SILVERMONT_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
1120 MSR_SILVERMONT_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
1121 MSR_SILVERMONT_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
1122 @{
1123 **/
1124 #define MSR_SILVERMONT_MC3_ADDR 0x0000040E
1125 #define MSR_SILVERMONT_MC4_ADDR 0x00000412
1126 #define MSR_SILVERMONT_MC5_ADDR 0x00000416
1127 /// @}
1128
1129
1130 /**
1131 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
1132
1133 @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1134 @param EAX Lower 32-bits of MSR value.
1135 @param EDX Upper 32-bits of MSR value.
1136
1137 <b>Example usage</b>
1138 @code
1139 UINT64 Msr;
1140
1141 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
1142 @endcode
1143 @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1144 **/
1145 #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1146
1147
1148 /**
1149 Core. Capability Reporting Register of VM-function Controls (R/O) See Table
1150 35-2.
1151
1152 @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
1153 @param EAX Lower 32-bits of MSR value.
1154 @param EDX Upper 32-bits of MSR value.
1155
1156 <b>Example usage</b>
1157 @code
1158 UINT64 Msr;
1159
1160 Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
1161 @endcode
1162 @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1163 **/
1164 #define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491
1165
1166
1167 /**
1168 Core. Note: C-state values are processor specific C-state code names,
1169 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
1170 Residency Counter. (R/O) Value since last reset that this core is in
1171 processor-specific C1 states. Counts at the TSC frequency.
1172
1173 @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
1174 @param EAX Lower 32-bits of MSR value.
1175 @param EDX Upper 32-bits of MSR value.
1176
1177 <b>Example usage</b>
1178 @code
1179 UINT64 Msr;
1180
1181 Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
1182 AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
1183 @endcode
1184 @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
1185 **/
1186 #define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660
1187
1188
1189 /**
1190 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1191 "RAPL Interfaces.".
1192
1193 @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
1194 @param EAX Lower 32-bits of MSR value.
1195 Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1196 @param EDX Upper 32-bits of MSR value.
1197 Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1198
1199 <b>Example usage</b>
1200 @code
1201 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;
1202
1203 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
1204 @endcode
1205 @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1206 **/
1207 #define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606
1208
1209 /**
1210 MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
1211 **/
1212 typedef union {
1213 ///
1214 /// Individual bit fields
1215 ///
1216 struct {
1217 ///
1218 /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
1219 /// based on the multiplier, 2^PU; where PU is an unsigned integer
1220 /// represented by bits 3:0. Default value is 0101b, indicating power unit
1221 /// is in 32 milliWatts increment.
1222 ///
1223 UINT32 PowerUnits:4;
1224 UINT32 Reserved1:4;
1225 ///
1226 /// [Bits 12:8] Energy Status Units. Energy related information (in
1227 /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
1228 /// unsigned integer represented by bits 12:8. Default value is 00101b,
1229 /// indicating energy unit is in 32 microJoules increment.
1230 ///
1231 UINT32 EnergyStatusUnits:5;
1232 UINT32 Reserved2:3;
1233 ///
1234 /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
1235 /// one second.
1236 ///
1237 UINT32 TimeUnits:4;
1238 UINT32 Reserved3:12;
1239 UINT32 Reserved4:32;
1240 } Bits;
1241 ///
1242 /// All bit fields as a 32-bit value
1243 ///
1244 UINT32 Uint32;
1245 ///
1246 /// All bit fields as a 64-bit value
1247 ///
1248 UINT64 Uint64;
1249 } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
1250
1251
1252 /**
1253 Package. PKG RAPL Power Limit Control (R/W).
1254
1255 @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
1256 @param EAX Lower 32-bits of MSR value.
1257 Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1258 @param EDX Upper 32-bits of MSR value.
1259 Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1260
1261 <b>Example usage</b>
1262 @code
1263 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;
1264
1265 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
1266 AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
1267 @endcode
1268 @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1269 **/
1270 #define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610
1271
1272 /**
1273 MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
1274 **/
1275 typedef union {
1276 ///
1277 /// Individual bit fields
1278 ///
1279 struct {
1280 ///
1281 /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
1282 /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.
1283 ///
1284 UINT32 Limit:15;
1285 ///
1286 /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
1287 /// RAPL Domain.".
1288 ///
1289 UINT32 Enable:1;
1290 ///
1291 /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
1292 /// "Package RAPL Domain.".
1293 ///
1294 UINT32 ClampingLimit:1;
1295 ///
1296 /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
1297 /// If 0 is specified in bits [23:17], defaults to 1 second window.
1298 ///
1299 UINT32 Time:7;
1300 UINT32 Reserved1:8;
1301 UINT32 Reserved2:32;
1302 } Bits;
1303 ///
1304 /// All bit fields as a 32-bit value
1305 ///
1306 UINT32 Uint32;
1307 ///
1308 /// All bit fields as a 64-bit value
1309 ///
1310 UINT64 Uint64;
1311 } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
1312
1313
1314 /**
1315 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
1316 and MSR_RAPL_POWER_UNIT in Table 35-7.
1317
1318 @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
1319 @param EAX Lower 32-bits of MSR value.
1320 @param EDX Upper 32-bits of MSR value.
1321
1322 <b>Example usage</b>
1323 @code
1324 UINT64 Msr;
1325
1326 Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
1327 @endcode
1328 @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1329 **/
1330 #define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611
1331
1332
1333 /**
1334 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1335 Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
1336
1337 @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
1338 @param EAX Lower 32-bits of MSR value.
1339 @param EDX Upper 32-bits of MSR value.
1340
1341 <b>Example usage</b>
1342 @code
1343 UINT64 Msr;
1344
1345 Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
1346 @endcode
1347 @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1348 **/
1349 #define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639
1350
1351
1352 /**
1353 Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
1354 policy. Writing a value of 0 disables core level HW demotion policy.
1355
1356 @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
1357 @param EAX Lower 32-bits of MSR value.
1358 @param EDX Upper 32-bits of MSR value.
1359
1360 <b>Example usage</b>
1361 @code
1362 UINT64 Msr;
1363
1364 Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
1365 AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
1366 @endcode
1367 @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
1368 **/
1369 #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
1370
1371
1372 /**
1373 Package. Module C6 demotion policy config MSR. Controls module (i.e. two
1374 cores sharing the second-level cache) C6 demotion policy. Writing a value of
1375 0 disables module level HW demotion policy.
1376
1377 @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
1378 @param EAX Lower 32-bits of MSR value.
1379 @param EDX Upper 32-bits of MSR value.
1380
1381 <b>Example usage</b>
1382 @code
1383 UINT64 Msr;
1384
1385 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
1386 AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
1387 @endcode
1388 @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
1389 **/
1390 #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
1391
1392
1393 /**
1394 Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
1395 specific C-state code names, unrelated to MWAIT extension C-state parameters
1396 or ACPI CStates. Time that this module is in module-specific C6 states since
1397 last reset. Counts at 1 Mhz frequency.
1398
1399 @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
1400 @param EAX Lower 32-bits of MSR value.
1401 @param EDX Upper 32-bits of MSR value.
1402
1403 <b>Example usage</b>
1404 @code
1405 UINT64 Msr;
1406
1407 Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
1408 @endcode
1409 @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
1410 **/
1411 #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664
1412
1413
1414 /**
1415 Package. PKG RAPL Parameter (R/0).
1416
1417 @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
1418 @param EAX Lower 32-bits of MSR value.
1419 Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1420 @param EDX Upper 32-bits of MSR value.
1421 Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1422
1423 <b>Example usage</b>
1424 @code
1425 MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;
1426
1427 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
1428 @endcode
1429 @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1430 **/
1431 #define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E
1432
1433 /**
1434 MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
1435 **/
1436 typedef union {
1437 ///
1438 /// Individual bit fields
1439 ///
1440 struct {
1441 ///
1442 /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
1443 /// the equivalent of thermal specification power of the package domain.
1444 /// The unit of this field is specified by the "Power Units" field of
1445 /// MSR_RAPL_POWER_UNIT.
1446 ///
1447 UINT32 ThermalSpecPower:15;
1448 UINT32 Reserved1:17;
1449 UINT32 Reserved2:32;
1450 } Bits;
1451 ///
1452 /// All bit fields as a 32-bit value
1453 ///
1454 UINT32 Uint32;
1455 ///
1456 /// All bit fields as a 64-bit value
1457 ///
1458 UINT64 Uint64;
1459 } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
1460
1461
1462 /**
1463 Package. PP0 RAPL Power Limit Control (R/W).
1464
1465 @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
1466 @param EAX Lower 32-bits of MSR value.
1467 Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1468 @param EDX Upper 32-bits of MSR value.
1469 Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1470
1471 <b>Example usage</b>
1472 @code
1473 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;
1474
1475 Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
1476 AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
1477 @endcode
1478 @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1479 **/
1480 #define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638
1481
1482 /**
1483 MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
1484 **/
1485 typedef union {
1486 ///
1487 /// Individual bit fields
1488 ///
1489 struct {
1490 ///
1491 /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1492 /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
1493 ///
1494 UINT32 Limit:15;
1495 ///
1496 /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1497 /// RAPL Domains.".
1498 ///
1499 UINT32 Enable:1;
1500 UINT32 Reserved1:1;
1501 ///
1502 /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
1503 /// duration over which the average power must remain below
1504 /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
1505 /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
1506 /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
1507 /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
1508 /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
1509 /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
1510 ///
1511 UINT32 Time:7;
1512 UINT32 Reserved2:8;
1513 UINT32 Reserved3:32;
1514 } Bits;
1515 ///
1516 /// All bit fields as a 32-bit value
1517 ///
1518 UINT32 Uint32;
1519 ///
1520 /// All bit fields as a 64-bit value
1521 ///
1522 UINT64 Uint64;
1523 } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
1524
1525 #endif
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