UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.
  21
  22 **/
  23
  24 #ifndef __XEON_E7_MSR_H__
  25 #define __XEON_E7_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Package. Reserved Attempt to read/write will cause #UD.
  31
  32   @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
  33   @param  EAX  Lower 32-bits of MSR value.
  34   @param  EDX  Upper 32-bits of MSR value.
  35
  36   <b>Example usage</b>
  37   @code
  38   UINT64  Msr;
  39
  40   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
  41   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
  42   @endcode
  43   @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
  44 **/
  45 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD
  46
  47
  48 /**
  49   Package. Uncore C-box 8 perfmon local box control MSR.
  50
  51   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
  52   @param  EAX  Lower 32-bits of MSR value.
  53   @param  EDX  Upper 32-bits of MSR value.
  54
  55   <b>Example usage</b>
  56   @code
  57   UINT64  Msr;
  58
  59   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
  60   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
  61   @endcode
  62   @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
  63 **/
  64 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40
  65
  66
  67 /**
  68   Package. Uncore C-box 8 perfmon local box status MSR.
  69
  70   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
  71   @param  EAX  Lower 32-bits of MSR value.
  72   @param  EDX  Upper 32-bits of MSR value.
  73
  74   <b>Example usage</b>
  75   @code
  76   UINT64  Msr;
  77
  78   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
  79   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
  80   @endcode
  81   @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
  82 **/
  83 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41
  84
  85
  86 /**
  87   Package. Uncore C-box 8 perfmon local box overflow control MSR.
  88
  89   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
  90   @param  EAX  Lower 32-bits of MSR value.
  91   @param  EDX  Upper 32-bits of MSR value.
  92
  93   <b>Example usage</b>
  94   @code
  95   UINT64  Msr;
  96
  97   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
  98   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
  99   @endcode
 100   @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
 101 **/
 102 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42
 103
 104
 105 /**
 106   Package. Uncore C-box 8 perfmon event select MSR.
 107
 108   @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
 109   @param  EAX  Lower 32-bits of MSR value.
 110   @param  EDX  Upper 32-bits of MSR value.
 111
 112   <b>Example usage</b>
 113   @code
 114   UINT64  Msr;
 115
 116   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
 117   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
 118   @endcode
 119   @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
 120         MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
 121         MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
 122         MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
 123         MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
 124         MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
 125   @{
 126 **/
 127 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50
 128 #define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52
 129 #define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54
 130 #define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56
 131 #define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58
 132 #define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A
 133 /// @}
 134
 135
 136 /**
 137   Package. Uncore C-box 8 perfmon counter MSR.
 138
 139   @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
 140   @param  EAX  Lower 32-bits of MSR value.
 141   @param  EDX  Upper 32-bits of MSR value.
 142
 143   <b>Example usage</b>
 144   @code
 145   UINT64  Msr;
 146
 147   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
 148   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
 149   @endcode
 150   @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
 151         MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
 152         MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
 153         MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
 154         MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
 155         MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
 156   @{
 157 **/
 158 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51
 159 #define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53
 160 #define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55
 161 #define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57
 162 #define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59
 163 #define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B
 164 /// @}
 165
 166
 167 /**
 168   Package. Uncore C-box 9 perfmon local box control MSR.
 169
 170   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
 171   @param  EAX  Lower 32-bits of MSR value.
 172   @param  EDX  Upper 32-bits of MSR value.
 173
 174   <b>Example usage</b>
 175   @code
 176   UINT64  Msr;
 177
 178   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
 179   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
 180   @endcode
 181   @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
 182 **/
 183 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0
 184
 185
 186 /**
 187   Package. Uncore C-box 9 perfmon local box status MSR.
 188
 189   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
 190   @param  EAX  Lower 32-bits of MSR value.
 191   @param  EDX  Upper 32-bits of MSR value.
 192
 193   <b>Example usage</b>
 194   @code
 195   UINT64  Msr;
 196
 197   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
 198   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
 199   @endcode
 200   @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 201 **/
 202 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1
 203
 204
 205 /**
 206   Package. Uncore C-box 9 perfmon local box overflow control MSR.
 207
 208   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
 209   @param  EAX  Lower 32-bits of MSR value.
 210   @param  EDX  Upper 32-bits of MSR value.
 211
 212   <b>Example usage</b>
 213   @code
 214   UINT64  Msr;
 215
 216   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
 217   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
 218   @endcode
 219   @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
 220 **/
 221 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2
 222
 223
 224 /**
 225   Package. Uncore C-box 9 perfmon event select MSR.
 226
 227   @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn
 228   @param  EAX  Lower 32-bits of MSR value.
 229   @param  EDX  Upper 32-bits of MSR value.
 230
 231   <b>Example usage</b>
 232   @code
 233   UINT64  Msr;
 234
 235   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
 236   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
 237   @endcode
 238   @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
 239         MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
 240         MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
 241         MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
 242         MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
 243         MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
 244   @{
 245 **/
 246 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0
 247 #define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2
 248 #define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4
 249 #define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6
 250 #define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8
 251 #define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA
 252 /// @}
 253
 254
 255 /**
 256   Package. Uncore C-box 9 perfmon counter MSR.
 257
 258   @param  ECX  MSR_XEON_E7_C9_PMON_CTRn
 259   @param  EAX  Lower 32-bits of MSR value.
 260   @param  EDX  Upper 32-bits of MSR value.
 261
 262   <b>Example usage</b>
 263   @code
 264   UINT64  Msr;
 265
 266   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
 267   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
 268   @endcode
 269   @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
 270         MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
 271         MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
 272         MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
 273         MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
 274         MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
 275   @{
 276 **/
 277 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1
 278 #define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3
 279 #define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5
 280 #define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7
 281 #define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9
 282 #define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB
 283 /// @}
 284
 285 #endif