UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index b95f963b1ed13f56766f78449684229e35b84199..3128c4b8dd11b5238df079e38b2ce9423cd398cb 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);\r
   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
 **/\r
 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD\r
 \r
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40\r
 \r
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41\r
 \r
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42\r
 \r
@@ -112,6 +116,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.\r
+        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50\r
@@ -137,6 +147,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.\r
+        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51\r
@@ -162,6 +178,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0\r
 \r
@@ -180,6 +197,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1\r
 \r
@@ -198,6 +216,7 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2\r
 \r
@@ -216,6 +235,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.\r
+        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0\r
@@ -241,6 +266,12 @@
   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);\r
   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);\r
   @endcode\r
+  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.\r
+        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
   @{\r
 **/\r
 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1\r