UefiCpuPkg: Clean up source files
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
1 /** @file
2 Local APIC Library.
3
4 This local APIC library instance supports xAPIC mode only.
5
6 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
7 Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
8
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #include <Register/Cpuid.h>
20 #include <Register/Amd/Cpuid.h>
21 #include <Register/Msr.h>
22 #include <Register/LocalApic.h>
23
24 #include <Library/BaseLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/LocalApicLib.h>
27 #include <Library/IoLib.h>
28 #include <Library/TimerLib.h>
29 #include <Library/PcdLib.h>
30
31 //
32 // Library internal functions
33 //
34
35 /**
36 Determine if the standard CPU signature is "AuthenticAMD".
37
38 @retval TRUE The CPU signature matches.
39 @retval FALSE The CPU signature does not match.
40
41 **/
42 BOOLEAN
43 StandardSignatureIsAuthenticAMD (
44 VOID
45 )
46 {
47 UINT32 RegEbx;
48 UINT32 RegEcx;
49 UINT32 RegEdx;
50
51 AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
52 return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
53 RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
54 RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
55 }
56
57 /**
58 Determine if the CPU supports the Local APIC Base Address MSR.
59
60 @retval TRUE The CPU supports the Local APIC Base Address MSR.
61 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
62
63 **/
64 BOOLEAN
65 LocalApicBaseAddressMsrSupported (
66 VOID
67 )
68 {
69 UINT32 RegEax;
70 UINTN FamilyId;
71
72 AsmCpuid (1, &RegEax, NULL, NULL, NULL);
73 FamilyId = BitFieldRead32 (RegEax, 8, 11);
74 if (FamilyId == 0x04 || FamilyId == 0x05) {
75 //
76 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
77 // Local APIC Base Address MSR
78 //
79 return FALSE;
80 }
81 return TRUE;
82 }
83
84 /**
85 Retrieve the base address of local APIC.
86
87 @return The base address of local APIC.
88
89 **/
90 UINTN
91 EFIAPI
92 GetLocalApicBaseAddress (
93 VOID
94 )
95 {
96 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
97
98 if (!LocalApicBaseAddressMsrSupported ()) {
99 //
100 // If CPU does not support Local APIC Base Address MSR, then retrieve
101 // Local APIC Base Address from PCD
102 //
103 return PcdGet32 (PcdCpuLocalApicBaseAddress);
104 }
105
106 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
107
108 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
109 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
110 }
111
112 /**
113 Set the base address of local APIC.
114
115 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
116
117 @param[in] BaseAddress Local APIC base address to be set.
118
119 **/
120 VOID
121 EFIAPI
122 SetLocalApicBaseAddress (
123 IN UINTN BaseAddress
124 )
125 {
126 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
127
128 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
129
130 if (!LocalApicBaseAddressMsrSupported ()) {
131 //
132 // Ignore set request if the CPU does not support APIC Base Address MSR
133 //
134 return;
135 }
136
137 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
138
139 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
140 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
141
142 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
143 }
144
145 /**
146 Read from a local APIC register.
147
148 This function reads from a local APIC register either in xAPIC or x2APIC mode.
149 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
150 accessed using multiple 32-bit loads or stores, so this function only performs
151 32-bit read.
152
153 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
154 It must be 16-byte aligned.
155
156 @return 32-bit Value read from the register.
157 **/
158 UINT32
159 EFIAPI
160 ReadLocalApicReg (
161 IN UINTN MmioOffset
162 )
163 {
164 ASSERT ((MmioOffset & 0xf) == 0);
165 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
166
167 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
168 }
169
170 /**
171 Write to a local APIC register.
172
173 This function writes to a local APIC register either in xAPIC or x2APIC mode.
174 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
175 accessed using multiple 32-bit loads or stores, so this function only performs
176 32-bit write.
177
178 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
179
180 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
181 It must be 16-byte aligned.
182 @param Value Value to be written to the register.
183 **/
184 VOID
185 EFIAPI
186 WriteLocalApicReg (
187 IN UINTN MmioOffset,
188 IN UINT32 Value
189 )
190 {
191 ASSERT ((MmioOffset & 0xf) == 0);
192 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
193
194 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
195 }
196
197 /**
198 Send an IPI by writing to ICR.
199
200 This function returns after the IPI has been accepted by the target processor.
201
202 @param IcrLow 32-bit value to be written to the low half of ICR.
203 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
204 **/
205 VOID
206 SendIpi (
207 IN UINT32 IcrLow,
208 IN UINT32 ApicId
209 )
210 {
211 LOCAL_APIC_ICR_LOW IcrLowReg;
212 UINT32 IcrHigh;
213 BOOLEAN InterruptState;
214
215 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
216 ASSERT (ApicId <= 0xff);
217
218 InterruptState = SaveAndDisableInterrupts ();
219
220 //
221 // Save existing contents of ICR high 32 bits
222 //
223 IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);
224
225 //
226 // Wait for DeliveryStatus clear in case a previous IPI
227 // is still being sent
228 //
229 do {
230 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
231 } while (IcrLowReg.Bits.DeliveryStatus != 0);
232
233 //
234 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
235 //
236 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
237 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
238
239 //
240 // Wait for DeliveryStatus clear again
241 //
242 do {
243 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
244 } while (IcrLowReg.Bits.DeliveryStatus != 0);
245
246 //
247 // And restore old contents of ICR high
248 //
249 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
250
251 SetInterruptState (InterruptState);
252
253 }
254
255 //
256 // Library API implementation functions
257 //
258
259 /**
260 Get the current local APIC mode.
261
262 If local APIC is disabled, then ASSERT.
263
264 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
265 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
266 **/
267 UINTN
268 EFIAPI
269 GetApicMode (
270 VOID
271 )
272 {
273 DEBUG_CODE (
274 {
275 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
276
277 //
278 // Check to see if the CPU supports the APIC Base Address MSR
279 //
280 if (LocalApicBaseAddressMsrSupported ()) {
281 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
282 //
283 // Local APIC should have been enabled
284 //
285 ASSERT (ApicBaseMsr.Bits.EN != 0);
286 ASSERT (ApicBaseMsr.Bits.EXTD == 0);
287 }
288 }
289 );
290 return LOCAL_APIC_MODE_XAPIC;
291 }
292
293 /**
294 Set the current local APIC mode.
295
296 If the specified local APIC mode is not valid, then ASSERT.
297 If the specified local APIC mode can't be set as current, then ASSERT.
298
299 @param ApicMode APIC mode to be set.
300
301 @note This API must not be called from an interrupt handler or SMI handler.
302 It may result in unpredictable behavior.
303 **/
304 VOID
305 EFIAPI
306 SetApicMode (
307 IN UINTN ApicMode
308 )
309 {
310 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
311 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
312 }
313
314 /**
315 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
316
317 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
318 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
319 the 32-bit local APIC ID is returned as initial APIC ID.
320
321 @return 32-bit initial local APIC ID of the executing processor.
322 **/
323 UINT32
324 EFIAPI
325 GetInitialApicId (
326 VOID
327 )
328 {
329 UINT32 ApicId;
330 UINT32 MaxCpuIdIndex;
331 UINT32 RegEbx;
332
333 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
334
335 //
336 // Get the max index of basic CPUID
337 //
338 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
339
340 //
341 // If CPUID Leaf B is supported,
342 // And CPUID.0BH:EBX[15:0] reports a non-zero value,
343 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
344 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
345 //
346 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
347 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &RegEbx, NULL, &ApicId);
348 if ((RegEbx & (BIT16 - 1)) != 0) {
349 return ApicId;
350 }
351 }
352
353 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
354 return RegEbx >> 24;
355 }
356
357 /**
358 Get the local APIC ID of the executing processor.
359
360 @return 32-bit local APIC ID of the executing processor.
361 **/
362 UINT32
363 EFIAPI
364 GetApicId (
365 VOID
366 )
367 {
368 UINT32 ApicId;
369
370 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
371
372 if ((ApicId = GetInitialApicId ()) < 0x100) {
373 //
374 // If the initial local APIC ID is less 0x100, read APIC ID from
375 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
376 //
377 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
378 ApicId >>= 24;
379 }
380 return ApicId;
381 }
382
383 /**
384 Get the value of the local APIC version register.
385
386 @return the value of the local APIC version register.
387 **/
388 UINT32
389 EFIAPI
390 GetApicVersion (
391 VOID
392 )
393 {
394 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
395 }
396
397 /**
398 Send a Fixed IPI to a specified target processor.
399
400 This function returns after the IPI has been accepted by the target processor.
401
402 @param ApicId The local APIC ID of the target processor.
403 @param Vector The vector number of the interrupt being sent.
404 **/
405 VOID
406 EFIAPI
407 SendFixedIpi (
408 IN UINT32 ApicId,
409 IN UINT8 Vector
410 )
411 {
412 LOCAL_APIC_ICR_LOW IcrLow;
413
414 IcrLow.Uint32 = 0;
415 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
416 IcrLow.Bits.Level = 1;
417 IcrLow.Bits.Vector = Vector;
418 SendIpi (IcrLow.Uint32, ApicId);
419 }
420
421 /**
422 Send a Fixed IPI to all processors excluding self.
423
424 This function returns after the IPI has been accepted by the target processors.
425
426 @param Vector The vector number of the interrupt being sent.
427 **/
428 VOID
429 EFIAPI
430 SendFixedIpiAllExcludingSelf (
431 IN UINT8 Vector
432 )
433 {
434 LOCAL_APIC_ICR_LOW IcrLow;
435
436 IcrLow.Uint32 = 0;
437 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
438 IcrLow.Bits.Level = 1;
439 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
440 IcrLow.Bits.Vector = Vector;
441 SendIpi (IcrLow.Uint32, 0);
442 }
443
444 /**
445 Send a SMI IPI to a specified target processor.
446
447 This function returns after the IPI has been accepted by the target processor.
448
449 @param ApicId Specify the local APIC ID of the target processor.
450 **/
451 VOID
452 EFIAPI
453 SendSmiIpi (
454 IN UINT32 ApicId
455 )
456 {
457 LOCAL_APIC_ICR_LOW IcrLow;
458
459 IcrLow.Uint32 = 0;
460 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
461 IcrLow.Bits.Level = 1;
462 SendIpi (IcrLow.Uint32, ApicId);
463 }
464
465 /**
466 Send a SMI IPI to all processors excluding self.
467
468 This function returns after the IPI has been accepted by the target processors.
469 **/
470 VOID
471 EFIAPI
472 SendSmiIpiAllExcludingSelf (
473 VOID
474 )
475 {
476 LOCAL_APIC_ICR_LOW IcrLow;
477
478 IcrLow.Uint32 = 0;
479 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
480 IcrLow.Bits.Level = 1;
481 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
482 SendIpi (IcrLow.Uint32, 0);
483 }
484
485 /**
486 Send an INIT IPI to a specified target processor.
487
488 This function returns after the IPI has been accepted by the target processor.
489
490 @param ApicId Specify the local APIC ID of the target processor.
491 **/
492 VOID
493 EFIAPI
494 SendInitIpi (
495 IN UINT32 ApicId
496 )
497 {
498 LOCAL_APIC_ICR_LOW IcrLow;
499
500 IcrLow.Uint32 = 0;
501 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
502 IcrLow.Bits.Level = 1;
503 SendIpi (IcrLow.Uint32, ApicId);
504 }
505
506 /**
507 Send an INIT IPI to all processors excluding self.
508
509 This function returns after the IPI has been accepted by the target processors.
510 **/
511 VOID
512 EFIAPI
513 SendInitIpiAllExcludingSelf (
514 VOID
515 )
516 {
517 LOCAL_APIC_ICR_LOW IcrLow;
518
519 IcrLow.Uint32 = 0;
520 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
521 IcrLow.Bits.Level = 1;
522 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
523 SendIpi (IcrLow.Uint32, 0);
524 }
525
526 /**
527 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
528
529 This function returns after the IPI has been accepted by the target processor.
530
531 if StartupRoutine >= 1M, then ASSERT.
532 if StartupRoutine is not multiple of 4K, then ASSERT.
533
534 @param ApicId Specify the local APIC ID of the target processor.
535 @param StartupRoutine Points to a start-up routine which is below 1M physical
536 address and 4K aligned.
537 **/
538 VOID
539 EFIAPI
540 SendInitSipiSipi (
541 IN UINT32 ApicId,
542 IN UINT32 StartupRoutine
543 )
544 {
545 LOCAL_APIC_ICR_LOW IcrLow;
546
547 ASSERT (StartupRoutine < 0x100000);
548 ASSERT ((StartupRoutine & 0xfff) == 0);
549
550 SendInitIpi (ApicId);
551 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
552 IcrLow.Uint32 = 0;
553 IcrLow.Bits.Vector = (StartupRoutine >> 12);
554 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
555 IcrLow.Bits.Level = 1;
556 SendIpi (IcrLow.Uint32, ApicId);
557 if (!StandardSignatureIsAuthenticAMD ()) {
558 MicroSecondDelay (200);
559 SendIpi (IcrLow.Uint32, ApicId);
560 }
561 }
562
563 /**
564 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
565
566 This function returns after the IPI has been accepted by the target processors.
567
568 if StartupRoutine >= 1M, then ASSERT.
569 if StartupRoutine is not multiple of 4K, then ASSERT.
570
571 @param StartupRoutine Points to a start-up routine which is below 1M physical
572 address and 4K aligned.
573 **/
574 VOID
575 EFIAPI
576 SendInitSipiSipiAllExcludingSelf (
577 IN UINT32 StartupRoutine
578 )
579 {
580 LOCAL_APIC_ICR_LOW IcrLow;
581
582 ASSERT (StartupRoutine < 0x100000);
583 ASSERT ((StartupRoutine & 0xfff) == 0);
584
585 SendInitIpiAllExcludingSelf ();
586 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
587 IcrLow.Uint32 = 0;
588 IcrLow.Bits.Vector = (StartupRoutine >> 12);
589 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
590 IcrLow.Bits.Level = 1;
591 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
592 SendIpi (IcrLow.Uint32, 0);
593 if (!StandardSignatureIsAuthenticAMD ()) {
594 MicroSecondDelay (200);
595 SendIpi (IcrLow.Uint32, 0);
596 }
597 }
598
599 /**
600 Initialize the state of the SoftwareEnable bit in the Local APIC
601 Spurious Interrupt Vector register.
602
603 @param Enable If TRUE, then set SoftwareEnable to 1
604 If FALSE, then set SoftwareEnable to 0.
605
606 **/
607 VOID
608 EFIAPI
609 InitializeLocalApicSoftwareEnable (
610 IN BOOLEAN Enable
611 )
612 {
613 LOCAL_APIC_SVR Svr;
614
615 //
616 // Set local APIC software-enabled bit.
617 //
618 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
619 if (Enable) {
620 if (Svr.Bits.SoftwareEnable == 0) {
621 Svr.Bits.SoftwareEnable = 1;
622 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
623 }
624 } else {
625 if (Svr.Bits.SoftwareEnable == 1) {
626 Svr.Bits.SoftwareEnable = 0;
627 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
628 }
629 }
630 }
631
632 /**
633 Programming Virtual Wire Mode.
634
635 This function programs the local APIC for virtual wire mode following
636 the example described in chapter A.3 of the MP 1.4 spec.
637
638 IOxAPIC is not involved in this type of virtual wire mode.
639 **/
640 VOID
641 EFIAPI
642 ProgramVirtualWireMode (
643 VOID
644 )
645 {
646 LOCAL_APIC_SVR Svr;
647 LOCAL_APIC_LVT_LINT Lint;
648
649 //
650 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
651 //
652 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
653 Svr.Bits.SpuriousVector = 0xf;
654 Svr.Bits.SoftwareEnable = 1;
655 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
656
657 //
658 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
659 //
660 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
661 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
662 Lint.Bits.InputPinPolarity = 0;
663 Lint.Bits.TriggerMode = 0;
664 Lint.Bits.Mask = 0;
665 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
666
667 //
668 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
669 //
670 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
671 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
672 Lint.Bits.InputPinPolarity = 0;
673 Lint.Bits.TriggerMode = 0;
674 Lint.Bits.Mask = 0;
675 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
676 }
677
678 /**
679 Disable LINT0 & LINT1 interrupts.
680
681 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
682 **/
683 VOID
684 EFIAPI
685 DisableLvtInterrupts (
686 VOID
687 )
688 {
689 LOCAL_APIC_LVT_LINT LvtLint;
690
691 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
692 LvtLint.Bits.Mask = 1;
693 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
694
695 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
696 LvtLint.Bits.Mask = 1;
697 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
698 }
699
700 /**
701 Read the initial count value from the init-count register.
702
703 @return The initial count value read from the init-count register.
704 **/
705 UINT32
706 EFIAPI
707 GetApicTimerInitCount (
708 VOID
709 )
710 {
711 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
712 }
713
714 /**
715 Read the current count value from the current-count register.
716
717 @return The current count value read from the current-count register.
718 **/
719 UINT32
720 EFIAPI
721 GetApicTimerCurrentCount (
722 VOID
723 )
724 {
725 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
726 }
727
728 /**
729 Initialize the local APIC timer.
730
731 The local APIC timer is initialized and enabled.
732
733 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
734 If it is 0, then use the current divide value in the DCR.
735 @param InitCount The initial count value.
736 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
737 @param Vector The timer interrupt vector number.
738 **/
739 VOID
740 EFIAPI
741 InitializeApicTimer (
742 IN UINTN DivideValue,
743 IN UINT32 InitCount,
744 IN BOOLEAN PeriodicMode,
745 IN UINT8 Vector
746 )
747 {
748 LOCAL_APIC_DCR Dcr;
749 LOCAL_APIC_LVT_TIMER LvtTimer;
750 UINT32 Divisor;
751
752 //
753 // Ensure local APIC is in software-enabled state.
754 //
755 InitializeLocalApicSoftwareEnable (TRUE);
756
757 //
758 // Program init-count register.
759 //
760 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
761
762 if (DivideValue != 0) {
763 ASSERT (DivideValue <= 128);
764 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
765 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
766
767 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
768 Dcr.Bits.DivideValue1 = (Divisor & 0x3);
769 Dcr.Bits.DivideValue2 = (Divisor >> 2);
770 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
771 }
772
773 //
774 // Enable APIC timer interrupt with specified timer mode.
775 //
776 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
777 if (PeriodicMode) {
778 LvtTimer.Bits.TimerMode = 1;
779 } else {
780 LvtTimer.Bits.TimerMode = 0;
781 }
782 LvtTimer.Bits.Mask = 0;
783 LvtTimer.Bits.Vector = Vector;
784 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
785 }
786
787 /**
788 Get the state of the local APIC timer.
789
790 This function will ASSERT if the local APIC is not software enabled.
791
792 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
793 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
794 @param Vector Return the timer interrupt vector number.
795 **/
796 VOID
797 EFIAPI
798 GetApicTimerState (
799 OUT UINTN *DivideValue OPTIONAL,
800 OUT BOOLEAN *PeriodicMode OPTIONAL,
801 OUT UINT8 *Vector OPTIONAL
802 )
803 {
804 UINT32 Divisor;
805 LOCAL_APIC_DCR Dcr;
806 LOCAL_APIC_LVT_TIMER LvtTimer;
807
808 //
809 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
810 // Vector Register.
811 // This bit will be 1, if local APIC is software enabled.
812 //
813 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
814
815 if (DivideValue != NULL) {
816 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
817 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
818 Divisor = (Divisor + 1) & 0x7;
819 *DivideValue = ((UINTN)1) << Divisor;
820 }
821
822 if (PeriodicMode != NULL || Vector != NULL) {
823 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
824 if (PeriodicMode != NULL) {
825 if (LvtTimer.Bits.TimerMode == 1) {
826 *PeriodicMode = TRUE;
827 } else {
828 *PeriodicMode = FALSE;
829 }
830 }
831 if (Vector != NULL) {
832 *Vector = (UINT8) LvtTimer.Bits.Vector;
833 }
834 }
835 }
836
837 /**
838 Enable the local APIC timer interrupt.
839 **/
840 VOID
841 EFIAPI
842 EnableApicTimerInterrupt (
843 VOID
844 )
845 {
846 LOCAL_APIC_LVT_TIMER LvtTimer;
847
848 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
849 LvtTimer.Bits.Mask = 0;
850 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
851 }
852
853 /**
854 Disable the local APIC timer interrupt.
855 **/
856 VOID
857 EFIAPI
858 DisableApicTimerInterrupt (
859 VOID
860 )
861 {
862 LOCAL_APIC_LVT_TIMER LvtTimer;
863
864 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
865 LvtTimer.Bits.Mask = 1;
866 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
867 }
868
869 /**
870 Get the local APIC timer interrupt state.
871
872 @retval TRUE The local APIC timer interrupt is enabled.
873 @retval FALSE The local APIC timer interrupt is disabled.
874 **/
875 BOOLEAN
876 EFIAPI
877 GetApicTimerInterruptState (
878 VOID
879 )
880 {
881 LOCAL_APIC_LVT_TIMER LvtTimer;
882
883 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
884 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
885 }
886
887 /**
888 Send EOI to the local APIC.
889 **/
890 VOID
891 EFIAPI
892 SendApicEoi (
893 VOID
894 )
895 {
896 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
897 }
898
899 /**
900 Get the 32-bit address that a device should use to send a Message Signaled
901 Interrupt (MSI) to the Local APIC of the currently executing processor.
902
903 @return 32-bit address used to send an MSI to the Local APIC.
904 **/
905 UINT32
906 EFIAPI
907 GetApicMsiAddress (
908 VOID
909 )
910 {
911 LOCAL_APIC_MSI_ADDRESS MsiAddress;
912
913 //
914 // Return address for an MSI interrupt to be delivered only to the APIC ID
915 // of the currently executing processor.
916 //
917 MsiAddress.Uint32 = 0;
918 MsiAddress.Bits.BaseAddress = 0xFEE;
919 MsiAddress.Bits.DestinationId = GetApicId ();
920 return MsiAddress.Uint32;
921 }
922
923 /**
924 Get the 64-bit data value that a device should use to send a Message Signaled
925 Interrupt (MSI) to the Local APIC of the currently executing processor.
926
927 If Vector is not in range 0x10..0xFE, then ASSERT().
928 If DeliveryMode is not supported, then ASSERT().
929
930 @param Vector The 8-bit interrupt vector associated with the MSI.
931 Must be in the range 0x10..0xFE
932 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
933 is handled. The only supported values are:
934 0: LOCAL_APIC_DELIVERY_MODE_FIXED
935 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
936 2: LOCAL_APIC_DELIVERY_MODE_SMI
937 4: LOCAL_APIC_DELIVERY_MODE_NMI
938 5: LOCAL_APIC_DELIVERY_MODE_INIT
939 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
940
941 @param LevelTriggered TRUE specifies a level triggered interrupt.
942 FALSE specifies an edge triggered interrupt.
943 @param AssertionLevel Ignored if LevelTriggered is FALSE.
944 TRUE specifies a level triggered interrupt that active
945 when the interrupt line is asserted.
946 FALSE specifies a level triggered interrupt that active
947 when the interrupt line is deasserted.
948
949 @return 64-bit data value used to send an MSI to the Local APIC.
950 **/
951 UINT64
952 EFIAPI
953 GetApicMsiValue (
954 IN UINT8 Vector,
955 IN UINTN DeliveryMode,
956 IN BOOLEAN LevelTriggered,
957 IN BOOLEAN AssertionLevel
958 )
959 {
960 LOCAL_APIC_MSI_DATA MsiData;
961
962 ASSERT (Vector >= 0x10 && Vector <= 0xFE);
963 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
964
965 MsiData.Uint64 = 0;
966 MsiData.Bits.Vector = Vector;
967 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
968 if (LevelTriggered) {
969 MsiData.Bits.TriggerMode = 1;
970 if (AssertionLevel) {
971 MsiData.Bits.Level = 1;
972 }
973 }
974 return MsiData.Uint64;
975 }
976
977 /**
978 Get Package ID/Core ID/Thread ID of a processor.
979
980 The algorithm assumes the target system has symmetry across physical
981 package boundaries with respect to the number of logical processors
982 per package, number of cores per package.
983
984 @param[in] InitialApicId Initial APIC ID of the target logical processor.
985 @param[out] Package Returns the processor package ID.
986 @param[out] Core Returns the processor core ID.
987 @param[out] Thread Returns the processor thread ID.
988 **/
989 VOID
990 EFIAPI
991 GetProcessorLocationByApicId (
992 IN UINT32 InitialApicId,
993 OUT UINT32 *Package OPTIONAL,
994 OUT UINT32 *Core OPTIONAL,
995 OUT UINT32 *Thread OPTIONAL
996 )
997 {
998 BOOLEAN TopologyLeafSupported;
999 CPUID_VERSION_INFO_EBX VersionInfoEbx;
1000 CPUID_VERSION_INFO_EDX VersionInfoEdx;
1001 CPUID_CACHE_PARAMS_EAX CacheParamsEax;
1002 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
1003 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
1004 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
1005 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
1006 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
1007 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
1008 UINT32 MaxStandardCpuIdIndex;
1009 UINT32 MaxExtendedCpuIdIndex;
1010 UINT32 SubIndex;
1011 UINTN LevelType;
1012 UINT32 MaxLogicProcessorsPerPackage;
1013 UINT32 MaxCoresPerPackage;
1014 UINTN ThreadBits;
1015 UINTN CoreBits;
1016
1017 //
1018 // Check if the processor is capable of supporting more than one logical processor.
1019 //
1020 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
1021 if (VersionInfoEdx.Bits.HTT == 0) {
1022 if (Thread != NULL) {
1023 *Thread = 0;
1024 }
1025 if (Core != NULL) {
1026 *Core = 0;
1027 }
1028 if (Package != NULL) {
1029 *Package = 0;
1030 }
1031 return;
1032 }
1033
1034 //
1035 // Assume three-level mapping of APIC ID: Package|Core|Thread.
1036 //
1037 ThreadBits = 0;
1038 CoreBits = 0;
1039
1040 //
1041 // Get max index of CPUID
1042 //
1043 AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
1044 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
1045
1046 //
1047 // If the extended topology enumeration leaf is available, it
1048 // is the preferred mechanism for enumerating topology.
1049 //
1050 TopologyLeafSupported = FALSE;
1051 if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
1052 AsmCpuidEx(
1053 CPUID_EXTENDED_TOPOLOGY,
1054 0,
1055 &ExtendedTopologyEax.Uint32,
1056 &ExtendedTopologyEbx.Uint32,
1057 &ExtendedTopologyEcx.Uint32,
1058 NULL
1059 );
1060 //
1061 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
1062 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
1063 // supported on that processor.
1064 //
1065 if (ExtendedTopologyEbx.Uint32 != 0) {
1066 TopologyLeafSupported = TRUE;
1067
1068 //
1069 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
1070 // the SMT sub-field of x2APIC ID.
1071 //
1072 LevelType = ExtendedTopologyEcx.Bits.LevelType;
1073 ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
1074 ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
1075
1076 //
1077 // Software must not assume any "level type" encoding
1078 // value to be related to any sub-leaf index, except sub-leaf 0.
1079 //
1080 SubIndex = 1;
1081 do {
1082 AsmCpuidEx (
1083 CPUID_EXTENDED_TOPOLOGY,
1084 SubIndex,
1085 &ExtendedTopologyEax.Uint32,
1086 NULL,
1087 &ExtendedTopologyEcx.Uint32,
1088 NULL
1089 );
1090 LevelType = ExtendedTopologyEcx.Bits.LevelType;
1091 if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
1092 CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
1093 break;
1094 }
1095 SubIndex++;
1096 } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
1097 }
1098 }
1099
1100 if (!TopologyLeafSupported) {
1101 //
1102 // Get logical processor count
1103 //
1104 AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
1105 MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
1106
1107 //
1108 // Assume single-core processor
1109 //
1110 MaxCoresPerPackage = 1;
1111
1112 //
1113 // Check for topology extensions on AMD processor
1114 //
1115 if (StandardSignatureIsAuthenticAMD()) {
1116 if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
1117 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
1118 if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
1119 //
1120 // Account for max possible thread count to decode ApicId
1121 //
1122 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
1123 MaxLogicProcessorsPerPackage = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
1124
1125 //
1126 // Get cores per processor package
1127 //
1128 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32, NULL, NULL);
1129 MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
1130 }
1131 }
1132 }
1133 else {
1134 //
1135 // Extract core count based on CACHE information
1136 //
1137 if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
1138 AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
1139 if (CacheParamsEax.Uint32 != 0) {
1140 MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
1141 }
1142 }
1143 }
1144
1145 ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
1146 CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
1147 }
1148
1149 if (Thread != NULL) {
1150 *Thread = InitialApicId & ((1 << ThreadBits) - 1);
1151 }
1152 if (Core != NULL) {
1153 *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
1154 }
1155 if (Package != NULL) {
1156 *Package = (InitialApicId >> (ThreadBits + CoreBits));
1157 }
1158 }