UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c

   1 /** @file
   2   Intel Processor Trace feature.
   3
   4   Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "CpuCommonFeatures.h"
  16
  17 ///
  18 /// This macro define the max entries in the Topa table.
  19 /// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
  20 /// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
  21 /// current table (for circular array) or to the base of another table.
  22 /// At least 2 entries are needed because the list of entries must
  23 /// be terminated by an entry with the END bit set to 1, so 2
  24 /// entries are required to use a single valid entry.
  25 ///
  26 #define MAX_TOPA_ENTRY_COUNT         2
  27
  28
  29 ///
  30 /// Processor trace output scheme selection.
  31 ///
  32 typedef enum {
  33   RtitOutputSchemeSingleRange = 0,
  34   RtitOutputSchemeToPA
  35 } RTIT_OUTPUT_SCHEME;
  36
  37 typedef struct  {
  38   BOOLEAN  ProcTraceSupported;
  39   BOOLEAN  TopaSupported;
  40   BOOLEAN  SingleRangeSupported;
  41 } PROC_TRACE_PROCESSOR_DATA;
  42
  43 typedef struct  {
  44   UINT32                      NumberOfProcessors;
  45
  46   UINT8                       ProcTraceOutputScheme;
  47   UINT32                      ProcTraceMemSize;
  48
  49   UINTN                       *ThreadMemRegionTable;
  50   UINTN                       AllocatedThreads;
  51
  52   UINTN                       *TopaMemArray;
  53   UINTN                       TopaMemArrayCount;
  54
  55   PROC_TRACE_PROCESSOR_DATA   *ProcessorData;
  56 } PROC_TRACE_DATA;
  57
  58 typedef struct {
  59   RTIT_TOPA_TABLE_ENTRY    TopaEntry[MAX_TOPA_ENTRY_COUNT];
  60 } PROC_TRACE_TOPA_TABLE;
  61
  62 /**
  63   Prepares for the data used by CPU feature detection and initialization.
  64
  65   @param[in]  NumberOfProcessors  The number of CPUs in the platform.
  66
  67   @return  Pointer to a buffer of CPU related configuration data.
  68
  69   @note This service could be called by BSP only.
  70 **/
  71 VOID *
  72 EFIAPI
  73 ProcTraceGetConfigData (
  74   IN UINTN  NumberOfProcessors
  75   )
  76 {
  77   PROC_TRACE_DATA  *ConfigData;
  78
  79   ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
  80   ASSERT (ConfigData != NULL);
  81   ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));
  82
  83   ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;
  84   ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
  85   ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
  86
  87   return ConfigData;
  88 }
  89
  90 /**
  91   Detects if Intel Processor Trace feature supported on current
  92   processor.
  93
  94   @param[in]  ProcessorNumber  The index of the CPU executing this function.
  95   @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION
  96                                structure for the CPU executing this function.
  97   @param[in]  ConfigData       A pointer to the configuration buffer returned
  98                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if
  99                                CPU_FEATURE_GET_CONFIG_DATA was not provided in
 100                                RegisterCpuFeature().
 101
 102   @retval TRUE     Processor Trace feature is supported.
 103   @retval FALSE    Processor Trace feature is not supported.
 104
 105   @note This service could be called by BSP/APs.
 106 **/
 107 BOOLEAN
 108 EFIAPI
 109 ProcTraceSupport (
 110   IN UINTN                             ProcessorNumber,
 111   IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
 112   IN VOID                              *ConfigData  OPTIONAL
 113   )
 114 {
 115   PROC_TRACE_DATA                             *ProcTraceData;
 116   CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
 117   CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX   Ecx;
 118
 119   //
 120   // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
 121   //
 122   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
 123   ASSERT (ProcTraceData != NULL);
 124   if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
 125       (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {
 126     return FALSE;
 127   }
 128
 129   //
 130   // Check if Processor Trace is supported
 131   //
 132   AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
 133   ProcTraceData->ProcessorData[ProcessorNumber].ProcTraceSupported = (BOOLEAN) (Ebx.Bits.IntelProcessorTrace == 1);
 134   if (!ProcTraceData->ProcessorData[ProcessorNumber].ProcTraceSupported) {
 135     return FALSE;
 136   }
 137
 138   AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
 139   ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);
 140   ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);
 141   if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
 142       (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {
 143     return TRUE;
 144   }
 145
 146   return FALSE;
 147 }
 148
 149 /**
 150   Initializes Intel Processor Trace feature to specific state.
 151
 152   @param[in]  ProcessorNumber  The index of the CPU executing this function.
 153   @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION
 154                                structure for the CPU executing this function.
 155   @param[in]  ConfigData       A pointer to the configuration buffer returned
 156                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if
 157                                CPU_FEATURE_GET_CONFIG_DATA was not provided in
 158                                RegisterCpuFeature().
 159   @param[in]  State            If TRUE, then the Processor Trace feature must be
 160                                enabled.
 161                                If FALSE, then the Processor Trace feature must be
 162                                disabled.
 163
 164   @retval RETURN_SUCCESS       Intel Processor Trace feature is initialized.
 165
 166 **/
 167 RETURN_STATUS
 168 EFIAPI
 169 ProcTraceInitialize (
 170   IN UINTN                             ProcessorNumber,
 171   IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
 172   IN VOID                              *ConfigData,  OPTIONAL
 173   IN BOOLEAN                           State
 174   )
 175 {
 176   UINT32                               MemRegionSize;
 177   UINTN                                Pages;
 178   UINTN                                Alignment;
 179   UINTN                                MemRegionBaseAddr;
 180   UINTN                                *ThreadMemRegionTable;
 181   UINTN                                Index;
 182   UINTN                                TopaTableBaseAddr;
 183   UINTN                                AlignedAddress;
 184   UINTN                                *TopaMemArray;
 185   PROC_TRACE_TOPA_TABLE                *TopaTable;
 186   PROC_TRACE_DATA                      *ProcTraceData;
 187   BOOLEAN                              FirstIn;
 188   MSR_IA32_RTIT_CTL_REGISTER           CtrlReg;
 189   MSR_IA32_RTIT_STATUS_REGISTER        StatusReg;
 190   MSR_IA32_RTIT_OUTPUT_BASE_REGISTER   OutputBaseReg;
 191   MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  OutputMaskPtrsReg;
 192   RTIT_TOPA_TABLE_ENTRY                *TopaEntryPtr;
 193
 194   //
 195   // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
 196   // MSR_IA32_RTIT_* for thread 0 in each core.
 197   //
 198   if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
 199       IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
 200     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
 201       return RETURN_SUCCESS;
 202     }
 203   }
 204
 205   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
 206   ASSERT (ProcTraceData != NULL);
 207
 208   MemRegionBaseAddr = 0;
 209   FirstIn = FALSE;
 210
 211   if (ProcTraceData->ThreadMemRegionTable == NULL) {
 212     FirstIn = TRUE;
 213     DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));
 214   }
 215
 216   ///
 217   /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
 218   ///
 219   MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
 220   if (FirstIn) {
 221     DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
 222   }
 223
 224   //
 225   // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b
 226   //
 227   CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 228   if (CtrlReg.Bits.TraceEn != 0) {
 229     ///
 230     /// Clear bit 0 in MSR IA32_RTIT_CTL (570)
 231     ///
 232     CtrlReg.Bits.TraceEn = 0;
 233     CPU_REGISTER_TABLE_WRITE64 (
 234       ProcessorNumber,
 235       Msr,
 236       MSR_IA32_RTIT_CTL,
 237       CtrlReg.Uint64
 238       );
 239
 240     ///
 241     /// Clear MSR IA32_RTIT_STS (571h) to all zeros
 242     ///
 243     StatusReg.Uint64 = 0x0;
 244     CPU_REGISTER_TABLE_WRITE64 (
 245       ProcessorNumber,
 246       Msr,
 247       MSR_IA32_RTIT_STATUS,
 248       StatusReg.Uint64
 249       );
 250   }
 251
 252   if (FirstIn) {
 253     //
 254     //   Let BSP allocate and create the necessary memory region (Aligned to the size of
 255     //   the memory region from setup option(ProcTraceMemSize) which is an integral multiple of 4kB)
 256     //   for the all the enabled threads for storing Processor Trace debug data. Then Configure the trace
 257     //   address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
 258     //   aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 clear.
 259     //
 260     ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
 261     if (ThreadMemRegionTable == NULL) {
 262       DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
 263       return RETURN_OUT_OF_RESOURCES;
 264     }
 265     ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
 266
 267     for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
 268       Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
 269       Alignment = MemRegionSize;
 270       AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
 271       if (AlignedAddress == 0) {
 272         DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
 273         if (Index == 0) {
 274           //
 275           // Could not allocate for BSP even
 276           //
 277           FreePool ((VOID *) ThreadMemRegionTable);
 278           ThreadMemRegionTable = NULL;
 279           return RETURN_OUT_OF_RESOURCES;
 280         }
 281         break;
 282       }
 283
 284       ThreadMemRegionTable[Index] = AlignedAddress;
 285       DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));
 286     }
 287
 288     DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
 289     MemRegionBaseAddr = ThreadMemRegionTable[0];
 290   } else {
 291     if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
 292       MemRegionBaseAddr = ProcTraceData->ThreadMemRegionTable[ProcessorNumber];
 293     } else {
 294       return RETURN_SUCCESS;
 295     }
 296   }
 297
 298   ///
 299   /// Check Processor Trace output scheme: Single Range output or ToPA table
 300   ///
 301
 302   //
 303   //  Single Range output scheme
 304   //
 305   if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
 306       (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
 307     if (FirstIn) {
 308       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
 309     }
 310
 311     //
 312     // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
 313     //
 314     CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 315     CtrlReg.Bits.ToPA = 0;
 316     CPU_REGISTER_TABLE_WRITE64 (
 317       ProcessorNumber,
 318       Msr,
 319       MSR_IA32_RTIT_CTL,
 320       CtrlReg.Uint64
 321       );
 322
 323     //
 324     // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
 325     //
 326     OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
 327     OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
 328     CPU_REGISTER_TABLE_WRITE64 (
 329       ProcessorNumber,
 330       Msr,
 331       MSR_IA32_RTIT_OUTPUT_BASE,
 332       OutputBaseReg.Uint64
 333       );
 334
 335     //
 336     // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
 337     //
 338     OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;
 339     OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
 340     CPU_REGISTER_TABLE_WRITE64 (
 341       ProcessorNumber,
 342       Msr,
 343       MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
 344       OutputMaskPtrsReg.Uint64
 345       );
 346   }
 347
 348   //
 349   //  ToPA(Table of physical address) scheme
 350   //
 351   if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
 352       (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
 353     //
 354     //  Create ToPA structure aligned at 4KB for each logical thread
 355     //  with at least 2 entries by 8 bytes size each. The first entry
 356     //  should have the trace output base address in bits 47:12, 6:9
 357     //  for Size, bits 4,2 and 0 must be cleared. The second entry
 358     //  should have the base address of the table location in bits
 359     //  47:12, bits 4 and 2 must be cleared and bit 0 must be set.
 360     //
 361     if (FirstIn) {
 362       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n"));
 363       //
 364       // Let BSP allocate ToPA table mem for all threads
 365       //
 366       TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
 367       if (TopaMemArray == NULL) {
 368         DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
 369         return RETURN_OUT_OF_RESOURCES;
 370       }
 371       ProcTraceData->TopaMemArray = TopaMemArray;
 372
 373       for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
 374         Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
 375         Alignment = 0x1000;
 376         AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
 377         if (AlignedAddress == 0) {
 378           if (Index < ProcTraceData->AllocatedThreads) {
 379             ProcTraceData->AllocatedThreads = Index;
 380           }
 381           DEBUG ((DEBUG_ERROR, "ProcTrace:  Out of mem, allocating ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
 382           if (Index == 0) {
 383             //
 384             // Could not allocate for BSP
 385             //
 386             FreePool ((VOID *) TopaMemArray);
 387             TopaMemArray = NULL;
 388             return RETURN_OUT_OF_RESOURCES;
 389           }
 390           break;
 391         }
 392
 393         TopaMemArray[Index] = AlignedAddress;
 394         DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index,  (UINT64) TopaMemArray[Index]));
 395       }
 396
 397       DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
 398       //
 399       // BSP gets the first block
 400       //
 401       TopaTableBaseAddr = TopaMemArray[0];
 402     } else {
 403       //
 404       // Count for currently executing AP.
 405       //
 406       if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
 407         TopaTableBaseAddr = ProcTraceData->TopaMemArray[ProcessorNumber];
 408       } else {
 409         return RETURN_SUCCESS;
 410       }
 411     }
 412
 413     TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;
 414     TopaEntryPtr = &TopaTable->TopaEntry[0];
 415     TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
 416     TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
 417     TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
 418     TopaEntryPtr->Bits.END = 0;
 419
 420     TopaEntryPtr = &TopaTable->TopaEntry[1];
 421     TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
 422     TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
 423     TopaEntryPtr->Bits.END = 1;
 424
 425     //
 426     // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
 427     //
 428     OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
 429     OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
 430     CPU_REGISTER_TABLE_WRITE64 (
 431       ProcessorNumber,
 432       Msr,
 433       MSR_IA32_RTIT_OUTPUT_BASE,
 434       OutputBaseReg.Uint64
 435       );
 436
 437     //
 438     // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
 439     //
 440     OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;
 441     OutputMaskPtrsReg.Bits.OutputOffset = 0;
 442     CPU_REGISTER_TABLE_WRITE64 (
 443       ProcessorNumber,
 444       Msr,
 445       MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
 446       OutputMaskPtrsReg.Uint64
 447       );
 448     //
 449     // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
 450     //
 451     CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 452     CtrlReg.Bits.ToPA = 1;
 453     CPU_REGISTER_TABLE_WRITE64 (
 454       ProcessorNumber,
 455       Msr,
 456       MSR_IA32_RTIT_CTL,
 457       CtrlReg.Uint64
 458       );
 459   }
 460
 461   ///
 462   /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
 463   ///
 464   CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 465   CtrlReg.Bits.OS = 1;
 466   CtrlReg.Bits.User = 1;
 467   CtrlReg.Bits.BranchEn = 1;
 468   if (!State) {
 469     CtrlReg.Bits.TraceEn = 0;
 470   } else {
 471     CtrlReg.Bits.TraceEn = 1;
 472   }
 473   CPU_REGISTER_TABLE_WRITE64 (
 474     ProcessorNumber,
 475     Msr,
 476     MSR_IA32_RTIT_CTL,
 477     CtrlReg.Uint64
 478     );
 479
 480   return RETURN_SUCCESS;
 481 }