1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
21 %include "StuffRsb.inc"
23 %define MSR_IA32_MISC_ENABLE 0x1A0
24 %define MSR_EFER 0xc0000080
25 %define MSR_EFER_XD 0x800
28 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
30 %define DSC_OFFSET 0xfb00
31 %define DSC_GDTPTR 0x30
32 %define DSC_GDTSIZ 0x38
36 %define DSC_OTHERSEG 20
38 %define PROTECT_MODE_CS 0x8
39 %define PROTECT_MODE_DS 0x20
40 %define TSS_SEGMENT 0x40
42 extern ASM_PFX(SmiRendezvous)
43 extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
44 extern ASM_PFX(CpuSmmDebugEntry)
45 extern ASM_PFX(CpuSmmDebugExit)
47 global ASM_PFX(gcSmiHandlerTemplate)
48 global ASM_PFX(gcSmiHandlerSize)
49 global ASM_PFX(gPatchSmiCr3)
50 global ASM_PFX(gPatchSmiStack)
51 global ASM_PFX(gPatchSmbase)
52 extern ASM_PFX(mXdSupported)
53 global ASM_PFX(gPatchXdSupported)
54 extern ASM_PFX(gSmiHandlerIdtr)
59 ASM_PFX(gcSmiHandlerTemplate):
61 mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
62 mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
65 mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
67 mov ebp, eax ; ebp = GDT base
68 o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
69 mov ax, PROTECT_MODE_CS
71 mov edi, strict dword 0 ; source operand will be patched
72 ASM_PFX(gPatchSmbase):
73 lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
86 mov ax, PROTECT_MODE_DS
92 mov esp, strict dword 0 ; source operand will be patched
93 ASM_PFX(gPatchSmiStack):
94 mov eax, ASM_PFX(gSmiHandlerIdtr)
99 mov eax, strict dword 0 ; source operand will be patched
100 ASM_PFX(gPatchSmiCr3):
103 ; Need to test for CR4 specific bit support
106 cpuid ; use CPUID to determine if specific CR4 bits are supported
107 xor eax, eax ; Clear EAX
108 test edx, BIT2 ; Check for DE capabilities
112 test edx, BIT6 ; Check for PAE capabilities
116 test edx, BIT7 ; Check for MCE capabilities
120 test edx, BIT24 ; Check for FXSR capabilities
124 test edx, BIT25 ; Check for SSE capabilities
127 .4: ; as cr4.PGE is not set here, refresh cr3
128 mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
130 cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
133 mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
138 ; enable NXE if supported
139 mov al, strict byte 1 ; source operand may be patched
140 ASM_PFX(gPatchXdSupported):
144 ; Check XD disable bit
146 mov ecx, MSR_IA32_MISC_ENABLE
148 push edx ; save MSR_IA32_MISC_ENABLE[63-32]
149 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
151 and dx, 0xFFFB ; clear XD Disable bit if it is set
156 or ax, MSR_EFER_XD ; enable NXE
164 or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
166 lea ebx, [edi + DSC_OFFSET]
167 mov ax, [ebx + DSC_DS]
169 mov ax, [ebx + DSC_OTHERSEG]
173 mov ax, [ebx + DSC_SS]
176 ; jmp _SmiHandler ; instruction is not needed
178 global ASM_PFX(SmiHandler)
180 mov ebx, [esp + 4] ; CPU Index
182 mov eax, ASM_PFX(CpuSmmDebugEntry)
187 mov eax, ASM_PFX(SmiRendezvous)
192 mov eax, ASM_PFX(CpuSmmDebugExit)
196 mov eax, ASM_PFX(mXdSupported)
200 pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
203 mov ecx, MSR_IA32_MISC_ENABLE
205 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
212 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
214 global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
215 ASM_PFX(PiSmmCpuSmiEntryFixupAddress):