2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef _CPU_PISMMCPUDXESMM_H_
16 #define _CPU_PISMMCPUDXESMM_H_
20 #include <Protocol/MpService.h>
21 #include <Protocol/SmmConfiguration.h>
22 #include <Protocol/SmmCpu.h>
23 #include <Protocol/SmmAccess2.h>
24 #include <Protocol/SmmCpuSaveState.h>
25 #include <Protocol/SmmReadyToLock.h>
26 #include <Protocol/SmmCpuService.h>
28 #include <Guid/AcpiS3Context.h>
30 #include <Library/BaseLib.h>
31 #include <Library/IoLib.h>
32 #include <Library/TimerLib.h>
33 #include <Library/SmmLib.h>
34 #include <Library/SynchronizationLib.h>
35 #include <Library/DebugLib.h>
36 #include <Library/BaseMemoryLib.h>
37 #include <Library/PcdLib.h>
38 #include <Library/CacheMaintenanceLib.h>
39 #include <Library/MtrrLib.h>
40 #include <Library/SmmCpuPlatformHookLib.h>
41 #include <Library/SmmServicesTableLib.h>
42 #include <Library/MemoryAllocationLib.h>
43 #include <Library/UefiBootServicesTableLib.h>
44 #include <Library/UefiRuntimeServicesTableLib.h>
45 #include <Library/DebugAgentLib.h>
46 #include <Library/HobLib.h>
47 #include <Library/LocalApicLib.h>
48 #include <Library/UefiCpuLib.h>
49 #include <Library/CpuExceptionHandlerLib.h>
50 #include <Library/ReportStatusCodeLib.h>
51 #include <Library/SmmCpuFeaturesLib.h>
52 #include <Library/PeCoffGetEntryPointLib.h>
54 #include <AcpiCpuData.h>
55 #include <CpuHotPlugData.h>
57 #include <Register/Cpuid.h>
59 #include "CpuService.h"
60 #include "SmmProfile.h"
63 // MSRs required for configuration of SMM Code Access Check
65 #define EFI_MSR_SMM_MCA_CAP 0x17D
66 #define SMM_CODE_ACCESS_CHK_BIT BIT58
68 #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0
69 #define SMM_CODE_CHK_EN_BIT BIT2
74 #define IA32_PG_P BIT0
75 #define IA32_PG_RW BIT1
76 #define IA32_PG_WT BIT3
77 #define IA32_PG_CD BIT4
78 #define IA32_PG_A BIT5
79 #define IA32_PG_PS BIT7
80 #define IA32_PG_PAT_2M BIT12
81 #define IA32_PG_PAT_4K IA32_PG_PS
82 #define IA32_PG_PMNT BIT62
83 #define IA32_PG_NX BIT63
86 // Size of Task-State Segment defined in IA32 Manual
89 #define TSS_X64_IST1_OFFSET 36
90 #define TSS_IA32_CR3_OFFSET 28
91 #define TSS_IA32_ESP_OFFSET 56
96 #define PROTECT_MODE_CODE_SEGMENT 0x08
97 #define LONG_MODE_CODE_SEGMENT 0x38
100 // The size 0x20 must be bigger than
101 // the size of template code of SmmInit. Currently,
102 // the size of SmmInit requires the 0x16 Bytes buffer
105 #define BACK_BUF_SIZE 0x20
107 #define EXCEPTION_VECTOR_NUMBER 0x20
109 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
111 typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS
;
112 #define ARRIVAL_EXCEPTION_BLOCKED 0x1
113 #define ARRIVAL_EXCEPTION_DELAYED 0x2
114 #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4
117 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
118 // Contains the SMM Configuration Protocols that is produced.
119 // Contains a mix of DXE and SMM contents. All the fields must be used properly.
121 #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')
126 EFI_HANDLE SmmCpuHandle
;
128 EFI_PROCESSOR_INFORMATION
*ProcessorInfo
;
129 SMM_CPU_OPERATION
*Operation
;
130 UINTN
*CpuSaveStateSize
;
133 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion
[1];
134 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext
;
135 EFI_SMM_ENTRY_POINT SmmCoreEntry
;
137 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration
;
138 } SMM_CPU_PRIVATE_DATA
;
140 extern SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
;
141 extern CPU_HOT_PLUG_DATA mCpuHotPlugData
;
142 extern UINTN mMaxNumberOfCpus
;
143 extern UINTN mNumberOfCpus
;
144 extern BOOLEAN mRestoreSmmConfigurationInS3
;
145 extern EFI_SMM_CPU_PROTOCOL mSmmCpu
;
148 /// The mode of the CPU at the time an SMI occurs
150 extern UINT8 mSmmSaveStateRegisterLma
;
154 // SMM CPU Protocol function prototypes.
158 Read information from the CPU save state.
160 @param This EFI_SMM_CPU_PROTOCOL instance
161 @param Width The number of bytes to read from the CPU save state.
162 @param Register Specifies the CPU register to read form the save state.
163 @param CpuIndex Specifies the zero-based index of the CPU save state
164 @param Buffer Upon return, this holds the CPU register value read from the save state.
166 @retval EFI_SUCCESS The register was read from Save State
167 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
168 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
174 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
176 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
182 Write data to the CPU save state.
184 @param This EFI_SMM_CPU_PROTOCOL instance
185 @param Width The number of bytes to read from the CPU save state.
186 @param Register Specifies the CPU register to write to the save state.
187 @param CpuIndex Specifies the zero-based index of the CPU save state
188 @param Buffer Upon entry, this holds the new CPU register value.
190 @retval EFI_SUCCESS The register was written from Save State
191 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
192 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
198 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
200 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
202 IN CONST VOID
*Buffer
206 Read a CPU Save State register on the target processor.
208 This function abstracts the differences that whether the CPU Save State register is in the
209 IA32 CPU Save State Map or X64 CPU Save State Map.
211 This function supports reading a CPU Save State register in SMBase relocation handler.
213 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
214 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
215 @param[in] Width The number of bytes to read from the CPU save state.
216 @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
218 @retval EFI_SUCCESS The register was read from Save State.
219 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
220 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
225 ReadSaveStateRegister (
227 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
233 Write value to a CPU Save State register on the target processor.
235 This function abstracts the differences that whether the CPU Save State register is in the
236 IA32 CPU Save State Map or X64 CPU Save State Map.
238 This function supports writing a CPU Save State register in SMBase relocation handler.
240 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
241 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
242 @param[in] Width The number of bytes to read from the CPU save state.
243 @param[in] Buffer Upon entry, this holds the new CPU register value.
245 @retval EFI_SUCCESS The register was written to Save State.
246 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
247 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.
252 WriteSaveStateRegister (
254 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
256 IN CONST VOID
*Buffer
268 extern IA32_FAR_ADDRESS gSmmJmpAddr
;
270 extern CONST UINT8 gcSmmInitTemplate
[];
271 extern CONST UINT16 gcSmmInitSize
;
272 extern UINT32 gSmmCr0
;
273 extern UINT32 gSmmCr3
;
274 extern UINT32 gSmmCr4
;
275 extern UINTN gSmmInitStack
;
278 Semaphore operation for all processor relocate SMMBase.
282 SmmRelocationSemaphoreComplete (
287 /// The type of SMM CPU Information
291 volatile EFI_AP_PROCEDURE Procedure
;
292 volatile VOID
*Parameter
;
294 volatile BOOLEAN Present
;
295 } SMM_CPU_DATA_BLOCK
;
298 SmmCpuSyncModeTradition
,
299 SmmCpuSyncModeRelaxedAp
,
305 // Pointer to an array. The array should be located immediately after this structure
306 // so that UC cache-ability can be set together.
308 SMM_CPU_DATA_BLOCK
*CpuData
;
309 volatile UINT32 Counter
;
310 volatile UINT32 BspIndex
;
311 volatile BOOLEAN InsideSmm
;
312 volatile BOOLEAN AllCpusInSync
;
313 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode
;
314 volatile BOOLEAN SwitchBsp
;
315 volatile BOOLEAN
*CandidateBsp
;
316 } SMM_DISPATCHER_MP_SYNC_DATA
;
323 #define SMM_PSD_OFFSET 0xfb00
326 UINT64 Signature
; // Offset 0x00
327 UINT16 Reserved1
; // Offset 0x08
328 UINT16 Reserved2
; // Offset 0x0A
329 UINT16 Reserved3
; // Offset 0x0C
330 UINT16 SmmCs
; // Offset 0x0E
331 UINT16 SmmDs
; // Offset 0x10
332 UINT16 SmmSs
; // Offset 0x12
333 UINT16 SmmOtherSegment
; // Offset 0x14
334 UINT16 Reserved4
; // Offset 0x16
335 UINT64 Reserved5
; // Offset 0x18
336 UINT64 Reserved6
; // Offset 0x20
337 UINT64 Reserved7
; // Offset 0x28
338 UINT64 SmmGdtPtr
; // Offset 0x30
339 UINT32 SmmGdtSize
; // Offset 0x38
340 UINT32 Reserved8
; // Offset 0x3C
341 UINT64 Reserved9
; // Offset 0x40
342 UINT64 Reserved10
; // Offset 0x48
343 UINT16 Reserved11
; // Offset 0x50
344 UINT16 Reserved12
; // Offset 0x52
345 UINT32 Reserved13
; // Offset 0x54
346 UINT64 MtrrBaseMaskPtr
; // Offset 0x58
347 } PROCESSOR_SMM_DESCRIPTOR
;
349 extern IA32_DESCRIPTOR gcSmiGdtr
;
350 extern IA32_DESCRIPTOR gcSmiIdtr
;
351 extern VOID
*gcSmiIdtrPtr
;
352 extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd
;
353 extern UINT64 gPhyMask
;
354 extern ACPI_CPU_DATA mAcpiCpuData
;
355 extern SMM_DISPATCHER_MP_SYNC_DATA
*mSmmMpSyncData
;
356 extern VOID
*mGdtForAp
;
357 extern VOID
*mIdtForAp
;
358 extern VOID
*mMachineCheckHandlerForAp
;
359 extern UINTN mSmmStackArrayBase
;
360 extern UINTN mSmmStackArrayEnd
;
361 extern UINTN mSmmStackSize
;
362 extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService
;
363 extern IA32_DESCRIPTOR gcSmiInitGdtr
;
366 Create 4G PageTable in SMRAM.
368 @param ExtraPages Additional page numbers besides for 4G memory
369 @return PageTable Address
379 Initialize global data for MP synchronization.
381 @param Stacks Base address of SMI stack buffer for all processors.
382 @param StackSize Stack size for each processor in SMM.
386 InitializeMpServiceData (
392 Initialize Timer for SMM AP Sync.
401 Start Timer for SMM AP Sync.
411 Check if the SMM AP Sync timer is timeout.
413 @param Timer The start timer from the begin.
423 Initialize IDT for SMM Stack Guard.
428 InitializeIDTSmmStackGuard (
434 Register the SMM Foundation entry point.
436 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
437 @param SmmEntryPoint SMM Foundation EntryPoint
439 @retval EFI_SUCCESS Successfully to register SMM foundation entry point
445 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL
*This
,
446 IN EFI_SMM_ENTRY_POINT SmmEntryPoint
450 Create PageTable for SMM use.
452 @return PageTable Address
461 Schedule a procedure to run on the specified CPU.
463 @param Procedure The address of the procedure to run
464 @param CpuIndex Target CPU number
465 @param ProcArguments The parameter to pass to the procedure
467 @retval EFI_INVALID_PARAMETER CpuNumber not valid
468 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
469 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
470 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
471 @retval EFI_SUCCESS - The procedure has been successfully scheduled
477 IN EFI_AP_PROCEDURE Procedure
,
479 IN OUT VOID
*ProcArguments OPTIONAL
483 Schedule a procedure to run on the specified CPU in a blocking fashion.
485 @param Procedure The address of the procedure to run
486 @param CpuIndex Target CPU Index
487 @param ProcArguments The parameter to pass to the procedure
489 @retval EFI_INVALID_PARAMETER CpuNumber not valid
490 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
491 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
492 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
493 @retval EFI_SUCCESS The procedure has been successfully scheduled
498 SmmBlockingStartupThisAp (
499 IN EFI_AP_PROCEDURE Procedure
,
501 IN OUT VOID
*ProcArguments OPTIONAL
505 Initialize MP synchronization data.
510 InitializeMpSyncData (
516 Find out SMRAM information including SMRR base and SMRR size.
518 @param SmrrBase SMRR base
519 @param SmrrSize SMRR size
524 OUT UINT32
*SmrrBase
,
529 The function is invoked before SMBASE relocation in S3 path to restores CPU status.
531 The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
532 and restores MTRRs for both BSP and APs.
541 The function is invoked after SMBASE relocation in S3 path to restores CPU status.
543 The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
544 data saved by normal boot path for both BSP and APs.
553 Page Fault handler for SMM use.
555 @param InterruptType Defines the type of interrupt or exception that
556 occurred on the processor.This parameter is processor architecture specific.
557 @param SystemContext A pointer to the processor context when
558 the interrupt occurred on the processor.
563 IN EFI_EXCEPTION_TYPE InterruptType
,
564 IN EFI_SYSTEM_CONTEXT SystemContext
568 Perform the remaining tasks.
572 PerformRemainingTasks (
577 Initialize MSR spin lock by MSR index.
579 @param MsrIndex MSR index value.
583 InitMsrSpinLockByIndex (
588 Hook return address of SMM Save State so that semaphore code
589 can be executed immediately after AP exits SMM to indicate to
590 the BSP that an AP has exited SMM after SMBASE relocation.
592 @param[in] CpuIndex The processor index.
593 @param[in] RebasedFlag A pointer to a flag that is set to TRUE
594 immediately after AP exits SMM.
600 IN
volatile BOOLEAN
*RebasedFlag
604 Configure SMM Code Access Check feature for all processors.
605 SMM Feature Control MSR will be locked after configuration.
608 ConfigSmmCodeAccessCheck (
613 Hook the code executed immediately after an RSM instruction on the currently
614 executing CPU. The mode of code executed immediately after RSM must be
615 detected, and the appropriate hook must be selected. Always clear the auto
616 HALT restart flag if it is set.
618 @param[in] CpuIndex The processor index for the currently
620 @param[in] CpuState Pointer to SMRAM Save State Map for the
621 currently executing CPU.
622 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
623 32-bit mode from 64-bit SMM.
624 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
627 @retval The value of the original instruction pointer before it was hooked.
634 SMRAM_SAVE_STATE_MAP
*CpuState
,
635 UINT64 NewInstructionPointer32
,
636 UINT64 NewInstructionPointer
640 Get the size of the SMI Handler in bytes.
642 @retval The size, in bytes, of the SMI Handler.
652 Install the SMI handler for the CPU specified by CpuIndex. This function
653 is called by the CPU that was elected as monarch during System Management
656 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
657 The value must be between 0 and the NumberOfCpus field
658 in the System Management System Table (SMST).
659 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
660 @param[in] SmiStack The stack to use when an SMI is processed by the
661 the CPU specified by CpuIndex.
662 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
663 processed by the CPU specified by CpuIndex.
664 @param[in] GdtBase The base address of the GDT to use when an SMI is
665 processed by the CPU specified by CpuIndex.
666 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
667 processed by the CPU specified by CpuIndex.
668 @param[in] IdtBase The base address of the IDT to use when an SMI is
669 processed by the CPU specified by CpuIndex.
670 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
671 processed by the CPU specified by CpuIndex.
672 @param[in] Cr3 The base address of the page tables to use when an SMI
673 is processed by the CPU specified by CpuIndex.
690 Search module name by input IP address and output it.
692 @param CallerIpAddress Caller instruction pointer.
697 IN UINTN CallerIpAddress