UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28
  29 #include <Library/BaseLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32 #include <Library/SynchronizationLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/PcdLib.h>
  36 #include <Library/CacheMaintenanceLib.h>
  37 #include <Library/MtrrLib.h>
  38 #include <Library/SmmCpuPlatformHookLib.h>
  39 #include <Library/SmmServicesTableLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/UefiRuntimeServicesTableLib.h>
  43 #include <Library/DebugAgentLib.h>
  44 #include <Library/HobLib.h>
  45 #include <Library/LocalApicLib.h>
  46 #include <Library/UefiCpuLib.h>
  47 #include <Library/CpuExceptionHandlerLib.h>
  48 #include <Library/ReportStatusCodeLib.h>
  49 #include <Library/SmmCpuFeaturesLib.h>
  50 #include <Library/PeCoffGetEntryPointLib.h>
  51
  52 #include <AcpiCpuData.h>
  53 #include <CpuHotPlugData.h>
  54
  55 #include <Register/Cpuid.h>
  56 #include <Register/Msr.h>
  57
  58 #include "CpuService.h"
  59 #include "SmmProfile.h"
  60
  61 //
  62 // MSRs required for configuration of SMM Code Access Check
  63 //
  64 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  65 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  66
  67 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  68 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  69
  70 ///
  71 /// Page Table Entry
  72 ///
  73 #define IA32_PG_P                   BIT0
  74 #define IA32_PG_RW                  BIT1
  75 #define IA32_PG_U                   BIT2
  76 #define IA32_PG_WT                  BIT3
  77 #define IA32_PG_CD                  BIT4
  78 #define IA32_PG_A                   BIT5
  79 #define IA32_PG_D                   BIT6
  80 #define IA32_PG_PS                  BIT7
  81 #define IA32_PG_PAT_2M              BIT12
  82 #define IA32_PG_PAT_4K              IA32_PG_PS
  83 #define IA32_PG_PMNT                BIT62
  84 #define IA32_PG_NX                  BIT63
  85
  86 #define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)
  87 //
  88 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
  89 // X64 PAE PDPTE does not have such restriction
  90 //
  91 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)
  92
  93 //
  94 // Size of Task-State Segment defined in IA32 Manual
  95 //
  96 #define TSS_SIZE              104
  97 #define TSS_X64_IST1_OFFSET   36
  98 #define TSS_IA32_CR3_OFFSET   28
  99 #define TSS_IA32_ESP_OFFSET   56
 100
 101 //
 102 // Code select value
 103 //
 104 #define PROTECT_MODE_CODE_SEGMENT          0x08
 105 #define LONG_MODE_CODE_SEGMENT             0x38
 106
 107 //
 108 // The size 0x20 must be bigger than
 109 // the size of template code of SmmInit. Currently,
 110 // the size of SmmInit requires the 0x16 Bytes buffer
 111 // at least.
 112 //
 113 #define BACK_BUF_SIZE  0x20
 114
 115 #define EXCEPTION_VECTOR_NUMBER     0x20
 116
 117 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 118
 119 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 120 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 121 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 122 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 123
 124 //
 125 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 126 // Contains the SMM Configuration Protocols that is produced.
 127 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 128 //
 129 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 130
 131 typedef struct {
 132   UINTN                           Signature;
 133
 134   EFI_HANDLE                      SmmCpuHandle;
 135
 136   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 137   SMM_CPU_OPERATION               *Operation;
 138   UINTN                           *CpuSaveStateSize;
 139   VOID                            **CpuSaveState;
 140
 141   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 142   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 143   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 144
 145   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 146 } SMM_CPU_PRIVATE_DATA;
 147
 148 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 149 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 150 extern UINTN                  mMaxNumberOfCpus;
 151 extern UINTN                  mNumberOfCpus;
 152 extern BOOLEAN                mRestoreSmmConfigurationInS3;
 153 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 154
 155 ///
 156 /// The mode of the CPU at the time an SMI occurs
 157 ///
 158 extern UINT8  mSmmSaveStateRegisterLma;
 159
 160
 161 //
 162 // SMM CPU Protocol function prototypes.
 163 //
 164
 165 /**
 166   Read information from the CPU save state.
 167
 168   @param  This      EFI_SMM_CPU_PROTOCOL instance
 169   @param  Width     The number of bytes to read from the CPU save state.
 170   @param  Register  Specifies the CPU register to read form the save state.
 171   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 172   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 173
 174   @retval EFI_SUCCESS   The register was read from Save State
 175   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 176   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 177
 178 **/
 179 EFI_STATUS
 180 EFIAPI
 181 SmmReadSaveState (
 182   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 183   IN UINTN                              Width,
 184   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 185   IN UINTN                              CpuIndex,
 186   OUT VOID                              *Buffer
 187   );
 188
 189 /**
 190   Write data to the CPU save state.
 191
 192   @param  This      EFI_SMM_CPU_PROTOCOL instance
 193   @param  Width     The number of bytes to read from the CPU save state.
 194   @param  Register  Specifies the CPU register to write to the save state.
 195   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 196   @param  Buffer    Upon entry, this holds the new CPU register value.
 197
 198   @retval EFI_SUCCESS   The register was written from Save State
 199   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 200   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 201
 202 **/
 203 EFI_STATUS
 204 EFIAPI
 205 SmmWriteSaveState (
 206   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 207   IN UINTN                              Width,
 208   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 209   IN UINTN                              CpuIndex,
 210   IN CONST VOID                         *Buffer
 211   );
 212
 213 /**
 214 Read a CPU Save State register on the target processor.
 215
 216 This function abstracts the differences that whether the CPU Save State register is in the
 217 IA32 CPU Save State Map or X64 CPU Save State Map.
 218
 219 This function supports reading a CPU Save State register in SMBase relocation handler.
 220
 221 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 222 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 223 @param[in]  Width          The number of bytes to read from the CPU save state.
 224 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 225
 226 @retval EFI_SUCCESS           The register was read from Save State.
 227 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 228 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 229
 230 **/
 231 EFI_STATUS
 232 EFIAPI
 233 ReadSaveStateRegister (
 234   IN UINTN                        CpuIndex,
 235   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 236   IN UINTN                        Width,
 237   OUT VOID                        *Buffer
 238   );
 239
 240 /**
 241 Write value to a CPU Save State register on the target processor.
 242
 243 This function abstracts the differences that whether the CPU Save State register is in the
 244 IA32 CPU Save State Map or X64 CPU Save State Map.
 245
 246 This function supports writing a CPU Save State register in SMBase relocation handler.
 247
 248 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 249 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 250 @param[in] Width          The number of bytes to read from the CPU save state.
 251 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 252
 253 @retval EFI_SUCCESS           The register was written to Save State.
 254 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 255 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 256
 257 **/
 258 EFI_STATUS
 259 EFIAPI
 260 WriteSaveStateRegister (
 261   IN UINTN                        CpuIndex,
 262   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 263   IN UINTN                        Width,
 264   IN CONST VOID                   *Buffer
 265   );
 266
 267 //
 268 //
 269 //
 270 typedef struct {
 271   UINT32                            Offset;
 272   UINT16                            Segment;
 273   UINT16                            Reserved;
 274 } IA32_FAR_ADDRESS;
 275
 276 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 277
 278 extern CONST UINT8                  gcSmmInitTemplate[];
 279 extern CONST UINT16                 gcSmmInitSize;
 280 extern UINT32                       gSmmCr0;
 281 extern UINT32                       gSmmCr3;
 282 extern UINT32                       gSmmCr4;
 283 extern UINTN                        gSmmInitStack;
 284
 285 /**
 286   Semaphore operation for all processor relocate SMMBase.
 287 **/
 288 VOID
 289 EFIAPI
 290 SmmRelocationSemaphoreComplete (
 291   VOID
 292   );
 293
 294 ///
 295 /// The type of SMM CPU Information
 296 ///
 297 typedef struct {
 298   SPIN_LOCK                         *Busy;
 299   volatile EFI_AP_PROCEDURE         Procedure;
 300   volatile VOID                     *Parameter;
 301   volatile UINT32                   *Run;
 302   volatile BOOLEAN                  *Present;
 303 } SMM_CPU_DATA_BLOCK;
 304
 305 typedef enum {
 306   SmmCpuSyncModeTradition,
 307   SmmCpuSyncModeRelaxedAp,
 308   SmmCpuSyncModeMax
 309 } SMM_CPU_SYNC_MODE;
 310
 311 typedef struct {
 312   //
 313   // Pointer to an array. The array should be located immediately after this structure
 314   // so that UC cache-ability can be set together.
 315   //
 316   SMM_CPU_DATA_BLOCK            *CpuData;
 317   volatile UINT32               *Counter;
 318   volatile UINT32               BspIndex;
 319   volatile BOOLEAN              *InsideSmm;
 320   volatile BOOLEAN              *AllCpusInSync;
 321   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 322   volatile BOOLEAN              SwitchBsp;
 323   volatile BOOLEAN              *CandidateBsp;
 324 } SMM_DISPATCHER_MP_SYNC_DATA;
 325
 326 #define MSR_SPIN_LOCK_INIT_NUM 15
 327
 328 typedef struct {
 329   SPIN_LOCK    *SpinLock;
 330   UINT32       MsrIndex;
 331 } MP_MSR_LOCK;
 332
 333 #define SMM_PSD_OFFSET              0xfb00
 334
 335 typedef struct {
 336   UINT64                            Signature;              // Offset 0x00
 337   UINT16                            Reserved1;              // Offset 0x08
 338   UINT16                            Reserved2;              // Offset 0x0A
 339   UINT16                            Reserved3;              // Offset 0x0C
 340   UINT16                            SmmCs;                  // Offset 0x0E
 341   UINT16                            SmmDs;                  // Offset 0x10
 342   UINT16                            SmmSs;                  // Offset 0x12
 343   UINT16                            SmmOtherSegment;        // Offset 0x14
 344   UINT16                            Reserved4;              // Offset 0x16
 345   UINT64                            Reserved5;              // Offset 0x18
 346   UINT64                            Reserved6;              // Offset 0x20
 347   UINT64                            Reserved7;              // Offset 0x28
 348   UINT64                            SmmGdtPtr;              // Offset 0x30
 349   UINT32                            SmmGdtSize;             // Offset 0x38
 350   UINT32                            Reserved8;              // Offset 0x3C
 351   UINT64                            Reserved9;              // Offset 0x40
 352   UINT64                            Reserved10;             // Offset 0x48
 353   UINT16                            Reserved11;             // Offset 0x50
 354   UINT16                            Reserved12;             // Offset 0x52
 355   UINT32                            Reserved13;             // Offset 0x54
 356   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 357 } PROCESSOR_SMM_DESCRIPTOR;
 358
 359
 360 ///
 361 /// All global semaphores' pointer
 362 ///
 363 typedef struct {
 364   volatile UINT32      *Counter;
 365   volatile BOOLEAN     *InsideSmm;
 366   volatile BOOLEAN     *AllCpusInSync;
 367   SPIN_LOCK            *PFLock;
 368   SPIN_LOCK            *CodeAccessCheckLock;
 369   SPIN_LOCK            *MemoryMappedLock;
 370 } SMM_CPU_SEMAPHORE_GLOBAL;
 371
 372 ///
 373 /// All semaphores for each processor
 374 ///
 375 typedef struct {
 376   SPIN_LOCK                         *Busy;
 377   volatile UINT32                   *Run;
 378   volatile BOOLEAN                  *Present;
 379 } SMM_CPU_SEMAPHORE_CPU;
 380
 381 ///
 382 /// All MSRs semaphores' pointer and counter
 383 ///
 384 typedef struct {
 385   SPIN_LOCK            *Msr;
 386   UINTN                AvailableCounter;
 387 } SMM_CPU_SEMAPHORE_MSR;
 388
 389 ///
 390 /// All semaphores' information
 391 ///
 392 typedef struct {
 393   SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;
 394   SMM_CPU_SEMAPHORE_CPU             SemaphoreCpu;
 395   SMM_CPU_SEMAPHORE_MSR             SemaphoreMsr;
 396 } SMM_CPU_SEMAPHORES;
 397
 398 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 399 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 400 extern VOID                                *gcSmiIdtrPtr;
 401 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 402 extern UINT64                              gPhyMask;
 403 extern ACPI_CPU_DATA                       mAcpiCpuData;
 404 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 405 extern VOID                                *mGdtForAp;
 406 extern VOID                                *mIdtForAp;
 407 extern VOID                                *mMachineCheckHandlerForAp;
 408 extern UINTN                               mSmmStackArrayBase;
 409 extern UINTN                               mSmmStackArrayEnd;
 410 extern UINTN                               mSmmStackSize;
 411 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 412 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 413 extern SMM_CPU_SEMAPHORES                  mSmmCpuSemaphores;
 414 extern UINTN                               mSemaphoreSize;
 415 extern SPIN_LOCK                           *mPFLock;
 416 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;
 417 extern SPIN_LOCK                           *mMemoryMappedLock;
 418
 419 /**
 420   Create 4G PageTable in SMRAM.
 421
 422   @param          ExtraPages       Additional page numbers besides for 4G memory
 423   @param          Is32BitPageTable Whether the page table is 32-bit PAE
 424   @return         PageTable Address
 425
 426 **/
 427 UINT32
 428 Gen4GPageTable (
 429   IN      UINTN                     ExtraPages,
 430   IN      BOOLEAN                   Is32BitPageTable
 431   );
 432
 433
 434 /**
 435   Initialize global data for MP synchronization.
 436
 437   @param Stacks       Base address of SMI stack buffer for all processors.
 438   @param StackSize    Stack size for each processor in SMM.
 439
 440 **/
 441 UINT32
 442 InitializeMpServiceData (
 443   IN VOID        *Stacks,
 444   IN UINTN       StackSize
 445   );
 446
 447 /**
 448   Initialize Timer for SMM AP Sync.
 449
 450 **/
 451 VOID
 452 InitializeSmmTimer (
 453   VOID
 454   );
 455
 456 /**
 457   Start Timer for SMM AP Sync.
 458
 459 **/
 460 UINT64
 461 EFIAPI
 462 StartSyncTimer (
 463   VOID
 464   );
 465
 466 /**
 467   Check if the SMM AP Sync timer is timeout.
 468
 469   @param Timer  The start timer from the begin.
 470
 471 **/
 472 BOOLEAN
 473 EFIAPI
 474 IsSyncTimerTimeout (
 475   IN      UINT64                    Timer
 476   );
 477
 478 /**
 479   Initialize IDT for SMM Stack Guard.
 480
 481 **/
 482 VOID
 483 EFIAPI
 484 InitializeIDTSmmStackGuard (
 485   VOID
 486   );
 487
 488 /**
 489   Initialize Gdt for all processors.
 490
 491   @param[in]   Cr3          CR3 value.
 492   @param[out]  GdtStepSize  The step size for GDT table.
 493
 494   @return GdtBase for processor 0.
 495           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 496 **/
 497 VOID *
 498 InitGdt (
 499   IN  UINTN  Cr3,
 500   OUT UINTN  *GdtStepSize
 501   );
 502
 503 /**
 504
 505   Register the SMM Foundation entry point.
 506
 507   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 508   @param          SmmEntryPoint     SMM Foundation EntryPoint
 509
 510   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 511
 512 **/
 513 EFI_STATUS
 514 EFIAPI
 515 RegisterSmmEntry (
 516   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 517   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 518   );
 519
 520 /**
 521   Create PageTable for SMM use.
 522
 523   @return     PageTable Address
 524
 525 **/
 526 UINT32
 527 SmmInitPageTable (
 528   VOID
 529   );
 530
 531 /**
 532   Schedule a procedure to run on the specified CPU.
 533
 534   @param   Procedure        The address of the procedure to run
 535   @param   CpuIndex         Target CPU number
 536   @param   ProcArguments    The parameter to pass to the procedure
 537
 538   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 539   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 540   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 541   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 542   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 543
 544 **/
 545 EFI_STATUS
 546 EFIAPI
 547 SmmStartupThisAp (
 548   IN      EFI_AP_PROCEDURE          Procedure,
 549   IN      UINTN                     CpuIndex,
 550   IN OUT  VOID                      *ProcArguments OPTIONAL
 551   );
 552
 553 /**
 554   Schedule a procedure to run on the specified CPU in a blocking fashion.
 555
 556   @param  Procedure                The address of the procedure to run
 557   @param  CpuIndex                 Target CPU Index
 558   @param  ProcArguments            The parameter to pass to the procedure
 559
 560   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 561   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 562   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 563   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 564   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 565
 566 **/
 567 EFI_STATUS
 568 EFIAPI
 569 SmmBlockingStartupThisAp (
 570   IN      EFI_AP_PROCEDURE          Procedure,
 571   IN      UINTN                     CpuIndex,
 572   IN OUT  VOID                      *ProcArguments OPTIONAL
 573   );
 574
 575 /**
 576   Initialize MP synchronization data.
 577
 578 **/
 579 VOID
 580 EFIAPI
 581 InitializeMpSyncData (
 582   VOID
 583   );
 584
 585 /**
 586
 587   Find out SMRAM information including SMRR base and SMRR size.
 588
 589   @param          SmrrBase          SMRR base
 590   @param          SmrrSize          SMRR size
 591
 592 **/
 593 VOID
 594 FindSmramInfo (
 595   OUT UINT32   *SmrrBase,
 596   OUT UINT32   *SmrrSize
 597   );
 598
 599 /**
 600   The function is invoked before SMBASE relocation in S3 path to restores CPU status.
 601
 602   The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
 603   and restores MTRRs for both BSP and APs.
 604
 605 **/
 606 VOID
 607 EarlyInitializeCpu (
 608   VOID
 609   );
 610
 611 /**
 612   The function is invoked after SMBASE relocation in S3 path to restores CPU status.
 613
 614   The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
 615   data saved by normal boot path for both BSP and APs.
 616
 617 **/
 618 VOID
 619 InitializeCpu (
 620   VOID
 621   );
 622
 623 /**
 624   Page Fault handler for SMM use.
 625
 626   @param  InterruptType    Defines the type of interrupt or exception that
 627                            occurred on the processor.This parameter is processor architecture specific.
 628   @param  SystemContext    A pointer to the processor context when
 629                            the interrupt occurred on the processor.
 630 **/
 631 VOID
 632 EFIAPI
 633 SmiPFHandler (
 634     IN EFI_EXCEPTION_TYPE   InterruptType,
 635     IN EFI_SYSTEM_CONTEXT   SystemContext
 636   );
 637
 638 /**
 639   Perform the remaining tasks.
 640
 641 **/
 642 VOID
 643 PerformRemainingTasks (
 644   VOID
 645   );
 646
 647 /**
 648   Perform the pre tasks.
 649
 650 **/
 651 VOID
 652 PerformPreTasks (
 653   VOID
 654   );
 655
 656 /**
 657   Initialize MSR spin lock by MSR index.
 658
 659   @param  MsrIndex       MSR index value.
 660
 661 **/
 662 VOID
 663 InitMsrSpinLockByIndex (
 664   IN UINT32      MsrIndex
 665   );
 666
 667 /**
 668   Hook return address of SMM Save State so that semaphore code
 669   can be executed immediately after AP exits SMM to indicate to
 670   the BSP that an AP has exited SMM after SMBASE relocation.
 671
 672   @param[in] CpuIndex     The processor index.
 673   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 674                           immediately after AP exits SMM.
 675
 676 **/
 677 VOID
 678 SemaphoreHook (
 679   IN UINTN             CpuIndex,
 680   IN volatile BOOLEAN  *RebasedFlag
 681   );
 682
 683 /**
 684 Configure SMM Code Access Check feature for all processors.
 685 SMM Feature Control MSR will be locked after configuration.
 686 **/
 687 VOID
 688 ConfigSmmCodeAccessCheck (
 689   VOID
 690   );
 691
 692 /**
 693   Hook the code executed immediately after an RSM instruction on the currently
 694   executing CPU.  The mode of code executed immediately after RSM must be
 695   detected, and the appropriate hook must be selected.  Always clear the auto
 696   HALT restart flag if it is set.
 697
 698   @param[in] CpuIndex                 The processor index for the currently
 699                                       executing CPU.
 700   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 701                                       currently executing CPU.
 702   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 703                                       32-bit mode from 64-bit SMM.
 704   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 705                                       same mode as SMM.
 706
 707   @retval The value of the original instruction pointer before it was hooked.
 708
 709 **/
 710 UINT64
 711 EFIAPI
 712 HookReturnFromSmm (
 713   IN UINTN              CpuIndex,
 714   SMRAM_SAVE_STATE_MAP  *CpuState,
 715   UINT64                NewInstructionPointer32,
 716   UINT64                NewInstructionPointer
 717   );
 718
 719 /**
 720   Get the size of the SMI Handler in bytes.
 721
 722   @retval The size, in bytes, of the SMI Handler.
 723
 724 **/
 725 UINTN
 726 EFIAPI
 727 GetSmiHandlerSize (
 728   VOID
 729   );
 730
 731 /**
 732   Install the SMI handler for the CPU specified by CpuIndex.  This function
 733   is called by the CPU that was elected as monarch during System Management
 734   Mode initialization.
 735
 736   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 737                         The value must be between 0 and the NumberOfCpus field
 738                         in the System Management System Table (SMST).
 739   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 740   @param[in] SmiStack   The stack to use when an SMI is processed by the
 741                         the CPU specified by CpuIndex.
 742   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 743                         processed by the CPU specified by CpuIndex.
 744   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 745                         processed by the CPU specified by CpuIndex.
 746   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 747                         processed by the CPU specified by CpuIndex.
 748   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 749                         processed by the CPU specified by CpuIndex.
 750   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 751                         processed by the CPU specified by CpuIndex.
 752   @param[in] Cr3        The base address of the page tables to use when an SMI
 753                         is processed by the CPU specified by CpuIndex.
 754 **/
 755 VOID
 756 EFIAPI
 757 InstallSmiHandler (
 758   IN UINTN   CpuIndex,
 759   IN UINT32  SmBase,
 760   IN VOID    *SmiStack,
 761   IN UINTN   StackSize,
 762   IN UINTN   GdtBase,
 763   IN UINTN   GdtSize,
 764   IN UINTN   IdtBase,
 765   IN UINTN   IdtSize,
 766   IN UINT32  Cr3
 767   );
 768
 769 /**
 770   Search module name by input IP address and output it.
 771
 772   @param CallerIpAddress   Caller instruction pointer.
 773
 774 **/
 775 VOID
 776 DumpModuleInfoByIp (
 777   IN  UINTN              CallerIpAddress
 778   );
 779
 780 /**
 781   This API provides a way to allocate memory for page table.
 782
 783   This API can be called more once to allocate memory for page tables.
 784
 785   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 786   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 787   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 788   returned.
 789
 790   @param  Pages                 The number of 4 KB pages to allocate.
 791
 792   @return A pointer to the allocated buffer or NULL if allocation fails.
 793
 794 **/
 795 VOID *
 796 AllocatePageTableMemory (
 797   IN UINTN           Pages
 798   );
 799
 800 #endif