Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h

   1 /**
   2
   3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9   @file
  10   PchRegsUsb.h
  11
  12   @brief
  13   Register names for PCH USB devices.
  14
  15   Conventions:
  16
  17   - Prefixes:
  18     Definitions beginning with "R_" are registers
  19     Definitions beginning with "B_" are bits within registers
  20     Definitions beginning with "V_" are meaningful values of bits within the registers
  21     Definitions beginning with "S_" are register sizes
  22     Definitions beginning with "N_" are the bit position
  23   - In general, PCH registers are denoted by "_PCH_" in register names
  24   - Registers / bits that are different between PCH generations are denoted by
  25     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  26   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  27     at the end of the register/bit names
  28   - Registers / bits of new devices introduced in a PCH generation will be just named
  29     as "_PCH_" without <generation_name> inserted.
  30
  31 **/
  32 #ifndef _PCH_REGS_USB_H_
  33 #define _PCH_REGS_USB_H_
  34
  35 ///
  36 /// USB Definitions
  37 ///
  38
  39 typedef enum {
  40   PchEhci1 = 0,
  41   PchEhciControllerMax
  42 } PCH_USB20_CONTROLLER_TYPE;
  43
  44 #define PCH_USB_MAX_PHYSICAL_PORTS          4      /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.
  45 #define PCH_EHCI_MAX_PORTS                  4      /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.
  46 #define PCH_HSIC_MAX_PORTS                  2
  47 #define PCH_XHCI_MAX_USB3_PORTS             1
  48
  49 #define PCI_DEVICE_NUMBER_PCH_USB           29
  50 #define PCI_FUNCTION_NUMBER_PCH_EHCI        0
  51
  52 #define R_PCH_USB_VENDOR_ID                 0x00  // Vendor ID
  53 #define V_PCH_USB_VENDOR_ID                 V_PCH_INTEL_VENDOR_ID
  54
  55 #define R_PCH_USB_DEVICE_ID                 0x02  // Device ID
  56 #define V_PCH_USB_DEVICE_ID_0               0x0F34  // EHCI#1
  57
  58 #define R_PCH_EHCI_SVID                     0x2C  // USB2 Subsystem Vendor ID
  59 #define B_PCH_EHCI_SVID                     0xFFFF // USB2 Subsystem Vendor ID Mask
  60
  61 #define R_PCH_EHCI_PWR_CNTL_STS             0x54  // Power Management Control / Status
  62 #define B_PCH_EHCI_PWR_CNTL_STS_PME_STS     BIT15 // PME Status
  63 #define B_PCH_EHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13) // Data Scale
  64 #define B_PCH_EHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9) // Data Select
  65 #define B_PCH_EHCI_PWR_CNTL_STS_PME_EN      BIT8  // Power Enable
  66 #define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0) // Power State
  67 #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0  0     // D0 State
  68 #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0) // D3 Hot State
  69
  70 ///
  71 /// USB3 (XHCI) related definitions
  72 ///
  73 #define PCI_DEVICE_NUMBER_PCH_XHCI          20
  74 #define PCI_FUNCTION_NUMBER_PCH_XHCI        0
  75 //
  76 /////
  77 ///// XHCI PCI Config Space registers
  78 /////
  79
  80 #define R_PCH_XHCI_SVID                     0x2C
  81 #define B_PCH_XHCI_SVID                     0xFFFF
  82
  83
  84 #define R_PCH_XHCI_PWR_CNTL_STS             0x74
  85 #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS     BIT15
  86 #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13)
  87 #define B_PCH_XHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9)
  88 #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN      BIT8
  89 #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0)
  90 #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0)
  91
  92 #endif