Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c

   1 /** @file
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 Module Name:
  15
  16   MemoryCallback.c
  17
  18 Abstract:
  19
  20   EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.
  21
  22 --*/
  23
  24 #include "PlatformEarlyInit.h"
  25
  26
  27 VOID
  28 UpdateDefaultSetupValue (
  29   IN  EFI_PLATFORM_INFO_HOB       *PlatformInfo
  30   )
  31 {
  32 return;
  33 }
  34
  35 /**
  36   PEI termination callback.
  37
  38   @param PeiServices         General purpose services available to every PEIM.
  39   @param NotifyDescriptor    Not uesed.
  40   @param Ppi                 Not uesed.
  41
  42   @retval EFI_SUCCESS        If the interface could be successfully
  43                              installed.
  44
  45 **/
  46 EFI_STATUS
  47 EFIAPI
  48 EndOfPeiPpiNotifyCallback (
  49   IN CONST EFI_PEI_SERVICES           **PeiServices,
  50   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
  51   IN VOID                       *Ppi
  52   )
  53 {
  54   EFI_STATUS                  Status;
  55   UINT64                      LowUncableBase;
  56   EFI_PLATFORM_INFO_HOB       *PlatformInfo;
  57   UINT32                      HecBaseHigh;
  58   EFI_BOOT_MODE               BootMode;
  59   EFI_PEI_HOB_POINTERS        Hob;
  60
  61   Status = (*PeiServices)->GetBootMode(
  62                              PeiServices,
  63                              &BootMode
  64                              );
  65
  66   ASSERT_EFI_ERROR (Status);
  67
  68   //
  69   // Set the some PCI and chipset range as UC
  70   // And align to 1M at leaset
  71   //
  72   Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
  73   ASSERT (Hob.Raw != NULL);
  74   PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
  75
  76   UpdateDefaultSetupValue (PlatformInfo);
  77
  78   DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));
  79   DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));
  80   DEBUG (
  81     (EFI_D_ERROR,
  82     "PCIE   BASE: %lX     Size : %X\n",
  83     PlatformInfo->PciData.PciExpressBase,
  84     PlatformInfo->PciData.PciExpressSize)
  85     );
  86   DEBUG (
  87     (EFI_D_ERROR,
  88     "PCI32  BASE: %X     Limit: %X\n",
  89     PlatformInfo->PciData.PciResourceMem32Base,
  90     PlatformInfo->PciData.PciResourceMem32Limit)
  91     );
  92   DEBUG (
  93     (EFI_D_ERROR,
  94     "PCI64  BASE: %lX     Limit: %lX\n",
  95     PlatformInfo->PciData.PciResourceMem64Base,
  96     PlatformInfo->PciData.PciResourceMem64Limit)
  97     );
  98   DEBUG ((EFI_D_ERROR, "UC    START: %lX     End  : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));
  99
 100   LowUncableBase = PlatformInfo->MemData.MemMaxTolm;
 101   LowUncableBase &= (0x0FFF00000);
 102
 103   if (BootMode != BOOT_ON_S3_RESUME) {
 104     //
 105     // In BIOS, HECBASE will be always below 4GB
 106     //
 107     HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);
 108     ASSERT (HecBaseHigh < 16);
 109   }
 110
 111   return Status;
 112 }
 113
 114 /**
 115   Install Firmware Volume Hob's once there is main memory
 116
 117   @param PeiServices       General purpose services available to every PEIM.
 118   @param NotifyDescriptor  Notify that this module published.
 119   @param Ppi               PPI that was installed.
 120
 121   @retval EFI_SUCCESS     The function completed successfully.
 122
 123 **/
 124 EFI_STATUS
 125 EFIAPI
 126 MemoryDiscoveredPpiNotifyCallback (
 127   IN CONST EFI_PEI_SERVICES           **PeiServices,
 128   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
 129   IN VOID                       *Ppi
 130   )
 131 {
 132   EFI_STATUS                  Status;
 133   EFI_BOOT_MODE               BootMode;
 134   EFI_CPUID_REGISTER          FeatureInfo;
 135   UINT8                       CpuAddressWidth;
 136   UINT16                      Pm1Cnt;
 137   EFI_PEI_HOB_POINTERS        Hob;
 138   EFI_PLATFORM_INFO_HOB       *PlatformInfo;
 139   UINT32                      RootComplexBar;
 140   UINT32                      PmcBase;
 141   UINT32                      IoBase;
 142   UINT32                      IlbBase;
 143   UINT32                      SpiBase;
 144   UINT32                      MphyBase;
 145
 146   //
 147   // Get Platform Info HOB
 148   //
 149   Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
 150   ASSERT (Hob.Raw != NULL);
 151   PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
 152
 153   Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
 154
 155   //
 156   // Check if user wants to turn off in PEI phase
 157   //
 158   if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
 159     CheckPowerOffNow();
 160   } else {
 161     Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
 162     Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
 163     IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
 164   }
 165
 166   #ifndef MINNOW2_FSP_BUILD
 167   //
 168   // Set PEI cache mode here
 169   //
 170   SetPeiCacheMode (PeiServices);
 171   #endif
 172
 173   //
 174   //  Pulish memory tyoe info
 175   //
 176   PublishMemoryTypeInfo ();
 177
 178   //
 179   // Work done if on a S3 resume
 180   //
 181   if (BootMode == BOOT_ON_S3_RESUME) {
 182     //
 183     //Program the side band packet register to send a sideband message to Punit
 184     //To indicate that DRAM has been initialized and PUNIT FW base address in memory.
 185     //
 186     return EFI_SUCCESS;
 187   }
 188
 189   RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;
 190   BuildResourceDescriptorHob (
 191     EFI_RESOURCE_MEMORY_MAPPED_IO,
 192     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 193     RootComplexBar,
 194     0x1000
 195     );
 196   DEBUG ((EFI_D_INFO, "RootComplexBar     : 0x%x\n", RootComplexBar));
 197
 198   PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;
 199   BuildResourceDescriptorHob (
 200     EFI_RESOURCE_MEMORY_MAPPED_IO,
 201     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 202     PmcBase,
 203     0x1000
 204     );
 205   DEBUG ((EFI_D_INFO, "PmcBase            : 0x%x\n", PmcBase));
 206
 207   IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;
 208   BuildResourceDescriptorHob (
 209     EFI_RESOURCE_MEMORY_MAPPED_IO,
 210     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 211     IoBase,
 212     0x4000
 213     );
 214   DEBUG ((EFI_D_INFO, "IoBase             : 0x%x\n", IoBase));
 215
 216   IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;
 217   BuildResourceDescriptorHob (
 218     EFI_RESOURCE_MEMORY_MAPPED_IO,
 219     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 220     IlbBase,
 221     0x1000
 222     );
 223   DEBUG ((EFI_D_INFO, "IlbBase            : 0x%x\n", IlbBase));
 224
 225   SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;
 226   BuildResourceDescriptorHob (
 227     EFI_RESOURCE_MEMORY_MAPPED_IO,
 228     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 229     SpiBase,
 230     0x1000
 231     );
 232   DEBUG ((EFI_D_INFO, "SpiBase            : 0x%x\n", SpiBase));
 233
 234   MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;
 235   BuildResourceDescriptorHob (
 236     EFI_RESOURCE_MEMORY_MAPPED_IO,
 237     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 238     MphyBase,
 239     0x100000
 240     );
 241   DEBUG ((EFI_D_INFO, "MphyBase           : 0x%x\n", MphyBase));
 242
 243   //
 244   // Local APIC
 245   //
 246   BuildResourceDescriptorHob (
 247     EFI_RESOURCE_MEMORY_MAPPED_IO,
 248     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 249     LOCAL_APIC_ADDRESS,
 250     0x1000
 251   );
 252   DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));
 253
 254   //
 255   // IO APIC
 256   //
 257   BuildResourceDescriptorHob (
 258     EFI_RESOURCE_MEMORY_MAPPED_IO,
 259     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 260     IO_APIC_ADDRESS,
 261     0x1000
 262   );
 263   DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS    : 0x%x\n", IO_APIC_ADDRESS));
 264
 265   //
 266   // Adding the PCIE Express area to the E820 memory table as type 2 memory.
 267   //
 268   BuildResourceDescriptorHob (
 269     EFI_RESOURCE_MEMORY_MAPPED_IO,
 270     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 271     PlatformInfo->PciData.PciExpressBase,
 272     PlatformInfo->PciData.PciExpressSize
 273     );
 274   DEBUG ((EFI_D_INFO, "PciExpressBase     : 0x%x\n", PlatformInfo->PciData.PciExpressBase));
 275
 276   //
 277   // Adding the Flashpart to the E820 memory table as type 2 memory.
 278   //
 279   BuildResourceDescriptorHob (
 280     EFI_RESOURCE_FIRMWARE_DEVICE,
 281     (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
 282     FixedPcdGet32 (PcdFlashAreaBaseAddress),
 283     FixedPcdGet32 (PcdFlashAreaSize)
 284     );
 285   DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));
 286
 287   //
 288   // Create a CPU hand-off information
 289   //
 290   CpuAddressWidth = 32;
 291   AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
 292   if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {
 293     AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
 294     CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
 295   }
 296
 297   BuildCpuHob(CpuAddressWidth, 16);
 298   ASSERT_EFI_ERROR (Status);
 299
 300   return Status;
 301
 302 }
 303
 304
 305 EFI_STATUS
 306 ValidateFvHeader (
 307   IN EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader
 308   )
 309 {
 310   UINT16  *Ptr;
 311   UINT16  HeaderLength;
 312   UINT16  Checksum;
 313
 314   //
 315   // Verify the header revision, header signature, length
 316   // Length of FvBlock cannot be 2**64-1
 317   // HeaderLength cannot be an odd number
 318   //
 319   if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
 320       (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
 321       (FwVolHeader->FvLength == ((UINT64) -1)) ||
 322       ((FwVolHeader->HeaderLength & 0x01) != 0)
 323       ) {
 324     return EFI_NOT_FOUND;
 325   }
 326
 327   //
 328   // Verify the header checksum
 329   //
 330   HeaderLength  = (UINT16) (FwVolHeader->HeaderLength / 2);
 331   Ptr           = (UINT16 *) FwVolHeader;
 332   Checksum      = 0;
 333   while (HeaderLength > 0) {
 334     Checksum = *Ptr++;
 335     HeaderLength--;
 336   }
 337
 338   if (Checksum != 0) {
 339     return EFI_NOT_FOUND;
 340   }
 341
 342   return EFI_SUCCESS;
 343 }