Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c

   1 /** @file
   2
   3   Copyright (c) 2004  - 2016, Intel Corporation. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9
  10 Module Name:
  11
  12   PlatformEarlyInit.c
  13
  14 Abstract:
  15
  16   Do platform specific PEI stage initializations.
  17
  18 --*/
  19
  20
  21 #include "PlatformEarlyInit.h"
  22
  23 #ifdef __GNUC__
  24 #pragma GCC push_options
  25 #pragma GCC optimize ("O0")
  26 #else
  27 #pragma optimize ("", off)
  28 #endif
  29
  30
  31
  32 static EFI_PEI_STALL_PPI  mStallPpi = {
  33   PEI_STALL_RESOLUTION,
  34   Stall
  35 };
  36
  37 static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {
  38   EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  39   &gEfiPeiStallPpiGuid,
  40   &mStallPpi
  41 };
  42
  43 //
  44 // The reserved SMBus addresses are defined in PlatformDxe.h file.
  45 //
  46 static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
  47 static PEI_SMBUS_POLICY_PPI         mSmbusPolicyPpi = {
  48   SMBUS_BASE_ADDRESS,
  49   SMBUS_BUS_DEV_FUNC,
  50   PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,
  51   mSmbusRsvdAddresses
  52 };
  53
  54 static EFI_PEI_PPI_DESCRIPTOR       mInstallSmbusPolicyPpi = {
  55   EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  56   &gPeiSmbusPolicyPpiGuid,
  57   &mSmbusPolicyPpi
  58 };
  59 static PEI_SPEAKER_IF_PPI    mSpeakerInterfacePpi = {
  60   ProgramToneFrequency,
  61   GenerateBeepTone
  62 };
  63
  64 static EFI_PEI_PPI_DESCRIPTOR       mInstallSpeakerInterfacePpi = {
  65   EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  66   &gPeiSpeakerInterfacePpiGuid,
  67   &mSpeakerInterfacePpi
  68 };
  69
  70 static EFI_PEI_RESET_PPI            mResetPpi = { IchReset };
  71
  72
  73 static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {
  74   (EFI_PEI_FIND_FV_FINDFV)FindFv
  75 };
  76
  77 static EFI_PEI_PPI_DESCRIPTOR       mPpiList[] = {
  78   {
  79     EFI_PEI_PPI_DESCRIPTOR_PPI,
  80     &gEfiPeiMasterBootModePpiGuid,
  81     NULL
  82   },
  83   {
  84     EFI_PEI_PPI_DESCRIPTOR_PPI,
  85     &gEfiPeiResetPpiGuid,
  86     &mResetPpi
  87   },
  88   {
  89     (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  90     &gEfiFindFvPpiGuid,
  91     &mEfiFindFvPpi
  92   }
  93 };
  94
  95 static EFI_PEI_NOTIFY_DESCRIPTOR    mNotifyList[] = {
  96   {
  97     EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
  98     &gEfiEndOfPeiSignalPpiGuid,
  99     (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback
 100   },
 101   {
 102     (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
 103     &gEfiPeiMemoryDiscoveredPpiGuid,
 104     (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback
 105   }
 106
 107 };
 108
 109
 110 /**
 111
 112   Parse the status registers for figuring out the wake-up event and save it into
 113   an GUID HOB which will be referenced later. However, modification is required
 114   to meet the chipset register definition and the practical hardware design. Thus,
 115   this is just an example.
 116
 117
 118   @param PeiServices    pointer to the PEI Service Table
 119   @param EFI_SUCCESS    Always return Success
 120
 121   @retval None
 122
 123
 124 **/
 125 EFI_STATUS
 126 EFIAPI
 127 GetWakeupEventAndSaveToHob (
 128   IN CONST EFI_PEI_SERVICES   **PeiServices
 129   )
 130 {
 131   UINT16  Pm1Sts;
 132   UINTN   Gpe0Sts;
 133   UINTN   WakeEventData;
 134
 135   //
 136   // Read the ACPI registers
 137   //
 138   Pm1Sts  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
 139   Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
 140
 141   //
 142   // Figure out the wake-up event
 143   //
 144   if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
 145     WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
 146   } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
 147     WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
 148   } else if (Gpe0Sts != 0) {
 149     WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
 150   } else {
 151     WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
 152   }
 153
 154   DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
 155   DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));
 156
 157   return EFI_SUCCESS;
 158 }
 159
 160 EFI_STATUS
 161 GetSetupVariable (
 162   IN CONST EFI_PEI_SERVICES                **PeiServices,
 163   IN   SYSTEM_CONFIGURATION          *SystemConfiguration
 164   )
 165 {
 166   UINTN                        VariableSize;
 167   EFI_STATUS                   Status;
 168   EFI_PEI_READ_ONLY_VARIABLE2_PPI   *Variable;
 169
 170   VariableSize = sizeof (SYSTEM_CONFIGURATION);
 171   ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
 172
 173   Status = (*PeiServices)->LocatePpi (
 174                              PeiServices,
 175                              &gEfiPeiReadOnlyVariable2PpiGuid,
 176                              0,
 177                              NULL,
 178                                       (void **)&Variable
 179                              );
 180   ASSERT_EFI_ERROR (Status);
 181
 182   //
 183   // Use normal setup default from NVRAM variable,
 184   // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
 185   //
 186   VariableSize = sizeof(SYSTEM_CONFIGURATION);
 187   Status = Variable->GetVariable (
 188                        Variable,
 189                        L"Setup",
 190                        &gEfiSetupVariableGuid,
 191                        NULL,
 192                        &VariableSize,
 193                        SystemConfiguration
 194                        );
 195   if (EFI_ERROR (Status) || VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
 196     //The setup variable is corrupted
 197     VariableSize = sizeof(SYSTEM_CONFIGURATION);
 198     Status = Variable->GetVariable(
 199               Variable,
 200               L"SetupRecovery",
 201               &gEfiSetupVariableGuid,
 202               NULL,
 203               &VariableSize,
 204               SystemConfiguration
 205               );
 206     ASSERT_EFI_ERROR (Status);
 207   }
 208   return Status;
 209 }
 210
 211 EFI_STATUS
 212 VlvPolicyInit (
 213   IN CONST EFI_PEI_SERVICES             **PeiServices,
 214   IN SYSTEM_CONFIGURATION         *SystemConfiguration
 215   )
 216 {
 217   EFI_STATUS                      Status;
 218   EFI_PEI_PPI_DESCRIPTOR          *mVlvPolicyPpiDesc;
 219   VLV_POLICY_PPI                   *mVlvPolicyPpi;
 220
 221   Status = (*PeiServices)->AllocatePool(
 222                              PeiServices,
 223                              sizeof (EFI_PEI_PPI_DESCRIPTOR),
 224                              (void **)&mVlvPolicyPpiDesc
 225                              );
 226   ASSERT_EFI_ERROR (Status);
 227
 228   Status = (*PeiServices)->AllocatePool(
 229                              PeiServices,
 230                              sizeof (VLV_POLICY_PPI),
 231                              (void **)&mVlvPolicyPpi
 232                              );
 233   ASSERT_EFI_ERROR (Status);
 234
 235   //
 236   // Initialize PPI
 237   //
 238   (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);
 239   mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
 240   mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;
 241   mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;
 242   mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;
 243   mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;
 244   mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;
 245   mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;
 246   if (SystemConfiguration->PrimaryVideoAdaptor != 2) {
 247     mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;
 248   } else {
 249     mVlvPolicyPpi->GtConfig.InternalGraphics = 0;
 250   }
 251
 252
 253   mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;
 254
 255
 256   mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;
 257   mVlvPolicyPpi->PlatformData.DynSR = 1;
 258   DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));
 259   mVlvPolicyPpi->ISPEn                      = SystemConfiguration->ISPEn;
 260   DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));
 261   mVlvPolicyPpi->ISPPciDevConfig            = SystemConfiguration->ISPDevSel;
 262   if (SystemConfiguration->ISPEn == 0) {
 263     mVlvPolicyPpi->ISPPciDevConfig          = 0;
 264     DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));
 265   }
 266   Status = (*PeiServices)->InstallPpi(
 267                              PeiServices,
 268                              mVlvPolicyPpiDesc
 269                              );
 270   ASSERT_EFI_ERROR (Status);
 271
 272   return EFI_SUCCESS;
 273 }
 274
 275
 276 EFI_STATUS
 277 ConfigureSoCGpio (
 278   IN SYSTEM_CONFIGURATION  *SystemConfiguration
 279   )
 280 {
 281
 282     DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));
 283     if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode
 284      DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));
 285
 286      //
 287      //Silicon Steppings
 288      //
 289      switch (PchStepping()) {
 290        case PchA0:  // SOC A0 and A1
 291        case PchA1:
 292          DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
 293          SystemConfiguration->LpsseMMCEnabled            = 1;
 294          SystemConfiguration->LpsseMMC45Enabled          = 0;
 295          break;
 296        case PchB0:  // SOC B0 and later
 297        default:
 298          DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
 299          SystemConfiguration->LpsseMMCEnabled            = 0;
 300          SystemConfiguration->LpsseMMC45Enabled          = 1;
 301          break;
 302      }
 303     } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41
 304         DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));
 305         SystemConfiguration->LpsseMMCEnabled            = 1;
 306         SystemConfiguration->LpsseMMC45Enabled          = 0;
 307     } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5
 308          DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));
 309          SystemConfiguration->LpsseMMCEnabled            = 0;
 310          SystemConfiguration->LpsseMMC45Enabled          = 1;
 311
 312     } else { // Disable eMMC controllers
 313          DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));
 314          SystemConfiguration->LpsseMMCEnabled            = 0;
 315          SystemConfiguration->LpsseMMC45Enabled          = 0;
 316     }
 317
 318   /*
 319   20.1.1  EMMC
 320   SDMMC1_CLK -         write 0x2003ED01 to IOBASE + 0x03E0
 321   SDMMC1_CMD -        write 0x2003EC81 to IOBASE + 0x0390
 322   SDMMC1_D0 -           write 0x2003EC81 to IOBASE + 0x03D0
 323   SDMMC1_D1 -           write 0x2003EC81 to IOBASE + 0x0400
 324   SDMMC1_D2 -           write 0x2003EC81 to IOBASE + 0x03B0
 325   SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
 326   MMC1_D4_SD_WE -   write 0x2003EC81 to IOBASE + 0x0380
 327   MMC1_D5 -                write 0x2003EC81 to IOBASE + 0x03C0
 328   MMC1_D6 -                write 0x2003EC81 to IOBASE + 0x0370
 329   MMC1_D7 -                write 0x2003EC81 to IOBASE + 0x03F0
 330   MMC1_RESET_B -       write 0x2003ED01 to IOBASE + 0x0330
 331   */
 332   if (SystemConfiguration->LpsseMMCEnabled== 1) {
 333     MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
 334     MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
 335     MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
 336     MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
 337     MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
 338     MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
 339     MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
 340     MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
 341     MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
 342     MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
 343     MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);
 344   }
 345
 346   /*
 347   eMMC 4.5 controller
 348   SDMMC1_CLK -         write 0x2003ED03 to IOBASE + 0x03E0
 349   SDMMC1_CMD -        write 0x2003EC83 to IOBASE + 0x0390
 350   SDMMC1_D0 -           write 0x2003EC83 to IOBASE + 0x03D0
 351   SDMMC1_D1 -           write 0x2003EC83 to IOBASE + 0x0400
 352   SDMMC1_D2 -           write 0x2003EC83 to IOBASE + 0x03B0
 353   SDMMC1_D3_CD_B -  write 0x2003EC83 to IOBASE + 0x0360
 354   MMC1_D4_SD_WE -   write 0x2003EC83 to IOBASE + 0x0380
 355   MMC1_D5 -                write 0x2003EC83 to IOBASE + 0x03C0
 356   MMC1_D6 -                write 0x2003EC83 to IOBASE + 0x0370
 357   MMC1_D7 -                write 0x2003EC83 to IOBASE + 0x03F0
 358   MMC1_RESET_B -       write 0x2003ED03 to IOBASE + 0x0330
 359   */
 360   if (SystemConfiguration->LpsseMMC45Enabled== 1) {
 361     MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5
 362     MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);
 363     MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);
 364     MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);
 365     MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);
 366     MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);
 367     MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);
 368     MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);
 369     MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);
 370     MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);
 371     MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);
 372
 373   }
 374
 375 //
 376 // Change GPIOC_0 setting to allow MMIO access under Android.
 377 //
 378   IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
 379            (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));
 380   DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));
 381   return EFI_SUCCESS;
 382 }
 383
 384 EFI_STATUS
 385 MeasuredBootInit (
 386   IN CONST EFI_PEI_SERVICES        **PeiServices,
 387   IN SYSTEM_CONFIGURATION           *SystemConfiguration
 388   )
 389 {
 390   if (SystemConfiguration->MeasuredBootEnable) {
 391     PcdSetBool (PcdMeasuredBootEnable, TRUE);
 392   } else {
 393     PcdSetBool (PcdMeasuredBootEnable, FALSE);
 394   }
 395
 396   return EFI_SUCCESS;
 397 }
 398
 399
 400 EFI_STATUS
 401 ConfigureLpssAndSccGpio (
 402   IN SYSTEM_CONFIGURATION        *SystemConfiguration,
 403   IN EFI_PLATFORM_INFO_HOB       *PlatformInfo
 404   )
 405 {
 406   /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
 407   GPIO SCORE -  write 0x01001002 to IOBASE + 0x0700
 408   GPIO NCORE -  write 0x01001002 to IOBASE + 0x0F00
 409   GPIO SSUS -    write 0x01001002 to IOBASE + 0x1700
 410   */
 411     DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));
 412
 413   /*
 414   19.1.1  PWM0
 415   PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
 416   19.1.2  PWM1
 417   PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
 418   */
 419   if (SystemConfiguration->LpssPwm0Enabled== 1) {
 420     MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);
 421   } else if (SystemConfiguration->LpssPwm0Enabled== 0) {
 422     MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);
 423   }
 424
 425   if (SystemConfiguration->LpssPwm1Enabled== 1) {
 426     MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);
 427   } else if (SystemConfiguration->LpssPwm1Enabled== 0) {
 428     MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);
 429   }
 430
 431   /*
 432   19.1.3  UART1
 433   UART1_RXD-L -     write 0x2003CC81 to IOBASE + 0x0020
 434   UART1_TXD-0 -     write 0x2003CC81 to IOBASE + 0x0010
 435   UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
 436   UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
 437   */
 438   if (SystemConfiguration->LpssHsuart0Enabled== 1) {
 439     MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1
 440     MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);
 441   if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {
 442     DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));
 443     MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);
 444     MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);
 445   } else {
 446     DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));
 447     MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);
 448     MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
 449     }
 450   } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {
 451     MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1
 452     MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);
 453   }
 454
 455
 456   /*
 457   19.1.4  UART2
 458   UART2_RTS_B-1 -  write 0x2003CC81 to IOBASE + 0x0090
 459   UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
 460   UART2_RXD-H -    write 0x2003CC81 to IOBASE + 0x0060
 461   UART2_TXD-0 -     write 0x2003CC81 to IOBASE + 0x0070
 462   */
 463   if (SystemConfiguration->LpssHsuart1Enabled== 1) {
 464     MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);
 465     MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);
 466
 467   if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {
 468     DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));
 469     MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B
 470     MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B
 471   } else {
 472     DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));
 473     MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2
 474     MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
 475   }
 476   } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {
 477   MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);
 478   MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);
 479   }
 480
 481   /*
 482   19.1.5  SPI
 483   SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
 484   SPI1_CLK -     write 0x2003CD01 to IOBASE + 0x0100
 485   SPI1_MOSI -   write 0x2003CC81 to IOBASE + 0x0130
 486   SPI1_MISO -   write 0x2003CC81 to IOBASE + 0x0120
 487   */
 488   if (SystemConfiguration->LpssSpiEnabled== 1) {
 489     MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI
 490     MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);
 491     MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);
 492     MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);
 493   } else if (SystemConfiguration->LpssSpiEnabled== 0) {
 494     MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);
 495     MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);
 496     MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);
 497     MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);
 498   }
 499
 500   /*
 501   19.1.6  I2C0
 502   I2C0_SDA-OD-O -    write 0x2003CC81 to IOBASE + 0x0210
 503   I2C0_SCL-OD-O -    write 0x2003CC81 to IOBASE + 0x0200
 504   */
 505   if (SystemConfiguration->LpssI2C0Enabled== 1) {
 506     MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);
 507     MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);
 508   }
 509   /*
 510   19.1.7  I2C1
 511   I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
 512   I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
 513   */
 514
 515   if (SystemConfiguration->LpssI2C1Enabled== 1) {
 516     MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);
 517     MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);
 518   }
 519   /*
 520   19.1.8  I2C2
 521   I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
 522   I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
 523   */
 524   if (SystemConfiguration->LpssI2C2Enabled== 1) {
 525     MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);
 526     MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);
 527   }
 528   /*
 529   19.1.9  I2C3
 530   I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
 531   I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
 532   */
 533   if (SystemConfiguration->LpssI2C3Enabled== 1) {
 534     MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);
 535     MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);
 536   }
 537   /*
 538   19.1.10 I2C4
 539   I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
 540   I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
 541   */
 542   if (SystemConfiguration->LpssI2C4Enabled== 1) {
 543     MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);
 544     MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);
 545   }
 546   /*
 547   19.1.11 I2C5
 548   I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
 549   I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
 550   */
 551   //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
 552   if (SystemConfiguration->LpssI2C5Enabled== 1) {
 553     MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);
 554     MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);
 555   } else if(SystemConfiguration->LpssI2C5Enabled== 0) {
 556     MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);
 557     MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);
 558   }
 559   /*
 560   19.1.12 I2C6
 561   I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
 562   I2C6_SCL-OD-O/I -  write 0x2003CC81 to IOBASE + 0x0160
 563   */
 564   if (SystemConfiguration->LpssI2C6Enabled== 1) {
 565     MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);
 566     MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);
 567   } else if (SystemConfiguration->LpssI2C6Enabled== 0) {
 568     MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);
 569     MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);
 570   }
 571
 572
 573   /*
 574   20.1.2  SDIO
 575   SDMMC2_CLK -  write 0x2003ED01 to IOBASE + 0x0320
 576   SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
 577   SDMMC2_D0 -    write 0x2003EC81 to IOBASE + 0x0350
 578   SDMMC2_D1 -    write 0x2003EC81 to IOBASE + 0x02F0
 579   SDMMC2_D2 -    write 0x2003EC81 to IOBASE + 0x0340
 580   SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
 581   */
 582   if (SystemConfiguration->LpssSdioEnabled== 1) {
 583     MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO
 584     MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);
 585     MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);
 586     MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);
 587     MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);
 588     MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);
 589   }
 590
 591   /*
 592   20.1.3  SD Card
 593   SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
 594   SDMMC3_CD_B -    write 0x2003CC81 to IOBASE + 0x03A0
 595   SDMMC3_CLK -       write 0x2003CD01 to IOBASE + 0x02B0
 596   SDMMC3_CMD -      write 0x2003CC81 to IOBASE + 0x02C0
 597   SDMMC3_D0 -         write 0x2003CC81 to IOBASE + 0x02E0
 598   SDMMC3_D1 -         write 0x2003CC81 to IOBASE + 0x0290
 599   SDMMC3_D2 -         write 0x2003CC81 to IOBASE + 0x02D0
 600   SDMMC3_D3 -         write 0x2003CC81 to IOBASE + 0x02A0
 601   SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
 602   SDMMC3_WP -            write 0x2003CC82 to IOBASE + 0x0160
 603   */
 604   if (SystemConfiguration->LpssSdcardEnabled == 1) {
 605     if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {
 606       MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD
 607       MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);
 608       MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);
 609       MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);
 610       MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);
 611       MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);
 612       MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);
 613       MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);
 614       MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
 615      }
 616   }
 617
 618
 619      DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));
 620     return EFI_SUCCESS;
 621 }
 622
 623 EFI_STATUS
 624 ConfigureLpeGpio (
 625   IN SYSTEM_CONFIGURATION  *SystemConfiguration
 626   )
 627 {
 628   DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));
 629
 630   if (SystemConfiguration->PchAzalia == 0) {
 631     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));
 632     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));
 633     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));
 634     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));
 635     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));
 636     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));
 637     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));
 638     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));
 639   }
 640
 641   DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));
 642
 643   return EFI_SUCCESS;
 644 }
 645
 646 EFI_STATUS
 647 ConfigureSciSmiGpioRout (
 648   IN EFI_PLATFORM_INFO_HOB       *PlatformInfo)
 649 {
 650         UINT32  GPI_Routing;
 651
 652         GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);
 653
 654         //
 655         // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
 656         //
 657         if(PlatformInfo->BoardRev == 3) {
 658         GPI_Routing = GPI_Routing & 0xfffc3ffc;
 659         GPI_Routing = GPI_Routing | 0x00024002;
 660         }
 661
 662         //
 663         // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
 664         //
 665         else {
 666         GPI_Routing = GPI_Routing & 0x3fff3ffc;
 667         GPI_Routing = GPI_Routing | 0x80004002;
 668         }
 669         MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);
 670
 671         return EFI_SUCCESS;
 672 }
 673
 674 EFI_STATUS
 675 ConfigureMipiCsi (
 676   VOID)
 677 {
 678           //
 679     //Configure the platform clock for MIPI-CSI usage
 680     //PLT_CLK0
 681     //
 682     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));
 683
 684     //
 685     //PLT_CLK1
 686     //
 687     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));
 688
 689     //
 690     //PLT_CLK2
 691     //
 692     MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));
 693
 694     return EFI_SUCCESS;
 695 }
 696
 697 EFI_STATUS
 698 ConfigureUSBULPI (
 699   VOID)
 700 {
 701           //
 702     //Configure USB ULPI
 703     //USB_ULPI_0_CLK
 704     //
 705     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));
 706     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));
 707
 708     //
 709     //USB_ULPI_0_DATA0
 710     //
 711     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));
 712     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));
 713
 714     //
 715     //USB_ULPI_0_DATA1
 716     //
 717     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));
 718     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));
 719
 720     //
 721     //USB_ULPI_0_DATA2
 722     //
 723     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));
 724     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));
 725
 726     //
 727     //USB_ULPI_0_DATA3
 728     //
 729     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));
 730     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));
 731
 732     //
 733     //USB_ULPI_0_DATA4
 734     //
 735     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));
 736     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));
 737
 738     //
 739     //USB_ULPI_0_DATA5
 740     //
 741     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));
 742     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));
 743
 744     //
 745     //USB_ULPI_0_DATA6
 746     //
 747     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));
 748     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));
 749
 750     //
 751     //USB_ULPI_0_DATA7
 752     //
 753     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));
 754     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));
 755
 756     //
 757     //USB_ULPI_0_DIR
 758     //
 759     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));
 760     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));
 761
 762     //
 763     //USB_ULPI_0_NXT
 764     //
 765     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));
 766     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));
 767
 768     //
 769     //USB_ULPI_0_STP
 770     //
 771     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));
 772     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));
 773
 774     //
 775     //USB_ULPI_0_REFCLK
 776     //
 777     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));
 778     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));
 779
 780     return EFI_SUCCESS;
 781 }
 782
 783 EFI_STATUS
 784 DisableRTD3 (
 785   VOID)
 786 {
 787           //
 788     //Disable RTD3
 789     //
 790     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));
 791     MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));
 792
 793     return EFI_SUCCESS;
 794 }
 795
 796 /**
 797   Platform specific initializations in stage1.
 798
 799   @param FfsHeader         Pointer to the PEIM FFS file header.
 800   @param PeiServices       General purpose services available to every PEIM.
 801
 802   @retval EFI_SUCCESS       Operation completed successfully.
 803   @retval Otherwise         Platform initialization failed.
 804 **/
 805 EFI_STATUS
 806 EFIAPI
 807 PlatformEarlyInitEntry (
 808
 809   IN       EFI_PEI_FILE_HANDLE  FileHandle,
 810   IN CONST EFI_PEI_SERVICES    **PeiServices
 811   )
 812 {
 813   EFI_STATUS                  Status;
 814   SYSTEM_CONFIGURATION        SystemConfiguration;
 815   EFI_PLATFORM_INFO_HOB       *PlatformInfo;
 816   EFI_PEI_HOB_POINTERS        Hob;
 817   EFI_PLATFORM_CPU_INFO       PlatformCpuInfo;
 818   EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *DescriptorBlock;
 819   EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *NewDescriptorBlock;
 820   UINTN                           Index;
 821   UINTN                           MaxIndex;
 822   UINT64                          Base;
 823   UINT64                          Size;
 824   UINT64                          NewSize;
 825
 826   //
 827   // Make sure base and size of the SMRAM region is aligned
 828   //
 829   Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);
 830   if (Hob.Raw != NULL) {
 831     DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);
 832     DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB\n"));
 833     for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
 834       DEBUG((DEBUG_INFO, "  SMRAM Descriptor[%02x]: Start=%016lx  Size=%016lx  State=%02x\n",
 835         Index,
 836         DescriptorBlock->Descriptor[Index].PhysicalStart,
 837         DescriptorBlock->Descriptor[Index].PhysicalSize,
 838         DescriptorBlock->Descriptor[Index].RegionState
 839         ));
 840     }
 841
 842     //
 843     // Find the largest usable range of SMRAM between 1MB and 4GB
 844     //
 845     for (Index = 0, MaxIndex = 0, Size = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
 846       //
 847       // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
 848       //
 849       if ((DescriptorBlock->Descriptor[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
 850         continue;
 851       }
 852       //
 853       // Skip any SMRAM region below 1MB
 854       //
 855       if (DescriptorBlock->Descriptor[Index].CpuStart < BASE_1MB) {
 856         continue;
 857       }
 858       //
 859       // Skip any SMRAM region that is above 4GB or crosses the 4GB boundary
 860       //
 861       if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize) >= BASE_4GB) {
 862         continue;
 863       }
 864       //
 865       // Cache the largest SMRAM region index
 866       //
 867       if (DescriptorBlock->Descriptor[Index].PhysicalSize >= DescriptorBlock->Descriptor[MaxIndex].PhysicalSize) {
 868         MaxIndex = Index;
 869       }
 870     }
 871
 872     //
 873     // Find the extent of the contiguous SMRAM region that surrounds the largest usable SMRAM range
 874     //
 875     Base = DescriptorBlock->Descriptor[MaxIndex].CpuStart;
 876     Size = DescriptorBlock->Descriptor[MaxIndex].PhysicalSize;
 877     for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
 878       if (DescriptorBlock->Descriptor[Index].CpuStart < Base &&
 879           Base == (DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize)) {
 880         Base  = DescriptorBlock->Descriptor[Index].CpuStart;
 881         Size += DescriptorBlock->Descriptor[Index].PhysicalSize;
 882       } else if ((Base + Size) == DescriptorBlock->Descriptor[Index].CpuStart) {
 883         Size += DescriptorBlock->Descriptor[Index].PhysicalSize;
 884       }
 885     }
 886
 887     //
 888     // Round SMRAM region up to nearest power of 2 that is at least 4KB
 889     //
 890     NewSize = MAX (LShiftU64 (1, HighBitSet64 (Size - 1) + 1), SIZE_4KB);
 891     if ((Base & ~(NewSize - 1)) != Base) {
 892       //
 893       // SMRAM region Base Address has smaller alignment than SMRAM region Size
 894       // This is not compatible with SMRR settings
 895       //
 896       DEBUG((DEBUG_ERROR, "ERROR: SMRAM Region Size has larger alignment than SMRAM Region Base\n"));
 897       DEBUG((DEBUG_ERROR, "  SMRAM Region Base=%016lx  Size=%016lx\n", Base, NewSize));
 898       ASSERT (FALSE);
 899     } else if (Size != NewSize) {
 900       //
 901       // See if the size difference can be added to an adjacent descriptor that is already allocated
 902       //
 903       for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
 904         if ((DescriptorBlock->Descriptor[Index].CpuStart + DescriptorBlock->Descriptor[Index].PhysicalSize) == (Base + Size)) {
 905           if (((DescriptorBlock->Descriptor[Index].RegionState) & EFI_ALLOCATED) != 0) {
 906             DescriptorBlock->Descriptor[Index].PhysicalSize += (NewSize - Size);
 907             Size = NewSize;
 908             break;
 909           }
 910         }
 911       }
 912
 913       if (Size != NewSize) {
 914         //
 915         // Add an allocated descriptor to the SMM PEI SMRAM Memory Reserved HOB to accomodate the larger size.
 916         //
 917         Index = DescriptorBlock->NumberOfSmmReservedRegions;
 918         NewDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *)BuildGuidHob (
 919           &gEfiSmmPeiSmramMemoryReserveGuid,
 920           sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + ((Index + 1) * sizeof (EFI_SMRAM_DESCRIPTOR))
 921           );
 922         ASSERT (NewDescriptorBlock != NULL);
 923
 924         //
 925         // Copy old EFI_SMRAM_HOB_DESCRIPTOR_BLOCK to new allocated region
 926         //
 927         CopyMem (
 928           NewDescriptorBlock,
 929           DescriptorBlock,
 930           sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK) + (Index * sizeof (EFI_SMRAM_DESCRIPTOR))
 931           );
 932
 933         //
 934         // Make sure last descriptor in NewDescriptorBlock contains last descriptor from DescriptorBlock
 935         //
 936         CopyMem (
 937           &NewDescriptorBlock->Descriptor[Index],
 938           &NewDescriptorBlock->Descriptor[Index - 1],
 939           sizeof (EFI_SMRAM_DESCRIPTOR)
 940           );
 941
 942         //
 943         // Fill next to last descriptor with an allocated descriptor that aligns the total size of SMRAM
 944         //
 945         NewDescriptorBlock->Descriptor[Index - 1].CpuStart      = Base + Size;
 946         NewDescriptorBlock->Descriptor[Index - 1].PhysicalStart = Base + Size;
 947         NewDescriptorBlock->Descriptor[Index - 1].PhysicalSize  = NewSize - Size;
 948         NewDescriptorBlock->Descriptor[Index - 1].RegionState   = DescriptorBlock->Descriptor[MaxIndex].RegionState | EFI_ALLOCATED;
 949         NewDescriptorBlock->NumberOfSmmReservedRegions++;
 950
 951         //
 952         // Invalidate the original gEfiSmmPeiSmramMemoryReserveGuid HOB
 953         //
 954         ZeroMem (&Hob.Guid->Name, sizeof (&Hob.Guid->Name));
 955       }
 956
 957       Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);
 958       DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);
 959       DEBUG ((DEBUG_INFO, "SMM PEI SMRAM Memory Reserved HOB - Updated\n"));
 960       for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
 961         DEBUG((DEBUG_INFO, "  SMRAM Descriptor[%02x]: Start=%016lx  Size=%016lx  State=%02x\n",
 962           Index,
 963           DescriptorBlock->Descriptor[Index].PhysicalStart,
 964           DescriptorBlock->Descriptor[Index].PhysicalSize,
 965           DescriptorBlock->Descriptor[Index].RegionState
 966           ));
 967       }
 968     }
 969   }
 970
 971   //
 972   // Initialize SmbusPolicy PPI
 973   //
 974   Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);
 975   ASSERT_EFI_ERROR (Status);
 976
 977   //
 978   // Initialize Stall PPIs
 979   //
 980   Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);
 981   ASSERT_EFI_ERROR (Status);
 982
 983   //
 984   // Initialize platform PPIs
 985   //
 986   Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);
 987   ASSERT_EFI_ERROR (Status);
 988
 989   //
 990   // Variable initialization
 991   //
 992   ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
 993
 994   //
 995   // Set the some PCI and chipset range as UC
 996   // And align to 1M at leaset
 997   //
 998   Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
 999   ASSERT (Hob.Raw != NULL);
1000   PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
1001
1002   //
1003   // Initialize PlatformInfo HOB
1004   //
1005   MultiPlatformInfoInit(PeiServices, PlatformInfo);
1006
1007   //
1008   // Do basic MCH init
1009   //
1010   MchInit (PeiServices);
1011
1012   //
1013   // Set the new boot mode
1014   //
1015   Status = UpdateBootMode (PeiServices, PlatformInfo);
1016   ASSERT_EFI_ERROR (Status);
1017
1018   SetPlatformBootMode (PeiServices, PlatformInfo);
1019
1020   //
1021   // Get setup variable. This can only be done after BootMode is updated
1022   //
1023   GetSetupVariable (PeiServices, &SystemConfiguration);
1024
1025   CheckOsSelection(PeiServices, &SystemConfiguration);
1026
1027   //
1028   // Update PlatformInfo HOB according to setup variable
1029   //
1030   PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);
1031
1032   InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);
1033
1034   //
1035   // Initialize VlvPolicy PPI
1036   //
1037   Status = VlvPolicyInit (PeiServices, &SystemConfiguration);
1038   ASSERT_EFI_ERROR (Status);
1039
1040   //
1041   // Soc specific GPIO setting
1042   //
1043   ConfigureSoCGpio(&SystemConfiguration);
1044
1045   //
1046   //  Baylake Board specific.
1047   //
1048   if (PlatformInfo->BoardId == BOARD_ID_BL_RVP  ||
1049       PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||
1050             PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||
1051       PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||
1052       PlatformInfo->BoardId == BOARD_ID_BL_STHI ||
1053       PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
1054       PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
1055       PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
1056       PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||
1057       PlatformInfo->BoardId == BOARD_ID_CVH) {
1058     ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
1059
1060   }
1061
1062
1063   //
1064   //  Configure LPE
1065   //  Alpine Valley and Bayley Bay board specific
1066   //
1067   ConfigureLpeGpio(&SystemConfiguration);
1068
1069   //
1070   //  Bayley Bay Board specific.
1071   //
1072   ConfigureSciSmiGpioRout(PlatformInfo);
1073   if (SystemConfiguration.LpssI2C3Enabled == 1) {
1074     ConfigureMipiCsi();
1075   }
1076
1077
1078   //
1079   // Do basic CPU init
1080   //
1081   Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);
1082
1083   //
1084   // Perform basic SSA related platform initialization
1085   //
1086   PlatformSsaInit (&SystemConfiguration,PeiServices);
1087
1088
1089   //
1090   // Do basic PCH init
1091   //
1092   Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);
1093   ASSERT_EFI_ERROR (Status);
1094
1095   //
1096   // Initialize platform PPIs
1097   //
1098   Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
1099   ASSERT_EFI_ERROR (Status);
1100
1101   if (PlatformInfo->BoardId != BOARD_ID_CVH) {
1102     InstallPlatformClocksNotify (PeiServices);
1103     InstallPlatformSysCtrlGPIONotify(PeiServices);
1104   }
1105
1106   //
1107   // Initialize platform PPIs
1108   //
1109   Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
1110   ASSERT_EFI_ERROR (Status);
1111
1112   //
1113   // Initialize Measured Boot
1114   //
1115   Status = MeasuredBootInit (PeiServices, &SystemConfiguration);
1116   ASSERT_EFI_ERROR (Status);
1117
1118   return Status;
1119 }
1120
1121 /**
1122
1123   Return the mainblockcompact Fv.
1124
1125   @param FvNumber    Our enumeration of the firmware volumes we care about.
1126
1127   @param FvAddress  Base Address of the memory containing the firmware volume
1128
1129   @retval EFI_SUCCESS
1130   @retval EFI_NOT_FOUND
1131
1132 **/
1133 EFI_STATUS
1134 EFIAPI
1135 FindFv (
1136   IN EFI_PEI_FIND_FV_PPI          *This,
1137   IN CONST EFI_PEI_SERVICES             **PeiServices,
1138   IN OUT UINT8                    *FvNumber,
1139   OUT EFI_FIRMWARE_VOLUME_HEADER  **FVAddress
1140   )
1141 {
1142         //
1143   // At present, we only have one Fv to search
1144   //
1145   if (*FvNumber == 0) {
1146     *FvNumber = 1;
1147     *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);
1148     return EFI_SUCCESS;
1149   }
1150   else if (*FvNumber == 1) {
1151     *FvNumber = 2;
1152     *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);
1153     return EFI_SUCCESS;
1154   }
1155   else { // Not the one Fv we care about
1156     return EFI_NOT_FOUND;
1157   }
1158 }
1159
1160 EFI_STATUS
1161 EFIAPI
1162 CpuOnlyReset (
1163   IN CONST EFI_PEI_SERVICES   **PeiServices
1164   )
1165 {
1166 //  MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
1167 #ifdef __GNUC__
1168   __asm__
1169   (
1170    "xorl %ecx, %ecx\n"
1171    "1:hlt; hlt; hlt\n"
1172    "jmp 1b\n"
1173   );
1174 #else
1175   _asm {
1176     xor   ecx, ecx
1177   HltLoop:
1178     hlt
1179     hlt
1180     hlt
1181     loop  HltLoop
1182   }
1183 #endif
1184   //
1185   // If we get here we need to mark it as a failure.
1186   //
1187   return EFI_UNSUPPORTED;
1188 }
1189
1190
1191 #ifdef __GNUC__
1192 #pragma GCC pop_options
1193 #else
1194 #pragma optimize ("", on)
1195 #endif