Vlv2TbltDevicePkg/PlatformSmm/S3Save.c

   1 /** @file
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 Module Name:
  16
  17     IchS3Save.c
  18
  19 Abstract:
  20
  21     SMM S3 handler Driver implementation file
  22
  23 Revision History
  24
  25 **/
  26 #include "SmmPlatform.h"
  27
  28 extern  UINT16                          mAcpiBaseAddr;
  29 EFI_PHYSICAL_ADDRESS                    mRuntimeScriptTableBase;
  30
  31 EFI_STATUS
  32 InitRuntimeScriptTable (
  33   IN EFI_SYSTEM_TABLE  *SystemTable
  34   )
  35 {
  36   EFI_STATUS        Status;
  37   UINT32            VarAttrib;
  38   UINTN             VarSize;
  39   ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;
  40
  41   //
  42   // Allocate runtime ACPI script table space. We need it to save some
  43   // settings done by CSM, which runs after normal script table closed
  44   //
  45   Status = gBS->AllocatePages (
  46                   AllocateAnyPages,
  47                   EfiACPIReclaimMemory,
  48                   1,
  49                   &mRuntimeScriptTableBase
  50                   );
  51   if (EFI_ERROR(Status)) {
  52     return EFI_OUT_OF_RESOURCES ;
  53   }
  54
  55   //
  56   // Save runtime script table base into global ACPI variable
  57   //
  58   VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS
  59               | EFI_VARIABLE_NON_VOLATILE;
  60   VarSize   = sizeof (UINTN);
  61   Status = SystemTable->RuntimeServices->GetVariable (
  62                           ACPI_GLOBAL_VARIABLE,
  63                           &gEfiAcpiVariableCompatiblityGuid,
  64                           &VarAttrib,
  65                           &VarSize,
  66                           &AcpiVariableBase
  67                           );
  68   if (EFI_ERROR(Status)) {
  69     return Status;
  70   }
  71
  72   AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;
  73
  74   return EFI_SUCCESS;
  75 }
  76
  77 EFI_STATUS
  78 SaveRuntimeScriptTable (
  79   VOID
  80   )
  81 {
  82   SMM_PCI_IO_ADDRESS    PciAddress;
  83   UINT32                Data32;
  84   UINT16                Data16;
  85   UINT8                 Data8;
  86   UINT8                 Mask;
  87   UINTN                 Index;
  88   UINTN                 Offset;
  89   UINT8                 RegTable[] = {
  90
  91           //
  92     //Bus  ,   Dev,  Func,    DMI
  93           //
  94       0x00 ,  0x00,  0x00,
  95
  96           //
  97     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
  98           //
  99       0x00 ,  0x08,  0x00,  0x00,  0x30,  0x00,  0x00,  0xa0,
 100
 101           //
 102     //Bus  ,   Dev,  Func,    LPC device
 103           //
 104       0x00 ,  0x1F,  0x00,
 105
 106           //
 107     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 108     //
 109       0x00 ,  0x08,  0x00,  0x07,  0x00,  0x00,  0x90,  0x00,
 110
 111           //
 112     //Bus  ,   Dev,  Func,    PCIE device
 113          //
 114       0x00 ,  0x1C,  0x00,
 115
 116           //
 117     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 118     //
 119       0xC0 ,  0x83,  0x30,  0x00,  0x00,  0x00,  0x00,  0x00,
 120
 121           //
 122     //Bus  ,   Dev,  Func,    PCIE device
 123     //
 124           0x00 ,  0x1C,  0x00,
 125
 126           //
 127     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 128     //
 129       0x03 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
 130
 131           //
 132     //Bus  ,   Dev,  Func,    SATA device
 133           //
 134       0x00 ,  0x13,  0x00,
 135
 136           //
 137     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 138     //
 139       0xf4 ,  0xab,  0x27,  0x10,  0xf1,  0x1d,  0x00,  0x40,
 140
 141     //
 142     //Bus  ,   Dev,  Func,    EHCI device
 143     //
 144      0x00 ,  0x1D,  0x00,
 145
 146     //
 147     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 148     //
 149      0x10 ,  0x88,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,
 150
 151     //
 152     //Bus  ,   Dev,  Func,    SMBUS device
 153     //
 154      0x00 ,  0x1f,  0x03,
 155
 156     //
 157     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 158     //
 159       0x10 ,  0x89,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
 160
 161     //
 162     //Bus  ,   Dev,  Func,    SMBUS device
 163     //
 164       0x00 ,  0x1f,  0x03,
 165
 166     //
 167     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 168     //
 169       0x02 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
 170
 171     //
 172     //Bus  ,   Dev,  Func,    VGA bus1
 173     //
 174       0x01 ,  0x00,  0x00,
 175
 176     //
 177     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 178     //
 179       0x58 ,  0x81,  0x18,  0x01,  0xb0,  0x00,  0x00,  0x00,
 180
 181     //
 182     //Bus  ,   Dev,  Func,    VGA bus1
 183     //
 184       0x01 ,  0x00,  0x00,
 185
 186     //
 187     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 188     //
 189       0x02 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
 190
 191     //
 192     //Bus  ,   Dev,  Func,    VGA bus1 function 1
 193     //
 194       0x01 ,  0x00,  0x01,
 195
 196     //
 197     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 198     //
 199       0x51 ,  0x80,  0x80,  0x01,  0x00,  0x00,  0x00,  0x00,
 200
 201     //
 202     //Bus  ,   Dev,  Func,    VGA bus1 function 1
 203     //
 204       0x01 ,  0x00,  0x01,
 205
 206     //
 207     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 208     //
 209       0x02 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
 210
 211     //
 212     //Bus  ,   Dev,  Func,    IGD bus0 function 0
 213     //
 214       0x00 ,  0x02,  0x00,
 215
 216     //
 217     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 218     //
 219       0x42 ,  0x81,  0x00,  0x00,  0x00,  0x00,  0x20,  0x00,
 220
 221     //
 222     //Bus  ,   Dev,  Func,    USB bus0 function 0
 223     //
 224       0x00 ,  0x16,  0x00,
 225
 226     //
 227     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 228     //
 229       0x32 ,  0x80,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
 230
 231     //
 232     //Bus  ,   Dev,  Func,    HD Audio bus0 function 0
 233     //
 234       0x00 ,  0x1B,  0x00,
 235
 236     //
 237     //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
 238     //
 239       0x00 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x02,  0x00,
 240
 241     //
 242     //0xFF indicates the end of the table
 243     //
 244       0xFF
 245  };
 246
 247   //
 248   // These registers have to set in byte order
 249   //
 250   UINT8                 ExtReg[] = { 0x9E, 0x9D };  // SMRAM settings
 251
 252
 253
 254   //
 255   // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
 256   // and vital to S3 resume. That's why we put save code here
 257   //
 258   PciAddress.Bus      = 0;
 259   PciAddress.Device   = 0;
 260   PciAddress.Function = 0;
 261   PciAddress.ExtendedRegister = 0;
 262
 263   for (Index = 0; Index < 2; Index++) {
 264     //
 265     // Read SRAM setting from Pci(0, 0, 0)
 266     //
 267     PciAddress.Register = ExtReg[Index];
 268     Data8 = MmioRead8 (
 269               MmPciAddress (0,
 270                 PciAddress.Bus,
 271                 PciAddress.Device,
 272                 PciAddress.Function,
 273                 PciAddress.Register
 274               )
 275             );
 276
 277     //
 278     // Save latest settings to runtime script table
 279     //
 280     S3BootScriptSavePciCfgWrite(
 281       S3BootScriptWidthUint8,
 282       *(UINT64*)&PciAddress,
 283       1,
 284       &Data8
 285       );
 286   }
 287
 288
 289   //
 290   // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
 291   // and vital to S3 resume. That's why we put save code here
 292   //
 293   Index = 0;
 294   while (RegTable[Index] != 0xFF) {
 295
 296     PciAddress.Bus      = RegTable[Index++];
 297     PciAddress.Device   = RegTable[Index++];
 298     PciAddress.Function = RegTable[Index++];
 299     PciAddress.Register = 0;
 300     PciAddress.ExtendedRegister = 0;
 301
 302     Data16 = MmioRead16 (
 303               MmPciAddress (0,
 304                 PciAddress.Bus,
 305                 PciAddress.Device,
 306                 PciAddress.Function,
 307                 PciAddress.Register
 308               )
 309             );
 310
 311     if (Data16 == 0xFFFF) {
 312       Index+=8;
 313       continue;
 314     }
 315
 316     for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {
 317
 318       if (Mask == 0x00) {
 319         Mask = 0x01;
 320       }
 321
 322       if (RegTable[Index + Offset/32] & Mask ) {
 323
 324         PciAddress.Register = (UINT8)Offset;
 325         Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));
 326
 327         //
 328         // Save latest settings to runtime script table
 329         //
 330         S3BootScriptSavePciCfgWrite (
 331           S3BootScriptWidthUint32,
 332           *(UINT64*)&PciAddress,
 333           1,
 334           &Data32
 335         );
 336       }
 337     }
 338
 339     Index += 8;
 340
 341   }
 342
 343
 344   //
 345   // Save I/O ports to S3 script table
 346   //
 347
 348   //
 349   // Selftest KBC
 350   //
 351   Data8 = 0xAA;
 352   S3BootScriptSaveIoWrite (
 353     S3BootScriptWidthUint8,
 354     0x64,
 355     (UINTN)1,
 356     &Data8
 357     );
 358
 359   Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
 360
 361   S3BootScriptSaveIoWrite (
 362       S3BootScriptWidthUint32,
 363       (mAcpiBaseAddr + R_PCH_SMI_EN),
 364       1,
 365       &Data32
 366       );
 367
 368   //
 369   // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.
 370   //
 371   Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);
 372
 373   S3BootScriptSaveIoWrite (
 374       S3BootScriptWidthUint16,
 375       mAcpiBaseAddr + R_PCH_TCO_CNT,
 376       1,
 377       &Data16
 378       );
 379
 380
 381   return EFI_SUCCESS;
 382 }