MdePkg/PciExpress21.h: Fix the PCI industry standard register defines

[mirror_edk2.git] / MdePkg / Include / IndustryStandard / PciExpress21.h

diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index d4003de74cca9a165e0c2cfc195115799e2e2124..f17f570775536402ae8558ce3d03b37d0d28b924 100644 (file)
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -91,6 +91,24 @@ typedef union {
   UINT16   Uint16;\r
 } PCI_REG_PCIE_DEVICE_CONTROL;\r
 \r
   UINT16   Uint16;\r
 } PCI_REG_PCIE_DEVICE_CONTROL;\r
 \r

+#define PCIE_MAX_PAYLOAD_SIZE_128B   0\r
+#define PCIE_MAX_PAYLOAD_SIZE_256B   1\r
+#define PCIE_MAX_PAYLOAD_SIZE_512B   2\r
+#define PCIE_MAX_PAYLOAD_SIZE_1024B  3\r
+#define PCIE_MAX_PAYLOAD_SIZE_2048B  4\r
+#define PCIE_MAX_PAYLOAD_SIZE_4096B  5\r
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1  6\r
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2  7\r
+\r
+#define PCIE_MAX_READ_REQ_SIZE_128B    0\r
+#define PCIE_MAX_READ_REQ_SIZE_256B    1\r
+#define PCIE_MAX_READ_REQ_SIZE_512B    2\r
+#define PCIE_MAX_READ_REQ_SIZE_1024B   3\r
+#define PCIE_MAX_READ_REQ_SIZE_2048B   4\r
+#define PCIE_MAX_READ_REQ_SIZE_4096B   5\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1   6\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2   7\r
+\r

 typedef union {\r
   struct {\r
     UINT16 CorrectableError : 1;\r
 typedef union {\r
   struct {\r
     UINT16 CorrectableError : 1;\r


@@ -250,16 +268,30 @@ typedef union {
     UINT32 NoRoEnabledPrPrPassing : 1;\r
     UINT32 LtrMechanism : 1;\r
     UINT32 TphCompleter : 2;\r
     UINT32 NoRoEnabledPrPrPassing : 1;\r
     UINT32 LtrMechanism : 1;\r
     UINT32 TphCompleter : 2;\r

-    UINT32 Reserved : 4;\r
+    UINT32 LnSystemCLS : 2;\r
+    UINT32 TenBitTagCompleterSupported : 1;\r
+    UINT32 TenBitTagRequesterSupported : 1;\r

     UINT32 Obff : 2;\r
     UINT32 ExtendedFmtField : 1;\r
     UINT32 EndEndTlpPrefix : 1;\r
     UINT32 MaxEndEndTlpPrefixes : 2;\r
     UINT32 Obff : 2;\r
     UINT32 ExtendedFmtField : 1;\r
     UINT32 EndEndTlpPrefix : 1;\r
     UINT32 MaxEndEndTlpPrefixes : 2;\r

-    UINT32 Reserved2 : 8;\r
+    UINT32 EmergencyPowerReductionSupported : 2;\r
+    UINT32 EmergencyPowerReductionInitializationRequired : 1;\r
+    UINT32 Reserved3 : 4;\r
+    UINT32 FrsSupported : 1;\r

   } Bits;\r
   UINT32   Uint32;\r
 } PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
 \r
   } Bits;\r
   UINT32   Uint32;\r
 } PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
 \r

+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED           0\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED       1\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED       2\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED     3\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED     6\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED   7\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED   14\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r
+\r

 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1\r
 \r
 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1\r
 \r


@@ -273,7 +305,8 @@ typedef union {
     UINT16 IdoRequest : 1;\r
     UINT16 IdoCompletion : 1;\r
     UINT16 LtrMechanism : 2;\r
     UINT16 IdoRequest : 1;\r
     UINT16 IdoCompletion : 1;\r
     UINT16 LtrMechanism : 2;\r

-    UINT16 Reserved : 2;\r
+    UINT16 EmergencyPowerReductionRequest : 1;\r
+    UINT16 TenBitTagRequesterEnable : 1;\r

     UINT16 Obff : 2;\r
     UINT16 EndEndTlpPrefixBlocking : 1;\r
   } Bits;\r
     UINT16 Obff : 2;\r
     UINT16 EndEndTlpPrefixBlocking : 1;\r
   } Bits;\r