OvmfPkg/PlatformInitLib: Add PlatformGetLowMemoryCB

[mirror_edk2.git] / OvmfPkg / Library / PlatformInitLib / Platform.c

diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c
index 3e13c5d4b34febac873e4e2cf2f05aa4aef78c73..9ab0342fd8c0e81162c345dcc9482467082b3e0e 100644 (file)
--- a/OvmfPkg/Library/PlatformInitLib/Platform.c
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -128,7 +128,6 @@ PlatformMemMapInitialization (
 {\r
   UINT64  PciIoBase;\r
   UINT64  PciIoSize;\r
-  UINT32  TopOfLowRam;\r
   UINT64  PciExBarBase;\r
   UINT32  PciBase;\r
   UINT32  PciSize;\r
@@ -150,7 +149,7 @@ PlatformMemMapInitialization (
     return;\r
   }\r
 \r
-  TopOfLowRam  = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
+  PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
   PciExBarBase = 0;\r
   if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
     //\r
@@ -158,11 +157,11 @@ PlatformMemMapInitialization (
     // the base of the 32-bit PCI host aperture.\r
     //\r
     PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);\r
-    ASSERT (TopOfLowRam <= PciExBarBase);\r
+    ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase);\r
     ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
     PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
   } else {\r
-    ASSERT (TopOfLowRam <= PlatformInfoHob->Uc32Base);\r
+    ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base);\r
     PciBase = PlatformInfoHob->Uc32Base;\r
   }\r
 \r