\r
TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
PciExBarBase = 0;\r
- PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
ASSERT (TopOfLowRam <= PciExBarBase);\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
- PciSize = 0xFC000000 - PciBase;\r
} else {\r
- PciSize = 0xFC000000 - PciBase;\r
+ PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
}\r
\r
//\r
// 0xFED20000 gap 896 KB\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
+ PciSize = 0xFC000000 - PciBase;\r
AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r