+++ /dev/null
-/** @file\r
-CPU power management control methods\r
-\r
-Copyright (c) 2013-2015 Intel Corporation.\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-DefinitionBlock (\r
- "CPUPM.aml",\r
- "SSDT",\r
- 0x01,\r
- "SsgPmm",\r
- "CpuPm",\r
- 0x0010\r
- )\r
-{\r
- External(\_PR.CPU0, DeviceObj)\r
- External(CFGD, FieldUnitObj)\r
-\r
- Scope(\)\r
- {\r
- // Config DWord, modified during POST\r
- // Bit definitions are the same as PPMFlags:\r
- // CFGD[0] = PPM_GV3 = GV3\r
- // CFGD[1] = PPM_TURBO = Turbo Mode\r
- // CFGD[2] = PPM_SUPER_LFM = N/2 Ratio\r
- // CFGD[4] = PPM_C1 = C1 Capable, Enabled\r
- // CFGD[5] = PPM_C2 = C2 Capable, Enabled\r
- // CFGD[6] = PPM_C3 = C3 Capable, Enabled\r
- // CFGD[7] = PPM_C4 = C4 Capable, Enabled\r
- // CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled\r
- // CFGD[9] = PPM_C6 = C6 Capable, Enabled\r
- // CFGD[10] = PPM_C1E = C1E Enabled\r
- // CFGD[11] = PPM_C2E = C2E Enabled\r
- // CFGD[12] = PPM_C3E = C3E Enabled\r
- // CFGD[13] = PPM_C4E = C4E Enabled\r
- // CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled\r
- // CFGD[16] = PPM_TM1 = Thermal Monitor 1\r
- // CFGD[17] = PPM_TM2 = Thermal Monitor 2\r
- // CFGD[19] = PPM_PHOT = Bi-directional ProcHot\r
- // CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported\r
- // CFGD[24] = PPM_CMP = CMP supported, Enabled\r
- // CFGD[28] = PPM_TSTATE = CPU T states supported\r
- //\r
- // Name(CFGD, 0x80000000)\r
- // External Defined in GNVS\r
-\r
- Name(PDC0,0x80000000) // CPU0 _PDC Flags.\r
-\r
- // We load it in AcpiPlatform\r
- //Name(SSDT,Package()\r
- //{\r
- // "CPU0IST ", 0x80000000, 0x80000000,\r
- // "CPU1IST ", 0x80000000, 0x80000000,\r
- // "CPU0CST ", 0x80000000, 0x80000000,\r
- // "CPU1CST ", 0x80000000, 0x80000000,\r
- //})\r
- }\r
- Scope(\_PR.CPU0)\r
- {\r
- Method(_PDC, 1)\r
- {\r
- //\r
- // Store result of PDC.\r
- //\r
- CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.\r
- Store(CAP0,PDC0) // Store It in PDC0.\r
- }\r
- }\r
-\r
-}\r