+++ /dev/null
-/** @file\r
-Quark platform specific information.\r
-\r
-Copyright (c) 2013 Intel Corporation.\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-**/\r
-#include "Uefi.h"\r
-\r
-#ifndef __PLATFORM_H__\r
-#define __PLATFORM_H__\r
-\r
-//\r
-// Constant definition\r
-//\r
-#define MAX_SMRAM_RANGES 4\r
-#define MAX_NODE 1\r
-\r
-#define QUARK_STAGE1_IMAGE_TYPE_MASK 0xF0\r
-#define QUARK_STAGE1_BOOT_IMAGE_TYPE 0x00 // Stage1 Boot images 0x00 -> 0x0F.\r
-#define QUARK_STAGE1_RECOVERY_IMAGE_TYPE 0x10 // Stage1 Recovery images 0x10 -> 0x1F.\r
-\r
-#define QUARK_BOOTROM_BASE_ADDRESS 0xFFFE0000 // Base address of Quark ROM in memory map.\r
-#define QUARK_BOOTROM_SIZE_BYTES 0x20000 // Quark ROM is 128KB.\r
-#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address.\r
-#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM.\r
-\r
-//\r
-// Gpio to be used to assert / deassert PCI express PERST# signal.\r
-//\r
-#define PCIEXP_PERST_RESUMEWELL_GPIO 3\r
-\r
-//\r
-// Minimum time in microseconds for assertion of PERST# signal.\r
-//\r
-#define PCIEXP_PERST_MIN_ASSERT_US 100\r
-\r
-//\r
-// Microsecond delay post issueing common lane reset.\r
-//\r
-#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1\r
-\r
-//\r
-// Microsecond delay to wait for PLL to lock.\r
-//\r
-#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80\r
-\r
-//\r
-// Microsecond delay post issueing sideband interface reset.\r
-//\r
-#define PCIEXP_DELAY_US_POST_SBI_RESET 20\r
-\r
-//\r
-// Microsecond delay post deasserting PERST#.\r
-//\r
-#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10\r
-\r
-//\r
-// Catastrophic Trip point in degrees Celsius for this platform.\r
-//\r
-#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105\r
-\r
-//\r
-// Platform flash update LED common definitions.\r
-//\r
-#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7\r
-#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL.\r
-\r
-//\r
-// This structure stores the base and size of the ACPI reserved memory used when\r
-// resuming from S3. This region must be allocated by the platform code.\r
-//\r
-typedef struct {\r
- UINT32 AcpiReservedMemoryBase;\r
- UINT32 AcpiReservedMemorySize;\r
- UINT32 SystemMemoryLength;\r
-} RESERVED_ACPI_S3_RANGE;\r
-\r
-#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))\r
-\r
-//\r
-// Define valid platform types.\r
-// First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition\r
-// and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.\r
-// Value shown for supported platforms to help sanity checking with build tools\r
-// and ACPI method usage.\r
-//\r
-typedef enum {\r
- TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!!\r
- QuarkEmulation = 1,\r
- ClantonPeakSVP = 2,\r
- KipsBay = 3,\r
- CrossHill = 4,\r
- ClantonHill = 5,\r
- Galileo = 6,\r
- TypePlatformRsv7 = 7,\r
- GalileoGen2 = 8,\r
- TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!!\r
-} EFI_PLATFORM_TYPE;\r
-\r
-#define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \\r
- L"TypeUnknown",\\r
- L"QuarkEmulation",\\r
- L"ClantonPeakSVP",\\r
- L"KipsBay",\\r
- L"CrossHill",\\r
- L"ClantonHill",\\r
- L"Galileo",\\r
- L"TypePlatformRsv7",\\r
- L"GalileoGen2",\\r
-\r
-typedef struct {\r
- UINT32 EntryOffset;\r
- UINT8 ImageIndex;\r
-} QUARK_EDKII_STAGE1_HEADER;\r
-\r
-#endif\r