+++ /dev/null
-/** @file\r
-Board config definitions for each of the boards supported by this platform\r
-package.\r
-\r
-Copyright (c) 2013 Intel Corporation.\r
-\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-**/\r
-#include "Platform.h"\r
-\r
-#ifndef __PLATFORM_BOARDS_H__\r
-#define __PLATFORM_BOARDS_H__\r
-\r
-//\r
-// Constant definition\r
-//\r
-\r
-//\r
-// Default resume well TPM reset.\r
-//\r
-#define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5\r
-\r
-//\r
-// Basic Configs for GPIO table definitions.\r
-//\r
-#define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r
-#define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}\r
-#define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER\r
-#define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}\r
-#define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}\r
-#define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}\r
-#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}\r
-#define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}\r
-#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}\r
-\r
-#define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}\r
-#define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
-#define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
-#define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
-#define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r
-#define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0}\r
-#define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}\r
-#define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}\r
-#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r
-\r
-//\r
-// Legacy Gpio to be used to assert / deassert PCI express PERST# signal\r
-// on Galileo Gen 2 platform.\r
-//\r
-#define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0\r
-\r
-//\r
-// Io expander slave address.\r
-//\r
-\r
-//\r
-// On Galileo value of Jumper J2 determines slave address of io expander.\r
-//\r
-#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5\r
-#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20\r
-#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21\r
-\r
-//\r
-// Three IO Expmanders at fixed addresses on Galileo Gen2.\r
-//\r
-#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25\r
-#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26\r
-#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27\r
-\r
-//\r
-// Led GPIOs for flash update / recovery.\r
-//\r
-#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1\r
-#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5\r
-\r
-//\r
-// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.\r
-//\r
-typedef struct {\r
- UINT32 CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.\r
- UINT32 CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.\r
- UINT32 CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.\r
- UINT32 CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.\r
- UINT32 CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.\r
- UINT32 CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.\r
- UINT32 CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.\r
- UINT32 CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.\r
- UINT32 CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.\r
- UINT32 ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.\r
- UINT32 ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.\r
- UINT32 ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.\r
- UINT32 ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.\r
- UINT32 ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.\r
- UINT32 ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.\r
- UINT32 ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.\r
- UINT32 ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.\r
- UINT32 ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.\r
-} BOARD_LEGACY_GPIO_CONFIG;\r
-\r
-//\r
-// GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.\r
-//\r
-typedef struct {\r
- UINT32 PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.\r
- UINT32 PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.\r
- UINT32 IntEn; ///< Value for IOH REG GPIO_INTEN.\r
- UINT32 IntMask; ///< Value for IOH REG GPIO_INTMASK.\r
- UINT32 IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.\r
- UINT32 IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.\r
- UINT32 Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.\r
- UINT32 LsSync; ///< Value for IOH REG GPIO_LS_SYNC.\r
-} BOARD_GPIO_CONTROLLER_CONFIG;\r
-\r
-///\r
-/// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported\r
-/// by this platform package.\r
-/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
-///\r
-#define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \\r
- /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
- NULL_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
- QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
- CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - KipsBay*/\\r
- KIPS_BAY_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - CrossHill*/\\r
- CROSS_HILL_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - ClantonHill*/\\r
- CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - Galileo*/\\r
- GALILEO_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\\r
- NULL_LEGACY_GPIO_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
- GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\\r
-\r
-///\r
-/// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board\r
-/// supported by this platform package.\r
-/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
-///\r
-#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \\r
- /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
- NULL_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
- QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
- CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - KipsBay*/\\r
- KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - CrossHill*/\\r
- CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - ClantonHill*/\\r
- CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - Galileo*/\\r
- GALILEO_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\\r
- NULL_GPIO_CONTROLLER_INITIALIZER,\\r
- /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
- GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\\r
-\r
-#endif\r
projects / mirror_edk2.git / blobdiff