\r
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r
(c)Copyright 2016 HP Development Company, L.P.<BR>\r
-Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR>\r
+Copyright (c) Microsoft Corporation.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
//\r
// Operational region for Smi port access\r
//\r
- OperationRegion (SMIP, SystemIO, 0xB2, 1)\r
+ OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)\r
Field (SMIP, ByteAcc, NoLock, Preserve)\r
{\r
- IOB2, 8\r
+ IOPN, 8\r
}\r
\r
//\r
//\r
// Trigger the SMI interrupt\r
//\r
- Store (MCIN, IOB2)\r
+ Store (MCIN, IOPN)\r
}\r
}\r
Return (0)\r
//\r
// Trigger the SMI interrupt\r
//\r
- Store (PPIN, IOB2)\r
+ Store (PPIN, IOPN)\r
Return (FRET)\r
\r
\r
//\r
// Trigger the SMI interrupt\r
//\r
- Store (PPIN, IOB2)\r
+ Store (PPIN, IOPN)\r
\r
Store (LPPR, Index (TPM3, 0x01))\r
Store (PPRP, Index (TPM3, 0x02))\r
//\r
// Trigger the SMI interrupt\r
//\r
- Store (PPIN, IOB2)\r
+ Store (PPIN, IOPN)\r
Return (FRET)\r
}\r
Case (8)\r
//\r
// Trigger the SMI interrupt\r
//\r
- Store (PPIN, IOB2)\r
+ Store (PPIN, IOPN)\r
\r
Return (FRET)\r
}\r
//\r
// Trigger the SMI interrupt\r
//\r
- Store (MCIN, IOB2)\r
+ Store (MCIN, IOPN)\r
Return (MRET)\r
}\r
Default {BreakPoint}\r