UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuService.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index 40f2a1719d5b6fe39292375963ebf039b4438980..93ebb9ec73e807abdcc7483c2f522e22e78f7d15 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -26,125 +26,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
   SmmRegisterExceptionHandler\r
 };\r
 \r
-/**\r
-  Get Package ID/Core ID/Thread ID of a processor.\r
-\r
-  APIC ID must be an initial APIC ID.\r
-\r
-  The algorithm below assumes the target system has symmetry across physical package boundaries\r
-  with respect to the number of logical processors per package, number of cores per package.\r
-\r
-  @param  ApicId    APIC ID of the target logical processor.\r
-  @param  Location    Returns the processor location information.\r
-**/\r
-VOID\r
-SmmGetProcessorLocation (\r
-  IN UINT32 ApicId,\r
-  OUT EFI_CPU_PHYSICAL_LOCATION *Location\r
-  )\r
-{\r
-  UINTN   ThreadBits;\r
-  UINTN   CoreBits;\r
-  UINT32  RegEax;\r
-  UINT32  RegEbx;\r
-  UINT32  RegEcx;\r
-  UINT32  RegEdx;\r
-  UINT32  MaxCpuIdIndex;\r
-  UINT32  SubIndex;\r
-  UINTN   LevelType;\r
-  UINT32  MaxLogicProcessorsPerPackage;\r
-  UINT32  MaxCoresPerPackage;\r
-  BOOLEAN TopologyLeafSupported;\r
-\r
-  ASSERT (Location != NULL);\r
-\r
-  ThreadBits            = 0;\r
-  CoreBits              = 0;\r
-  TopologyLeafSupported = FALSE;\r
-\r
-  //\r
-  // Check if the processor is capable of supporting more than one logical processor.\r
-  //\r
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r
-  ASSERT ((RegEdx & BIT28) != 0);\r
-\r
-  //\r
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
-  //\r
-\r
-  //\r
-  // Get the max index of basic CPUID\r
-  //\r
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
-\r
-  //\r
-  // If the extended topology enumeration leaf is available, it\r
-  // is the preferred mechanism for enumerating topology.\r
-  //\r
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
-    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);\r
-    //\r
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
-    // supported on that processor.\r
-    //\r
-    if ((RegEbx & 0xffff) != 0) {\r
-      TopologyLeafSupported = TRUE;\r
-\r
-      //\r
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
-      // the SMT sub-field of x2APIC ID.\r
-      //\r
-      LevelType = (RegEcx >> 8) & 0xff;\r
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
-      if ((RegEbx & 0xffff) > 1 ) {\r
-        ThreadBits = RegEax & 0x1f;\r
-      } else {\r
-        //\r
-        // HT is not supported\r
-        //\r
-        ThreadBits = 0;\r
-      }\r
-\r
-      //\r
-      // Software must not assume any "level type" encoding\r
-      // value to be related to any sub-leaf index, except sub-leaf 0.\r
-      //\r
-      SubIndex = 1;\r
-      do {\r
-        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);\r
-        LevelType = (RegEcx >> 8) & 0xff;\r
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
-          CoreBits = (RegEax & 0x1f) - ThreadBits;\r
-          break;\r
-        }\r
-        SubIndex++;\r
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
-    }\r
-  }\r
-\r
-  if (!TopologyLeafSupported) {\r
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
-    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;\r
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);\r
-      MaxCoresPerPackage = (RegEax >> 26) + 1;\r
-    } else {\r
-      //\r
-      // Must be a single-core processor.\r
-      //\r
-      MaxCoresPerPackage = 1;\r
-    }\r
-\r
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
-  }\r
-\r
-  Location->Thread = ApicId & ~((-1) << ThreadBits);\r
-  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);\r
-  Location->Package = (ApicId >> (ThreadBits+ CoreBits));\r
-}\r
-\r
 /**\r
   Gets processor information on the requested processor at the instant this call is made.\r
 \r
@@ -280,7 +161,12 @@ SmmAddProcessor (
         gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;\r
       gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;\r
-      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);\r
+      GetProcessorLocation (\r
+        (UINT32)ProcessorId,\r
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,\r
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,\r
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread\r
+        );\r
 \r
       *ProcessorNumber = Index;\r
       gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;\r